src/alu.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use work.gen_pkg.all;
   5
   6 entity alu is
   7         port
   8         (
   9                 sys_clk : in std_logic;
  10                 sys_res_n : in std_logic;
  11                 opcode : in alu_ops;
  12                 op1 : in csigned;
  13                 op2 : in csigned;
  14                 op3 : out csigned;
  15                 opM : out csigned;
  16                 do_calc : in std_logic;
  17                 calc_done : out std_logic;
  18                 calc_error : out std_logic
  19         );
  20 end entity alu;
  21
  22 architecture beh of alu is
  23         type ALU_STATE is (SIDLE, SADD, SSUB, SMUL, SDIV, SDIV_CALC, SDONE, SERROR);
  24         signal state_int, state_next : ALU_STATE;
  25         signal done_intern, error_intern : std_logic;
  26         signal div_go_calc_int : std_logic;
  27         signal op3_int, op3_next, opM_int, opM_next : csigned;
  28         signal calc_done_int, calc_done_next : std_logic;
  29         signal calc_error_int, calc_error_next : std_logic;
  30         -- signale fuer division
  31         signal dividend_msb_int, dividend_msb_next, laengediv_int, laengediv_next : divinteger;
  32         signal quo_int, quo_next, aktdiv_int, aktdiv_int_next, op1_int, op1_next, op2_int, op2_next : csigned;
  33         signal sign_int, sign_next : std_logic;
  34 begin
  35         op3 <= op3_int;
  36         opM <= opM_int;
  37         calc_done <= calc_done_int;
  38         calc_error <= calc_error_int;
  39
  40         -- sync
  41         process(sys_clk, sys_res_n)
  42         begin
  43                 if sys_res_n = '0' then
  44                         state_int <= SIDLE;
  45                         op3_int <= (others => '0');
  46                         opM_int <= (others => '0');
  47                         calc_done_int <= '0';
  48                         calc_error_int <= '0';
  49                         --div
  50                         dividend_msb_int <= (others => '0');
  51                         laengediv_int <= (others => '0');
  52                         quo_int <= (others => '0');
  53                         aktdiv_int <= (others => '0');
  54                         op1_int <= (others => '0');
  55                         op2_int <= (others => '0');
  56                         sign_int <= '0';
  57                 elsif rising_edge(sys_clk) then
  58                         state_int <= state_next;
  59                         op3_int <= op3_next;
  60                         opM_int <= opM_next;
  61                         calc_done_int <= calc_done_next;
  62                         calc_error_int <= calc_error_next;
  63                         -- div
  64                         dividend_msb_int <= dividend_msb_next;
  65                         laengediv_int <= laengediv_next;
  66                         quo_int <= quo_next;
  67                         aktdiv_int <= aktdiv_int_next;
  68                         op1_int <= op1_next;
  69                         op2_int <= op2_next;
  70                         sign_int <= sign_next;
  71                 end if;
  72         end process;
  73
  74         -- next state
  75         process(state_int, opcode, done_intern, error_intern, do_calc, div_go_calc_int)
  76         begin
  77                 -- set a default value for next state
  78                 state_next <= state_int;
  79                 -- next state berechnen
  80                 case state_int is
  81                         when SIDLE =>
  82                                 if do_calc = '1' then
  83                                         case opcode is
  84                                                 when ALU_ADD => state_next <= SADD;
  85                                                 when ALU_SUB => state_next <= SSUB;
  86                                                 when ALU_MUL => state_next <= SMUL;
  87                                                 when ALU_DIV => state_next <= SDIV;
  88                                                 when others => state_next <= SIDLE;
  89                                         end case;
  90                                 end if;
  91                         when SADD | SSUB | SMUL | SDIV | SDIV_CALC =>
  92                                 case state_int is
  93                                         when SDIV =>
  94                                                 if div_go_calc_int = '1' then
  95                                                         state_next <= SDIV_CALC;
  96                                                 end if;
  97                                         when others => null;
  98                                 end case;
  99                                 if done_intern = '1' then
 100                                         state_next <= SDONE;
 101                                 end if;
 102                                 if error_intern = '1' then
 103                                         state_next <= SERROR;
 104                                 end if;
 105                         when SDONE | SERROR =>
 106                                 if do_calc = '0' then
 107                                         state_next <= SIDLE;
 108                                 end if;
 109                 end case;
 110         end process;
 111
 112         -- output
 113         process(state_int, op1, op2, dividend_msb_int, laengediv_int, quo_int,
 114                 aktdiv_int, sign_int, op1_int, op2_int, op3_int, opM_int)
 115                 variable multmp, multmp2 : signed(((2*CBITS)-1) downto 0);
 116                 variable mulsign : std_logic;
 117                 variable tmp : csigned;
 118                 -- vars fuer div
 119                 variable laengediv_var, dividend_msb_var, divtmp : divinteger;
 120                 variable aktdiv_int_var, quo_var, op1_var, op2_var : csigned;
 121         begin
 122                 calc_done_next <= '0';
 123                 calc_error_next <= '0';
 124                 div_go_calc_int <= '0';
 125                 done_intern <= '0';
 126                 error_intern <= '0';
 127                 -- default fuer div
 128                 dividend_msb_next <= (others => '0');
 129                 laengediv_next <= (others => '0');
 130                 quo_next <= (others => '0');
 131                 aktdiv_int_next <= aktdiv_int;
 132                 op1_next <= (others => '0');
 133                 op2_next <= (others => '0');
 134                 sign_next <= '0';
 135                 op3_next <= op3_int;
 136                 opM_next <= opM_int;
 137
 138                 case state_int is
 139                         when SIDLE =>
 140                                 opM_next <= (others => '0');
 141                                 aktdiv_int_next <= (others => '0');
 142                         when SADD =>
 143                                 tmp := op1 + op2;
 144                                 op3_next <= tmp;
 145
 146                                 -- over- bzw. underflow?
 147                                 if (op1(CBITS-1) = op2(CBITS-1)) and (op1(CBITS-1) /= tmp(CBITS -1)) then
 148                                         error_intern <= '1';
 149                                 else
 150                                         done_intern <= '1';
 151                                 end if;
 152                         when SSUB =>
 153                                 tmp := op1 - op2;
 154                                 op3_next <= tmp;
 155
 156                                 -- over- bzw. underflow?
 157                                 if (op1(CBITS-1) /= op2(CBITS-1)) and (op1(CBITS-1) /= tmp(CBITS -1)) then
 158                                         error_intern <= '1';
 159                                 else
 160                                         done_intern <= '1';
 161                                 end if;
 162                         when SMUL =>
 163                                 mulsign := op1(CBITS-1) xor op2(CBITS-1);
 164                                 multmp := op1 * op2;
 165                                 op3_next((CBITS-2) downto 0) <= multmp((CBITS-2) downto 0);
 166                                 op3_next(CBITS-1) <= mulsign;
 167
 168                                 if mulsign = '1' then
 169                                         multmp2 := (not multmp) + 1;
 170                                 else
 171                                         multmp2 := multmp;
 172                                 end if;
 173                                 -- overflow?
 174                                 if(multmp2((2*CBITS)-2 downto (CBITS-1)) > 0) then
 175                                         error_intern <= '1';
 176                                 else
 177                                         done_intern <= '1';
 178                                 end if;
 179
 180                         when SDIV =>
 181                                 -- division implementiert nach ~hwmod/doc/division.pdf
 182                                 if ((op1 = x"80000000" and op2 = to_signed(-1, CBITS)) or op2 = to_signed(0, CBITS)) then
 183                                         error_intern <= '1';
 184                                 else
 185                                         -- sign check
 186                                         op1_var := op1;
 187                                         op2_var := op2;
 188                                         if op1(CBITS-1) = '1' then
 189                                                 op1_var := (not op1_var) + 1;
 190                                         end if;
 191                                         if op2(CBITS-1) = '1' then
 192                                                 op2_var := (not op2_var) + 1;
 193                                         end if;
 194
 195                                         dividend_msb_var := divinteger(find_msb(std_logic_vector(op1_var)))-1;
 196                                         laengediv_var := divinteger(find_msb(std_logic_vector(op2_var)))-1;
 197
 198                                         aktdiv_int_next <= op1_var srl to_integer(dividend_msb_var - laengediv_var + 1);
 199
 200                                         -- anmerkung: xst (xilinx) kann folgende zeile nicht uebersetzen
 201                                         -- > if op1 = to_signed(-2147483648, CBITS) then
 202                                         -- darum folgende schreibweise ->
 203                                         if op1 = x"80000000" then
 204                                                 -- so ziemlich das boeseste was passieren kann
 205                                                 done_intern <= '1';
 206                                                 op3_next <= to_signed(-214748364,CBITS);
 207                                                 opM_next <= to_signed(8,CBITS);
 208                                         elsif (op1_var < op2_var) then
 209                                                 done_intern <= '1';
 210                                                 op3_next <= to_signed(0,CBITS);
 211                                                 opM_next <= op1_var;
 212                                         else
 213                                                 div_go_calc_int <= '1';
 214                                                 dividend_msb_next <= dividend_msb_var;
 215                                                 laengediv_next <= laengediv_var;
 216                                                 quo_next <= (others => '0');
 217                                                 op1_next <= op1_var;
 218                                                 op2_next <= op2_var;
 219                                                 sign_next <= op1(CBITS-1) xor op2(CBITS-1);
 220                                         end if;
 221                                 end if;
 222                         when SDIV_CALC =>
 223                                 divtmp := dividend_msb_int - laengediv_int + 1;
 224
 225                                 if divtmp > 0 then
 226                                         aktdiv_int_var := aktdiv_int sll 1;
 227                                         aktdiv_int_var(0) := op1_int(to_integer(divtmp) - 1);
 228
 229                                         quo_var := quo_int sll 1;
 230                                         if aktdiv_int_var >= op2_int then
 231                                                 quo_var(0) := '1';
 232                                                 aktdiv_int_var := aktdiv_int_var - op2_int;
 233                                         end if;
 234
 235                                         quo_next <= quo_var;
 236                                         aktdiv_int_next <= aktdiv_int_var;
 237                                         dividend_msb_next <= dividend_msb_int;
 238                                         laengediv_next <= laengediv_int + 1;
 239                                         op1_next <= op1_int;
 240                                         op2_next <= op2_int;
 241                                         sign_next <= sign_int;
 242                                 else
 243                                         if sign_int = '1' then
 244                                                 op3_next <= (not quo_int) + 1;
 245                                         else
 246                                                 op3_next <= quo_int;
 247                                         end if;
 248                                         opM_next <= aktdiv_int;
 249                                         done_intern <= '1';
 250                                 end if;
 251                         when SDONE | SERROR =>
 252                                 calc_done_next <= '1';
 253                                 if (state_int = SERROR) then
 254                                         calc_error_next <= '1';
 255                                 end if;
 256                 end case;
 257         end process;
 258 end architecture beh;
 259