source src/mainboard/Kconfig
source src/arch/i386/Kconfig
-source src/arch/ppc/Kconfig
menu "Chipset"
+++ /dev/null
-ldscript init/ldscript.lb
-
-makerule coreboot.rom
- depends "coreboot"
- action "cp $< $@"
-end
-
-initobject /src/lib/cbfs.o
-initobject /src/lib/lzma.o
-
-dir init
-dir lib
-dir boot
+++ /dev/null
-# This option is used to set the architecture of a mainboard to PowerPC.
-# It is usually set in mainboard/*/Kconfig.
-config ARCH_POWERPC
- bool
-
-# This is the name of the respective architecture subdirectory in arch/.
-config ARCH
- string
- default ppc
- depends on ARCH_POWERPC
-
+++ /dev/null
-object boot.o
-object tables.o
-object coreboot_table.o
+++ /dev/null
-#include <ip_checksum.h>
-#include <boot/elf.h>
-#include <boot/elf_boot.h>
-#include <string.h>
-#include <console/console.h>
-
-extern void flush_dcache(void);
-
-int elf_check_arch(Elf_ehdr *ehdr)
-{
- return (
- (ehdr->e_machine == EM_PPC) &&
- (ehdr->e_ident[EI_CLASS] == ELFCLASS32) &&
- (ehdr->e_ident[EI_DATA] == ELFDATA2MSB)
- );
-
-}
-
-void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long bounce_size)
-{
- void (*kernel_entry)(void);
-
- kernel_entry = entry;
-
- /*
- * Kernel will invalidate and disable dcache immediately on
- * entry. This is bad if we've been using it, which we
- * have. Make sure it is flushed to memory.
- */
- flush_dcache();
-
- /* On ppc we don't currently support loading over coreboot.
- * So ignore the buffer.
- */
-
- /* Jump to kernel */
- kernel_entry();
-}
+++ /dev/null
-#include <console/console.h>
-#include <ip_checksum.h>
-#include <boot/coreboot_tables.h>
-#include "coreboot_table.h"
-#include <string.h>
-#include <version.h>
-#include <device/device.h>
-#include <stdlib.h>
-
-struct lb_header *lb_table_init(unsigned long addr)
-{
- struct lb_header *header;
-
- /* 16 byte align the address */
- addr += 15;
- addr &= ~15;
-
- header = (void *)addr;
- header->signature[0] = 'L';
- header->signature[1] = 'B';
- header->signature[2] = 'I';
- header->signature[3] = 'O';
- header->header_bytes = sizeof(*header);
- header->header_checksum = 0;
- header->table_bytes = 0;
- header->table_checksum = 0;
- header->table_entries = 0;
- return header;
-}
-
-struct lb_record *lb_first_record(struct lb_header *header)
-{
- struct lb_record *rec;
- rec = (void *)(((char *)header) + sizeof(*header));
- return rec;
-}
-
-struct lb_record *lb_last_record(struct lb_header *header)
-{
- struct lb_record *rec;
- rec = (void *)(((char *)header) + sizeof(*header) + header->table_bytes);
- return rec;
-}
-
-struct lb_record *lb_next_record(struct lb_record *rec)
-{
- rec = (void *)(((char *)rec) + rec->size);
- return rec;
-}
-
-struct lb_record *lb_new_record(struct lb_header *header)
-{
- struct lb_record *rec;
- rec = lb_last_record(header);
- if (header->table_entries) {
- header->table_bytes += rec->size;
- }
- rec = lb_last_record(header);
- header->table_entries++;
- rec->tag = LB_TAG_UNUSED;
- rec->size = sizeof(*rec);
- return rec;
-}
-
-
-struct lb_memory *lb_memory(struct lb_header *header)
-{
- struct lb_record *rec;
- struct lb_memory *mem;
- rec = lb_new_record(header);
- mem = (struct lb_memory *)rec;
- mem->tag = LB_TAG_MEMORY;
- mem->size = sizeof(*mem);
- return mem;
-}
-
-struct lb_mainboard *lb_mainboard(struct lb_header *header)
-{
- struct lb_record *rec;
- struct lb_mainboard *mainboard;
- rec = lb_new_record(header);
- mainboard = (struct lb_mainboard *)rec;
- mainboard->tag = LB_TAG_MAINBOARD;
-
- mainboard->size = (sizeof(*mainboard) +
- strlen(mainboard_vendor) + 1 +
- strlen(mainboard_part_number) + 1 +
- 3) & ~3;
-
- mainboard->vendor_idx = 0;
- mainboard->part_number_idx = strlen(mainboard_vendor) + 1;
-
- memcpy(mainboard->strings + mainboard->vendor_idx,
- mainboard_vendor, strlen(mainboard_vendor) + 1);
- memcpy(mainboard->strings + mainboard->part_number_idx,
- mainboard_part_number, strlen(mainboard_part_number) + 1);
-
- return mainboard;
-}
-
-void lb_strings(struct lb_header *header)
-{
- static const struct {
- uint32_t tag;
- const uint8_t *string;
- } strings[] = {
- { LB_TAG_VERSION, coreboot_version, },
- { LB_TAG_EXTRA_VERSION, coreboot_extra_version, },
- { LB_TAG_BUILD, coreboot_build, },
- { LB_TAG_COMPILE_TIME, coreboot_compile_time, },
- { LB_TAG_COMPILE_BY, coreboot_compile_by, },
- { LB_TAG_COMPILE_HOST, coreboot_compile_host, },
- { LB_TAG_COMPILE_DOMAIN, coreboot_compile_domain, },
- { LB_TAG_COMPILER, coreboot_compiler, },
- { LB_TAG_LINKER, coreboot_linker, },
- { LB_TAG_ASSEMBLER, coreboot_assembler, },
- };
- unsigned int i;
- for(i = 0; i < ARRAY_SIZE(strings); i++) {
- struct lb_string *rec;
- size_t len;
- rec = (struct lb_string *)lb_new_record(header);
- len = strlen(strings[i].string);
- rec->tag = strings[i].tag;
- rec->size = (sizeof(*rec) + len + 1 + 3) & ~3;
- memcpy(rec->string, strings[i].string, len+1);
- }
-
-}
-
-void lb_memory_range(struct lb_memory *mem,
- uint32_t type, uint64_t start, uint64_t size)
-{
- int entries;
- entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]);
- mem->map[entries].start = pack_lb64(start);
- mem->map[entries].size = pack_lb64(size);
- mem->map[entries].type = type;
- mem->size += sizeof(mem->map[0]);
-}
-
-static void lb_reserve_table_memory(struct lb_header *head)
-{
- struct lb_record *last_rec;
- struct lb_memory *mem;
- uint64_t start;
- uint64_t end;
- int i, entries;
-
- last_rec = lb_last_record(head);
- mem = get_lb_mem();
- start = (unsigned long)head;
- end = (unsigned long)last_rec;
- entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]);
- /* Resize the right two memory areas so this table is in
- * a reserved area of memory. Everything has been carefully
- * setup so that is all we need to do.
- */
- for(i = 0; i < entries; i++ ) {
- uint64_t map_start = unpack_lb64(mem->map[i].start);
- uint64_t map_end = map_start + unpack_lb64(mem->map[i].size);
- /* Does this area need to be expanded? */
- if (map_end == start) {
- mem->map[i].size = pack_lb64(end - map_start);
- }
- /* Does this area need to be contracted? */
- else if (map_start == start) {
- mem->map[i].start = pack_lb64(end);
- mem->map[i].size = pack_lb64(map_end - end);
- }
- }
-}
-
-unsigned long lb_table_fini(struct lb_header *head)
-{
- struct lb_record *rec, *first_rec;
- rec = lb_last_record(head);
- if (head->table_entries) {
- head->table_bytes += rec->size;
- }
- lb_reserve_table_memory(head);
- first_rec = lb_first_record(head);
- head->table_checksum = compute_ip_checksum(first_rec, head->table_bytes);
- head->header_checksum = 0;
- head->header_checksum = compute_ip_checksum(head, sizeof(*head));
- printk_debug("Wrote coreboot table at: %p - %p checksum %lx\n",
- head, rec, head->table_checksum);
- return (unsigned long)rec;
-}
-
-static void lb_cleanup_memory_ranges(struct lb_memory *mem)
-{
- int entries;
- int i, j;
- entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]);
-
- /* Sort the lb memory ranges */
- for(i = 0; i < entries; i++) {
- uint64_t entry_start = unpack_lb64(mem->map[i].start);
- for(j = i; j < entries; j++) {
- uint64_t temp_start = unpack_lb64(mem->map[j].start);
- if (temp_start < entry_start) {
- struct lb_memory_range tmp;
- tmp = mem->map[i];
- mem->map[i] = mem->map[j];
- mem->map[j] = tmp;
- }
- }
- }
-
- /* Merge adjacent entries */
- for(i = 0; (i + 1) < entries; i++) {
- uint64_t start, end, nstart, nend;
- if (mem->map[i].type != mem->map[i + 1].type) {
- continue;
- }
- start = unpack_lb64(mem->map[i].start);
- end = start + unpack_lb64(mem->map[i].size);
- nstart = unpack_lb64(mem->map[i + 1].start);
- nend = nstart + unpack_lb64(mem->map[i + 1].size);
- if ((start <= nstart) && (end > nstart)) {
- if (start > nstart) {
- start = nstart;
- }
- if (end < nend) {
- end = nend;
- }
- /* Record the new region size */
- mem->map[i].start = pack_lb64(start);
- mem->map[i].size = pack_lb64(end - start);
-
- /* Delete the entry I have merged with */
- memmove(&mem->map[i + 1], &mem->map[i + 2],
- ((entries - i - 2) * sizeof(mem->map[0])));
- mem->size -= sizeof(mem->map[0]);
- entries -= 1;
- /* See if I can merge with the next entry as well */
- i -= 1;
- }
- }
-}
-
-static void lb_remove_memory_range(struct lb_memory *mem,
- uint64_t start, uint64_t size)
-{
- uint64_t end;
- int entries;
- int i;
-
- end = start + size;
- entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]);
-
- /* Remove a reserved area from the memory map */
- for(i = 0; i < entries; i++) {
- uint64_t map_start = unpack_lb64(mem->map[i].start);
- uint64_t map_end = map_start + unpack_lb64(mem->map[i].size);
- if ((start <= map_start) && (end >= map_end)) {
- /* Remove the completely covered range */
- memmove(&mem->map[i], &mem->map[i + 1],
- ((entries - i - 1) * sizeof(mem->map[0])));
- mem->size -= sizeof(mem->map[0]);
- entries -= 1;
- /* Since the index will disappear revisit what will appear here */
- i -= 1;
- }
- else if ((start > map_start) && (end < map_end)) {
- /* Split the memory range */
- memmove(&mem->map[i + 1], &mem->map[i],
- ((entries - i) * sizeof(mem->map[0])));
- mem->size += sizeof(mem->map[0]);
- entries += 1;
- /* Update the first map entry */
- mem->map[i].size = pack_lb64(start - map_start);
- /* Update the second map entry */
- mem->map[i + 1].start = pack_lb64(end);
- mem->map[i + 1].size = pack_lb64(map_end - end);
- /* Don't bother with this map entry again */
- i += 1;
- }
- else if ((start <= map_start) && (end > map_start)) {
- /* Shrink the start of the memory range */
- mem->map[i].start = pack_lb64(end);
- mem->map[i].size = pack_lb64(map_end - end);
- }
- else if ((start < map_end) && (start > map_start)) {
- /* Shrink the end of the memory range */
- mem->map[i].size = pack_lb64(start - map_start);
- }
- }
-}
-
-static void lb_add_memory_range(struct lb_memory *mem,
- uint32_t type, uint64_t start, uint64_t size)
-{
- lb_remove_memory_range(mem, start, size);
- lb_memory_range(mem, type, start, size);
- lb_cleanup_memory_ranges(mem);
-}
-
-/* Routines to extract part so the coreboot table or
- * information from the coreboot table after we have written it.
- * Currently get_lb_mem relies on a global we can change the
- * implementaiton.
- */
-static struct lb_memory *mem_ranges = 0;
-struct lb_memory *get_lb_mem(void)
-{
- return mem_ranges;
-}
-
-static void build_lb_mem_range(void *gp, struct device *dev, struct resource *res)
-{
- struct lb_memory *mem = gp;
- lb_memory_range(mem, LB_MEM_RAM, res->base, res->size);
-}
-
-static struct lb_memory *build_lb_mem(struct lb_header *head)
-{
- struct lb_memory *mem;
-
- /* Record where the lb memory ranges will live */
- mem = lb_memory(head);
- mem_ranges = mem;
-
- /* Build the raw table of memory */
- search_global_resources(
- IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
- build_lb_mem_range, mem);
- lb_cleanup_memory_ranges(mem);
- return mem;
-}
-
-unsigned long write_coreboot_table(
- unsigned long low_table_start, unsigned long low_table_end,
- unsigned long rom_table_start, unsigned long rom_table_end)
-{
- unsigned long table_size;
- struct lb_header *head;
- struct lb_memory *mem;
-
- head = lb_table_init(low_table_end);
- low_table_end = (unsigned long)head;
- if (CONFIG_HAVE_OPTION_TABLE == 1) {
- struct lb_record *rec_dest, *rec_src;
- /* Write the option config table... */
- rec_dest = lb_new_record(head);
- rec_src = (struct lb_record *)(void *)&option_table;
- memcpy(rec_dest, rec_src, rec_src->size);
- }
- /* Record where RAM is located */
- mem = build_lb_mem(head);
-
- /* Find the current mptable size */
- table_size = (low_table_end - low_table_start);
-
- /* Record the mptable and the the lb_table (This will be adjusted later) */
- lb_add_memory_range(mem, LB_MEM_TABLE,
- low_table_start, table_size);
-
- /* Record the pirq table */
- lb_add_memory_range(mem, LB_MEM_TABLE,
- rom_table_start, (rom_table_end - rom_table_start));
-
- /* Note:
- * I assume that there is always memory at immediately after
- * the low_table_end. This means that after I setup the coreboot table.
- * I can trivially fixup the reserved memory ranges to hold the correct
- * size of the coreboot table.
- */
-
- /* Record our motheboard */
- lb_mainboard(head);
- /* Record our various random string information */
- lb_strings(head);
-
- low_table_end = lb_table_fini(head);
-
- /* Remember where my valid memory ranges are */
- return low_table_end;
-}
+++ /dev/null
-#ifndef COREBOOT_TABLE_H
-#define COREBOOT_TABLE_H
-
-#include <boot/coreboot_tables.h>
-
-struct mem_range;
-
-/* This file holds function prototypes for building the coreboot table. */
-unsigned long write_coreboot_table(
- unsigned long low_table_start, unsigned long low_table_end,
- unsigned long rom_table_start, unsigned long rom_table_end);
-
-struct lb_header *lb_table_init(unsigned long addr);
-struct lb_record *lb_first_record(struct lb_header *header);
-struct lb_record *lb_last_record(struct lb_header *header);
-struct lb_record *lb_next_record(struct lb_record *rec);
-struct lb_record *lb_new_record(struct lb_header *header);
-struct lb_memory *lb_memory(struct lb_header *header);
-void lb_memory_range(struct lb_memory *mem,
- uint32_t type, uint64_t startk, uint64_t sizek);
-struct lb_mainboard *lb_mainboard(struct lb_header *header);
-unsigned long lb_table_fini(struct lb_header *header);
-
-/* Routines to extract part so the coreboot table or information
- * from the coreboot table.
- */
-struct lb_memory *get_lb_mem(void);
-
-extern struct cmos_option_table option_table;
-
-#endif /* COREBOOT_TABLE_H */
+++ /dev/null
-#include <console/console.h>
-#include <cpu/cpu.h>
-#include <boot/tables.h>
-#include <boot/coreboot_tables.h>
-#include "coreboot_table.h"
-
-struct lb_memory *
-write_tables(void)
-{
- unsigned long low_table_start, low_table_end;
- unsigned long rom_table_start, rom_table_end;
-
- rom_table_start = 0xf0000;
- rom_table_end = 0xf0000;
- /* Start low addr at 16 bytes instead of 0 because of a buglet
- * in the generic linux unzip code, as it tests for the a20 line.
- */
- low_table_start = 0;
- low_table_end = 16;
-
- /* The coreboot table must be in 0-4K or 960K-1M */
- write_coreboot_table(
- low_table_start, low_table_end,
- rom_table_start, rom_table_end);
-
- return get_lb_mem();
-}
+++ /dev/null
-#ifndef ASM_I386_BOOT_H
-#define ASM_I386_BOOT_H
-
-#define ELF_CLASS ELFCLASS32
-#define ELF_DATA ELFDATA2MSB
-#define ELF_ARCH EM_PPC
-
-#endif /* ASM_I386_BOOT_H */
+++ /dev/null
-#ifndef _BYTEORDER_H
-#define _BYTEORDER_H
-
-#define __BIG_ENDIAN 4321
-
-#include <swab.h>
-
-#define cpu_to_le32(x) swab32((x))
-#define le32_to_cpu(x) swab32((x))
-#define cpu_to_le16(x) swab16((x))
-#define le16_to_cpu(x) swab16((x))
-#define cpu_to_be32(x) ((unsigned int)(x))
-#define be32_to_cpu(x) ((unsigned int)(x))
-#define cpu_to_be16(x) ((unsigned short)(x))
-#define be16_to_cpu(x) ((unsigned short)(x))
-
-#endif /* _BYTEORDER_H */
+++ /dev/null
-#ifndef ARCH_CPU_H
-#define ARCH_CPU_H
-/*
- * this should probably integrate code from src/arch/ppc/lib/cpuid.c
- */
-
-struct cpu_device_id {
- unsigned pvr;
-};
-
-struct cpu_driver {
- struct device_operations *ops;
- struct cpu_device_id *id_table;
-};
-
-#ifndef CONFIG_STACK_SIZE
-#error CONFIG_STACK_SIZE not defined
-#endif
-
-/* The basic logic comes from the Linux kernel.
- * The invariant is that (1 << 31 - STACK_BITS) == CONFIG_STACK_SIZE
- * I wish there was simpler way to support multiple stack sizes.
- * Oh well.
- */
-#if CONFIG_STACK_SIZE == 4096
-#define STACK_BITS "19"
-#elif CONFIG_STACK_SIZE == 8192
-#define STACK_BITS "18"
-#elif CONFIG_STACK_SIZE == 16384
-#define STACK_BITS "17"
-#elif CONFIG_STACK_SIZE == 32768
-#define STACK_BITS "16"
-#elif CONFIG_STACK_SIZE == 65536
-#define STACK_BITS "15"
-#else
-#error Unimplemented stack size
-#endif
-
-
-struct cpu_info {
- struct device *cpu;
- unsigned long index;
-};
-
-
-static inline struct cpu_info *cpu_info(void)
-{
- struct cpu_info *ci;
- __asm__("rlwinm %0,1,0,0," STACK_BITS : "=r"(ci));
- return ci;
-}
-
-static inline unsigned long cpu_index(void)
-{
- struct cpu_info *ci;
- ci = cpu_info();
- return ci->index;
-}
-
-#endif /* ARCH_CPU_H */
+++ /dev/null
-/*
- * BK Id: SCCS/s.io.h 1.14 10/16/01 15:58:42 trini
- */
-#ifndef _PPC_IO_H
-#define _PPC_IO_H
-
-#include <stdint.h>
-
-#define SIO_CONFIG_RA 0x398
-#define SIO_CONFIG_RD 0x399
-
-#define SLOW_DOWN_IO
-
-#ifndef CONFIG_IO_BASE
-#define CONFIG_IO_BASE 0
-#endif
-
-#define readb(addr) in_8((volatile uint8_t *)(addr))
-#define writeb(b,addr) out_8((volatile uint8_t *)(addr), (b))
-#define readw(addr) in_le16((volatile uint16_t *)(addr))
-#define readl(addr) in_le32((volatile uint32_t *)(addr))
-#define writew(b,addr) out_le16((volatile uint16_t *)(addr),(b))
-#define writel(b,addr) out_le32((volatile uint32_t *)(addr),(b))
-
-
-#define __raw_readb(addr) (*(volatile unsigned char *)(addr))
-#define __raw_readw(addr) (*(volatile unsigned short *)(addr))
-#define __raw_readl(addr) (*(volatile unsigned int *)(addr))
-#define __raw_writeb(v, addr) (*(volatile unsigned char *)(addr) = (v))
-#define __raw_writew(v, addr) (*(volatile unsigned short *)(addr) = (v))
-#define __raw_writel(v, addr) (*(volatile unsigned int *)(addr) = (v))
-
-/*
- * The insw/outsw/insl/outsl macros don't do byte-swapping.
- * They are only used in practice for transferring buffers which
- * are arrays of bytes, and byte-swapping is not appropriate in
- * that case. - paulus
- */
-#define insw(port, buf, ns) _insw_ns((uint16_t *)((port)+CONFIG_IO_BASE), (buf), (ns))
-#define outsw(port, buf, ns) _outsw_ns((uint16_t *)((port)+CONFIG_IO_BASE), (buf), (ns))
-
-#define inb(port) in_8((uint8_t *)((port)+CONFIG_IO_BASE))
-#define outb(val, port) out_8((uint8_t *)((port)+CONFIG_IO_BASE), (val))
-#define inw(port) in_le16((uint16_t *)((port)+CONFIG_IO_BASE))
-#define outw(val, port) out_le16((uint16_t *)((port)+CONFIG_IO_BASE), (val))
-#define inl(port) in_le32((uint32_t *)((port)+CONFIG_IO_BASE))
-#define outl(val, port) out_le32((uint32_t *)((port)+CONFIG_IO_BASE), (val))
-
-#define inb_p(port) inb((port))
-#define outb_p(val, port) outb((val), (port))
-#define inw_p(port) inw((port))
-#define outw_p(val, port) outw((val), (port))
-#define inl_p(port) inl((port))
-#define outl_p(val, port) outl((val), (port))
-
-/*
- * The *_ns versions below do byte-swapping.
- */
-#define insw_ns(port, buf, ns) _insw((uint16_t *)((port)+CONFIG_IO_BASE), (buf), (ns))
-#define outsw_ns(port, buf, ns) _outsw((uint16_t *)((port)+CONFIG_IO_BASE), (buf), (ns))
-
-
-#define IO_SPACE_LIMIT ~0
-
-#define memset_io(a,b,c) memset((void *)(a),(b),(c))
-#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
-#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
-
-/*
- * Enforce In-order Execution of I/O:
- * Acts as a barrier to ensure all previous I/O accesses have
- * completed before any further ones are issued.
- */
-static inline void eieio(void)
-{
- __asm__ __volatile__ ("eieio" : : : "memory");
-}
-
-/* Enforce in-order execution of data I/O.
- * No distinction between read/write on PPC; use eieio for all three.
- */
-#define iobarrier_rw() eieio()
-#define iobarrier_r() eieio()
-#define iobarrier_w() eieio()
-
-/*
- * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
- */
-static inline int in_8(volatile unsigned char *addr)
-{
- int ret;
-
- __asm__ __volatile__("lbz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
- return ret;
-}
-
-static inline void out_8(volatile unsigned char *addr, int val)
-{
- __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
-}
-
-static inline int in_le16(volatile unsigned short *addr)
-{
- int ret;
-
- __asm__ __volatile__("lhbrx %0,0,%1; eieio" : "=r" (ret) :
- "r" (addr), "m" (*addr));
- return ret;
-}
-
-static inline int in_be16(volatile unsigned short *addr)
-{
- int ret;
-
- __asm__ __volatile__("lhz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
- return ret;
-}
-
-static inline void out_le16(volatile unsigned short *addr, int val)
-{
- __asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) :
- "r" (val), "r" (addr));
-}
-
-static inline void out_be16(volatile unsigned short *addr, int val)
-{
- __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
-}
-
-static inline unsigned in_le32(volatile unsigned *addr)
-{
- unsigned ret;
-
- __asm__ __volatile__("lwbrx %0,0,%1; eieio" : "=r" (ret) :
- "r" (addr), "m" (*addr));
- return ret;
-}
-
-static inline unsigned in_be32(volatile unsigned *addr)
-{
- unsigned ret;
-
- __asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
- return ret;
-}
-
-static inline void out_le32(volatile unsigned *addr, int val)
-{
- __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) :
- "r" (val), "r" (addr));
-}
-
-static inline void out_be32(volatile unsigned *addr, int val)
-{
- __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
-}
-
-static inline void _insw_ns(volatile uint16_t *port, void *buf, int ns)
-{
- uint16_t * b = (uint16_t *)buf;
-
- while (ns > 0) {
- *b++ = in_le16(port);
- ns--;
- }
-}
-
-static inline void _outsw_ns(volatile uint16_t *port, const void *buf, int ns)
-{
- uint16_t * b = (uint16_t *)buf;
-
- while (ns > 0) {
- out_le16(port, *b++);
- ns--;
- }
-}
-
-static inline void _insw(volatile uint16_t *port, void *buf, int ns)
-{
- uint16_t * b = (uint16_t *)buf;
-
- while (ns > 0) {
- *b++ = in_be16(port);
- ns--;
- }
-}
-
-static inline void _outsw(volatile uint16_t *port, const void *buf, int ns)
-{
- uint16_t * b = (uint16_t *)buf;
-
- while (ns > 0) {
- out_be16(port, *b++);
- ns--;
- }
-}
-#endif
+++ /dev/null
-#ifndef ARCH_PPC_PCI_OPS_H
-#define ARCH_PPC_PCI_OPS_H
-
-extern const struct pci_bus_operations pci_ppc_conf1;
-
-#endif /* ARCH_PPC_PCI_OPS_H */
+++ /dev/null
-#ifndef _PCICONF_H
-#define _PCICONF_H
-
-/*
- * Direct access to PCI hardware...
- */
-uint8_t pci_ppc_read_config8(unsigned char, int, int);
-uint16_t pci_ppc_read_config16(unsigned char, int, int);
-uint32_t pci_ppc_read_config32(unsigned char, int, int);
-int pci_ppc_write_config8(unsigned char, int, int, uint8_t);
-int pci_ppc_write_config16(unsigned char, int, int, uint16_t);
-int pci_ppc_write_config32(unsigned char, int, int, uint32_t);
-
-#define CONFIG_CMD(bus,devfn,where) \
- ((bus << 16) | (devfn << 8) | (where & ~3) | 0x80000000)
-
-#endif /* _PCICONF_H */
+++ /dev/null
-#ifndef ARCH_PIRQ_ROUTING_H
-#define ARCH_PIRQ_ROUTING_H
-
-#include <types.h>
-
-#define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
-#define PIRQ_VERSION 0x0100
-
-struct irq_info {
- u8 bus, devfn; /* Bus, device and function */
- struct {
- u8 link; /* IRQ line ID, chipset dependent, 0=not routed */
- u16 bitmap; /* Available IRQs */
- } __attribute__((packed)) irq[4];
- u8 slot; /* Slot number, 0=onboard */
- u8 rfu;
-} __attribute__((packed));
-
-#if defined(CONFIG_IRQ_SLOT_COUNT)
-#define IRQ_SLOTS_COUNT CONFIG_IRQ_SLOT_COUNT
-#elif (__GNUC__ < 3)
-#define IRQ_SLOTS_COUNT 1
-#else
-#define IRQ_SLOTS_COUNT
-#endif
-
-struct irq_routing_table {
- u32 signature; /* PIRQ_SIGNATURE should be here */
- u16 version; /* PIRQ_VERSION */
- u16 size; /* Table size in bytes */
- u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */
- u16 exclusive_irqs; /* IRQs devoted exclusively to PCI usage */
- u16 rtr_vendor, rtr_device; /* Vendor and device ID of interrupt router */
- u32 miniport_data; /* Crap */
- u8 rfu[11];
- u8 checksum; /* Modulo 256 checksum must give zero */
- struct irq_info slots[IRQ_SLOTS_COUNT];
-} __attribute__((packed));
-
-extern const struct irq_routing_table intel_irq_routing_table;
-
-#if defined(CONFIG_DEBUG) && defined(CONFIG_GENERATE_PIRQ_TABLE)
-void check_pirq_routing_table(void);
-#else
-#define check_pirq_routing_table() do {} while(0)
-#endif
-
-#if defined(CONFIG_GENERATE_PIRQ_TABLE)
-unsigned long copy_pirq_routing_table(unsigned long start);
-#else
-#define copy_pirq_routing_table(start) (start)
-#endif
-
-#endif /* ARCH_PIRQ_ROUTING_H */
+++ /dev/null
-#ifndef I386_BITOPS_H
-#define I386_BITOPS_H
-
-/**
- * log2 - Find the truncated log base 2 of x
- */
-
-static inline unsigned long log2(unsigned long x)
-{
- unsigned long r = 0;
- /*
- __asm__(
- "bsrl %1, %0\n\t"
- "jnz 1f\n\t"
- "movl $-1, %0\n\t"
- "1:\n\t"
- : "=r" (r) : "r" (x));
- */
- return r;
-
-}
-#endif /* I386_BITOPS_H */
+++ /dev/null
-#ifndef _BOARD_H
-#define _BOARD_H
-
-/*
- * Provided for all PPC boards to do board-level initialization. This
- * happens prior to entry into hardwaremain().
- */
-extern void board_init(void);
-extern void board_init2(void);
-#endif /* _BOARD_H */
+++ /dev/null
-#ifndef _CLOCK_H
-#define _CLOCK_H
-
-/*
- * Various clock routines.
- */
-extern unsigned long get_timer_freq(void);
-extern unsigned long get_pci_bus_freq(void);
-#endif /* _CLOCK_H */
+++ /dev/null
-#define ULONG_MAX 4294967295
-#include <arch-generic/div64.h>
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _PPC_H
-#define _PPC_H
-
-#define BIG_ENDIAN
-#define RODATA __attribute__ ((__section__ (".rodata")))
-
-/* stringify is needed for macro expansion */
-#define stringify(x) #x
-
-#define mfdcr(reg) ({unsigned int result; \
- __asm__ volatile("mfdcr %0, " stringify(reg) \
- : "=r" (result)); result;})
-
-#define mtdcr(reg, v) asm volatile("mtdcr " stringify(reg) ",%0" \
- : : "r" (v))
-
-extern unsigned ppc_getmsr(void);
-extern unsigned ppc_gethid0(void);
-extern unsigned ppc_gethid1(void);
-extern unsigned ppc_getpvr(void);
-extern void ppc_setmsr(unsigned);
-extern void ppc_sethid0(unsigned);
-extern void ppc_set1015(unsigned);
-
-extern void ppc_init_float_registers(const double *);
-
-/* Do CPU specific setup, with optional icache */
-extern void ppc_setup_cpu(int icache);
-
-extern void ppc_enable_dcache(void);
-extern void ppc_disable_dcache(void);
-extern void ppc_enable_mmu(void);
-
-/* Describe which sort of ppc CPU I am */
-extern void ppc_identify(void);
-#endif
+++ /dev/null
-/*----------------------------------------------------------------------------+
-|
-| This source code has been made available to you by IBM on an AS-IS
-| basis. Anyone receiving this source is licensed under IBM
-| copyrights to use it in any way he or she deems fit, including
-| copying it, modifying it, compiling it, and redistributing it either
-| with or without modifications. No license under IBM patents or
-| patent applications is to be implied by the copyright license.
-|
-| Any user of this software should understand that IBM cannot provide
-| technical support for this software and will not be responsible for
-| any consequences resulting from the use of this software.
-|
-| Any person who transfers this source code or any derivative work
-| must include the IBM copyright notice, this paragraph, and the
-| preceding two paragraphs in the transferred software.
-|
-| COPYRIGHT I B M CORPORATION 1999
-| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
-+----------------------------------------------------------------------------*/
-
-#ifndef __PPC4XX_H__
-#define __PPC4XX_H__
-
-/*--------------------------------------------------------------------- */
-/* Special Purpose Registers */
-/*--------------------------------------------------------------------- */
- #define srr2 0x3de /* save/restore register 2 */
- #define srr3 0x3df /* save/restore register 3 */
- #define dbsr 0x3f0 /* debug status register */
- #define dbcr0 0x3f2 /* debug control register 0 */
- #define dbcr1 0x3bd /* debug control register 1 */
- #define iac1 0x3f4 /* instruction address comparator 1 */
- #define iac2 0x3f5 /* instruction address comparator 2 */
- #define iac3 0x3b4 /* instruction address comparator 3 */
- #define iac4 0x3b5 /* instruction address comparator 4 */
- #define dac1 0x3f6 /* data address comparator 1 */
- #define dac2 0x3f7 /* data address comparator 2 */
- #define dccr 0x3fa /* data cache control register */
- #define iccr 0x3fb /* instruction cache control register */
- #define esr 0x3d4 /* execption syndrome register */
- #define dear 0x3d5 /* data exeption address register */
- #define evpr 0x3d6 /* exeption vector prefix register */
- #define tsr 0x3d8 /* timer status register */
- #define tcr 0x3da /* timer control register */
- #define pit 0x3db /* programmable interval timer */
- #define sgr 0x3b9 /* storage guarded reg */
- #define dcwr 0x3ba /* data cache write-thru reg*/
- #define sler 0x3bb /* storage little-endian reg */
- #define cdbcr 0x3d7 /* cache debug cntrl reg */
- #define icdbdr 0x3d3 /* instr cache dbug data reg*/
- #define ccr0 0x3b3 /* core configuration register */
- #define dvc1 0x3b6 /* data value compare register 1 */
- #define dvc2 0x3b7 /* data value compare register 2 */
- #define pid 0x3b1 /* process ID */
- #define su0r 0x3bc /* storage user-defined register 0 */
- #define zpr 0x3b0 /* zone protection regsiter */
-
- #define tbl 0x11c /* time base lower - privileged write */
- #define tbu 0x11d /* time base upper - privileged write */
-
- #define sprg4r 0x104 /* Special purpose general 4 - read only */
- #define sprg5r 0x105 /* Special purpose general 5 - read only */
- #define sprg6r 0x106 /* Special purpose general 6 - read only */
- #define sprg7r 0x107 /* Special purpose general 7 - read only */
- #define sprg4w 0x114 /* Special purpose general 4 - write only */
- #define sprg5w 0x115 /* Special purpose general 5 - write only */
- #define sprg6w 0x116 /* Special purpose general 6 - write only */
- #define sprg7w 0x117 /* Special purpose general 7 - write only */
-
-/*----------------------------------------------------------------------------+
-| Machine State Register. MSR_EE, MSR_PR, MSR_FP, MSR_ME, MSR_FE0, MSR_FE1,
-+----------------------------------------------------------------------------*/
-#define MSR_APE 0x00080000 /* wait state enable */
-#define MSR_WE 0x00040000 /* wait state enable */
-#define MSR_CE 0x00020000 /* critical interrupt enable */
-#define MSR_DWE 0x00000400 /* debug wait enable */
-#define MSR_DE 0x00000200 /* debug interrupt enable */
-#define MSR_IR 0x00000020 /* instruction relocale */
-#define MSR_DR 0x00000010 /* data relocale */
-
-/******************************************************************************
- * Special for PPC405GP
- ******************************************************************************/
-
-/******************************************************************************
- * DMA
- ******************************************************************************/
-#define DMA_DCR_BASE 0x100
-#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */
-#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */
-#define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */
-#define dmasa0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */
-#define dmasb0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */
-#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */
-#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */
-#define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */
-#define dmasa1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */
-#define dmasb1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */
-#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */
-#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */
-#define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */
-#define dmasa2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */
-#define dmasb2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */
-#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */
-#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */
-#define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */
-#define dmasa3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */
-#define dmasb3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */
-#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */
-#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */
-#define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */
-
-/******************************************************************************
- * Universal interrupt controller
- ******************************************************************************/
-#define UIC_DCR_BASE 0xc0
-#define uicsr (UIC_DCR_BASE+0x0) /* UIC status */
-#define uicsrs (UIC_DCR_BASE+0x1) /* UIC status set */
-#define uicer (UIC_DCR_BASE+0x2) /* UIC enable */
-#define uiccr (UIC_DCR_BASE+0x3) /* UIC critical */
-#define uicpr (UIC_DCR_BASE+0x4) /* UIC polarity */
-#define uictr (UIC_DCR_BASE+0x5) /* UIC triggering */
-#define uicmsr (UIC_DCR_BASE+0x6) /* UIC masked status */
-#define uicvr (UIC_DCR_BASE+0x7) /* UIC vector */
-#define uicvcr (UIC_DCR_BASE+0x8) /* UIC vector configuration */
-
-/*-----------------------------------------------------------------------------+
-| Universal interrupt controller interrupts
-+-----------------------------------------------------------------------------*/
-#define UIC_UART0 0x80000000 /* UART 0 */
-#define UIC_UART1 0x40000000 /* UART 1 */
-#define UIC_IIC 0x20000000 /* IIC */
-#define UIC_EXT_MAST 0x10000000 /* External Master */
-#define UIC_PCI 0x08000000 /* PCI write to command reg */
-#define UIC_DMA0 0x04000000 /* DMA chan. 0 */
-#define UIC_DMA1 0x02000000 /* DMA chan. 1 */
-#define UIC_DMA2 0x01000000 /* DMA chan. 2 */
-#define UIC_DMA3 0x00800000 /* DMA chan. 3 */
-#define UIC_EMAC_WAKE 0x00400000 /* EMAC wake up */
-#define UIC_MAL_SERR 0x00200000 /* MAL SERR */
-#define UIC_MAL_TXEOB 0x00100000 /* MAL TXEOB */
-#define UIC_MAL_RXEOB 0x00080000 /* MAL RXEOB */
-#define UIC_MAL_TXDE 0x00040000 /* MAL TXDE */
-#define UIC_MAL_RXDE 0x00020000 /* MAL RXDE */
-#define UIC_ENET 0x00010000 /* Ethernet */
-#define UIC_EXT_PCI_SERR 0x00008000 /* External PCI SERR# */
-#define UIC_ECC_CE 0x00004000 /* ECC Correctable Error */
-#define UIC_PCI_PM 0x00002000 /* PCI Power Management */
-#define UIC_EXT0 0x00000040 /* External interrupt 0 */
-#define UIC_EXT1 0x00000020 /* External interrupt 1 */
-#define UIC_EXT2 0x00000010 /* External interrupt 2 */
-#define UIC_EXT3 0x00000008 /* External interrupt 3 */
-#define UIC_EXT4 0x00000004 /* External interrupt 4 */
-#define UIC_EXT5 0x00000002 /* External interrupt 5 */
-#define UIC_EXT6 0x00000001 /* External interrupt 6 */
-
-/******************************************************************************
- * SDRAM Controller
- ******************************************************************************/
-#define SDRAM_DCR_BASE 0x10
-#define memcfga (SDRAM_DCR_BASE+0x0) /* Memory configuration address reg */
-#define memcfgd (SDRAM_DCR_BASE+0x1) /* Memory configuration data reg */
- /* values for memcfga register - indirect addressing of these regs */
-#ifndef CONFIG_405EP
- #define mem_besra 0x00 /* bus error syndrome reg a */
- #define mem_besrsa 0x04 /* bus error syndrome reg set a */
- #define mem_besrb 0x08 /* bus error syndrome reg b */
- #define mem_besrsb 0x0c /* bus error syndrome reg set b */
- #define mem_bear 0x10 /* bus error address reg */
-#endif
- #define mem_mcopt1 0x20 /* memory controller options 1 */
- #define mem_rtr 0x30 /* refresh timer reg */
- #define mem_pmit 0x34 /* power management idle timer */
- #define mem_mb0cf 0x40 /* memory bank 0 configuration */
- #define mem_mb1cf 0x44 /* memory bank 1 configuration */
- #define mem_mb2cf 0x48 /* memory bank 2 configuration */
- #define mem_mb3cf 0x4c /* memory bank 3 configuration */
- #define mem_sdtr1 0x80 /* timing reg 1 */
-#ifndef CONFIG_405EP
- #define mem_ecccf 0x94 /* ECC configuration */
- #define mem_eccerr 0x98 /* ECC error status */
-#endif
-
-/******************************************************************************
- * Decompression Controller
- ******************************************************************************/
-#define DECOMP_DCR_BASE 0x14
-#define kiar (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */
-#define kidr (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */
- /* values for kiar register - indirect addressing of these regs */
- #define kitor0 0x00 /* index table origin register 0 */
- #define kitor1 0x01 /* index table origin register 1 */
- #define kitor2 0x02 /* index table origin register 2 */
- #define kitor3 0x03 /* index table origin register 3 */
- #define kaddr0 0x04 /* address decode definition regsiter 0 */
- #define kaddr1 0x05 /* address decode definition regsiter 1 */
- #define kconf 0x40 /* decompression core config register */
- #define kid 0x41 /* decompression core ID register */
- #define kver 0x42 /* decompression core version # reg */
- #define kpear 0x50 /* bus error addr reg (PLB addr) */
- #define kbear 0x51 /* bus error addr reg (DCP to EBIU addr)*/
- #define kesr0 0x52 /* bus error status reg 0 (R/clear) */
- #define kesr0s 0x53 /* bus error status reg 0 (set) */
- /* There are 0x400 of the following registers, from krom0 to krom3ff*/
- /* Only the first one is given here. */
- #define krom0 0x400 /* SRAM/ROM read/write */
-
-/******************************************************************************
- * Power Management
- ******************************************************************************/
-#define POWERMAN_DCR_BASE 0xb8
-#define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */
-#define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */
-#define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */
-
-/******************************************************************************
- * Extrnal Bus Controller
- ******************************************************************************/
-#define EBC_DCR_BASE 0x12
-#define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */
-#define ebccfgd (EBC_DCR_BASE+0x1) /* External bus controller data reg */
- /* values for ebccfga register - indirect addressing of these regs */
- #define pb0cr 0x00 /* periph bank 0 config reg */
- #define pb1cr 0x01 /* periph bank 1 config reg */
- #define pb2cr 0x02 /* periph bank 2 config reg */
- #define pb3cr 0x03 /* periph bank 3 config reg */
- #define pb4cr 0x04 /* periph bank 4 config reg */
- #define pb5cr 0x05 /* periph bank 5 config reg */
- #define pb6cr 0x06 /* periph bank 6 config reg */
- #define pb7cr 0x07 /* periph bank 7 config reg */
- #define pb0ap 0x10 /* periph bank 0 access parameters */
- #define pb1ap 0x11 /* periph bank 1 access parameters */
- #define pb2ap 0x12 /* periph bank 2 access parameters */
- #define pb3ap 0x13 /* periph bank 3 access parameters */
- #define pb4ap 0x14 /* periph bank 4 access parameters */
- #define pb5ap 0x15 /* periph bank 5 access parameters */
- #define pb6ap 0x16 /* periph bank 6 access parameters */
- #define pb7ap 0x17 /* periph bank 7 access parameters */
- #define pbear 0x20 /* periph bus error addr reg */
- #define pbesr0 0x21 /* periph bus error status reg 0 */
- #define pbesr1 0x22 /* periph bus error status reg 1 */
- #define epcr 0x23 /* external periph control reg */
-
-/******************************************************************************
- * Control
- ******************************************************************************/
-#define CNTRL_DCR_BASE 0x0b0
-#define CPC0_PLLMR (CNTRL_DCR_BASE+0x0) /* PLL mode register */
-#define CPC0_CR0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */
-#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */
-#define CPC0_PSR (CNTRL_DCR_BASE+0x4) /* strap register */
-
-#define ecr (0xaa) /* edge conditioner register (405gpr) */
-
-/* Bit definitions */
-#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */
-#define PLLMR_FWD_DIV_BYPASS 0xE0000000
-#define PLLMR_FWD_DIV_3 0xA0000000
-#define PLLMR_FWD_DIV_4 0x80000000
-#define PLLMR_FWD_DIV_6 0x40000000
-
-#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */
-#define PLLMR_FB_DIV_1 0x02000000
-#define PLLMR_FB_DIV_2 0x04000000
-#define PLLMR_FB_DIV_3 0x06000000
-#define PLLMR_FB_DIV_4 0x08000000
-
-#define PLLMR_TUNING_MASK 0x01F80000
-
-#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */
-#define PLLMR_CPU_PLB_DIV_1 0x00000000
-#define PLLMR_CPU_PLB_DIV_2 0x00020000
-#define PLLMR_CPU_PLB_DIV_3 0x00040000
-#define PLLMR_CPU_PLB_DIV_4 0x00060000
-
-#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */
-#define PLLMR_OPB_PLB_DIV_1 0x00000000
-#define PLLMR_OPB_PLB_DIV_2 0x00008000
-#define PLLMR_OPB_PLB_DIV_3 0x00010000
-#define PLLMR_OPB_PLB_DIV_4 0x00018000
-
-#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */
-#define PLLMR_PCI_PLB_DIV_1 0x00000000
-#define PLLMR_PCI_PLB_DIV_2 0x00002000
-#define PLLMR_PCI_PLB_DIV_3 0x00004000
-#define PLLMR_PCI_PLB_DIV_4 0x00006000
-
-#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */
-#define PLLMR_EXB_PLB_DIV_2 0x00000000
-#define PLLMR_EXB_PLB_DIV_3 0x00000800
-#define PLLMR_EXB_PLB_DIV_4 0x00001000
-#define PLLMR_EXB_PLB_DIV_5 0x00001800
-
-/* definitions for PPC405GPr (new mode strapping) */
-#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */
-
-#define PSR_PLL_FWD_MASK 0xC0000000
-#define PSR_PLL_FDBACK_MASK 0x30000000
-#define PSR_PLL_TUNING_MASK 0x0E000000
-#define PSR_PLB_CPU_MASK 0x01800000
-#define PSR_OPB_PLB_MASK 0x00600000
-#define PSR_PCI_PLB_MASK 0x00180000
-#define PSR_EB_PLB_MASK 0x00060000
-#define PSR_ROM_WIDTH_MASK 0x00018000
-#define PSR_ROM_LOC 0x00004000
-#define PSR_PCI_ASYNC_EN 0x00001000
-#define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */
-#define PSR_PCI_ARBIT_EN 0x00000400
-#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */
-
-/*
- * PLL Voltage Controlled Oscillator (VCO) definitions
- * Maximum and minimum values (in MHz) for correct PLL operation.
- */
-#define VCO_MIN 400
-#define VCO_MAX 800
-
-/******************************************************************************
- * Memory Access Layer
- ******************************************************************************/
-#define MAL_DCR_BASE 0x180
-#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
-#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */
-#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
-#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
-#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */
-#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
-#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
-#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
-#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */
-#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
-#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
-#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
-#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */
-#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */
-#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
-#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
-
-/*-----------------------------------------------------------------------------
-| IIC Register Offsets
-'----------------------------------------------------------------------------*/
-#define IICMDBUF 0x00
-#define IICSDBUF 0x02
-#define IICLMADR 0x04
-#define IICHMADR 0x05
-#define IICCNTL 0x06
-#define IICMDCNTL 0x07
-#define IICSTS 0x08
-#define IICEXTSTS 0x09
-#define IICLSADR 0x0A
-#define IICHSADR 0x0B
-#define IICCLKDIV 0x0C
-#define IICINTRMSK 0x0D
-#define IICXFRCNT 0x0E
-#define IICXTCNTLSS 0x0F
-#define IICDIRECTCNTL 0x10
-
-/*-----------------------------------------------------------------------------
-| UART Register Offsets
-'----------------------------------------------------------------------------*/
-#define DATA_REG 0x00
-#define DL_LSB 0x00
-#define DL_MSB 0x01
-#define INT_ENABLE 0x01
-#define FIFO_CONTROL 0x02
-#define LINE_CONTROL 0x03
-#define MODEM_CONTROL 0x04
-#define LINE_STATUS 0x05
-#define MODEM_STATUS 0x06
-#define SCRATCH 0x07
-
-/******************************************************************************
- * On Chip Memory
- ******************************************************************************/
-#define OCM_DCR_BASE 0x018
-#define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */
-#define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */
-#define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */
-#define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */
-
-/******************************************************************************
- * GPIO macro register defines
- ******************************************************************************/
-#define GPIO_BASE 0xEF600700
-#define GPIO0_OR (GPIO_BASE+0x0)
-#define GPIO0_TCR (GPIO_BASE+0x4)
-#define GPIO0_OSRH (GPIO_BASE+0x8)
-#define GPIO0_OSRL (GPIO_BASE+0xC)
-#define GPIO0_TSRH (GPIO_BASE+0x10)
-#define GPIO0_TSRL (GPIO_BASE+0x14)
-#define GPIO0_ODR (GPIO_BASE+0x18)
-#define GPIO0_IR (GPIO_BASE+0x1C)
-#define GPIO0_RR1 (GPIO_BASE+0x20)
-#define GPIO0_RR2 (GPIO_BASE+0x24)
-#define GPIO0_ISR1H (GPIO_BASE+0x30)
-#define GPIO0_ISR1L (GPIO_BASE+0x34)
-#define GPIO0_ISR2H (GPIO_BASE+0x38)
-#define GPIO0_ISR2L (GPIO_BASE+0x3C)
-
-#ifndef ASM
-/*
- * Macro for accessing the indirect EBC register
- */
-#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
-#define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd)
-
-struct ppc4xx_sys_info
-{
- unsigned long pllFwdDiv;
- unsigned long pllFwdDivB;
- unsigned long pllFbkDiv;
- unsigned long pllPlbDiv;
- unsigned long pllPciDiv;
- unsigned long pllExtBusDiv;
- unsigned long pllOpbDiv;
- unsigned long freqVCOMhz; /* in MHz */
- unsigned long freqProcessor;
- unsigned long freqPLB;
- unsigned long freqPCI;
- unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
- unsigned long pciClkSync; /* PCI clock is synchronous */
-};
-#endif /* !ASM */
-#endif /* __PPC4XX_H__ */
-
+++ /dev/null
-/* We are interested in the following hid0 bits:
- 6 - ECLK - Enable external test clock (603 only)
- 11 - DPM - Turn on dynamic power management (603 only)
- 15 - NHR - Not hard reset
- 16 - ICE - Instruction cache enable
- 17 - DCE - Data cache enable
- 18 - ILOCK - Instruction cache lock
- 19 - DLOCK - Data cache lock
- 20 - ICFI - Instruction cache invalidate
- 21 - DCFI - Data cache invalidate
- 24 - NOSER - Serial execution disable (604 only - turbo mode)
- 24 - SGE - Store gathering enable (7410 only)
- 29 - BHT - Branch history table (604 only)
-
- I made up the tags for the 604 specific bits, as they aren't
- named in the 604 book. The 603 book calls the invalidate bits
- ICFI and DCI, and I have no idea why it isn't DCFI. Maybe IBM named
- one, and Motorola named the other. */
-
-#define HID0_ECLK 0x02000000
-#define HID0_DPM 0x00100000
-#define HID0_NHR 0x00010000
-#define HID0_ICE 0x00008000
-#define HID0_DCE 0x00004000
-#define HID0_ILOCK 0x00002000
-#define HID0_DLOCK 0x00001000
-#define HID0_ICFI 0x00000800
-#define HID0_DCFI 0x00000400
-#define HID0_NOSER 0x00000080
-#define HID0_SGE 0x00000080
-#define HID0_BTIC 0x00000020
-#define HID0_BHT 0x00000004
-
-/*----------------------------------------------------------------------------+
-| Machine State Register. MSR_EE, MSR_PR, MSR_FP, MSR_ME, MSR_FE0, MSR_FE1,
-+----------------------------------------------------------------------------*/
-#define MSR_APE 0x00080000 /* wait state enable */
-#define MSR_WE 0x00040000 /* wait state enable */
-#define MSR_CE 0x00020000 /* critical interrupt enable */
-#define MSR_DWE 0x00000400 /* debug wait enable */
-#define MSR_DE 0x00000200 /* debug interrupt enable */
-#define MSR_IR 0x00000020 /* instruction relocale */
-#define MSR_DR 0x00000010 /* data relocale */
-
+++ /dev/null
-/* We are interested in the following hid0 bits:
- 6 - ECLK - Enable external test clock (603 only)
- 11 - DPM - Turn on dynamic power management (603 only)
- 15 - NHR - Not hard reset
- 16 - ICE - Instruction cache enable
- 17 - DCE - Data cache enable
- 18 - ILOCK - Instruction cache lock
- 19 - DLOCK - Data cache lock
- 20 - ICFI - Instruction cache invalidate
- 21 - DCFI - Data cache invalidate
- 24 - NOSER - Serial execution disable (604 only - turbo mode)
- 24 - SGE - Store gathering enable (7410 only)
- 29 - BHT - Branch history table (604 only)
-
- I made up the tags for the 604 specific bits, as they aren't
- named in the 604 book. The 603 book calls the invalidate bits
- ICFI and DCI, and I have no idea why it isn't DCFI. Maybe IBM named
- one, and Motorola named the other. */
-
-#define HID0_ECLK 0x02000000
-#define HID0_DPM 0x00100000
-#define HID0_NHR 0x00010000
-#define HID0_ICE 0x00008000
-#define HID0_DCE 0x00004000
-#define HID0_ILOCK 0x00002000
-#define HID0_DLOCK 0x00001000
-#define HID0_ICFI 0x00000800
-#define HID0_DCFI 0x00000400
-#define HID0_NOSER 0x00000080
-#define HID0_SGE 0x00000080
-#define HID0_BTIC 0x00000020
-#define HID0_BHT 0x00000004
-
-/*----------------------------------------------------------------------------+
-| Machine State Register. MSR_EE, MSR_PR, MSR_FP, MSR_ME, MSR_FE0, MSR_FE1,
-+----------------------------------------------------------------------------*/
-#define MSR_APE 0x00080000 /* wait state enable */
-#define MSR_WE 0x00040000 /* wait state enable */
-#define MSR_CE 0x00020000 /* critical interrupt enable */
-#define MSR_DWE 0x00000400 /* debug wait enable */
-#define MSR_DE 0x00000200 /* debug interrupt enable */
-#define MSR_IR 0x00000020 /* instruction relocale */
-#define MSR_DR 0x00000010 /* data relocale */
-
+++ /dev/null
-/*kernel/include/sys/as_archppc970.h, epos_code, epos_1.0 8/25/04 15:33:07*/
-/*----------------------------------------------------------------------------+
-| COPYRIGHT I B M CORPORATION 2003
-| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
-| US Government Users Restricted Rights - Use, duplication or
-| disclosure restricted by GSA ADP Schedule Contract with
-| IBM Corp.
-+----------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------+
-| EPOS
-| Author: Maciej P. Tyrlik
-| Component: Include file.
-| File: sys/as_archppc970.h
-| Purpose: Assembler include file for PPC970 processor.
-| Changes:
-| Date: Comment:
-| ----- --------
-| 13-Oct-03 Created MPT
-+----------------------------------------------------------------------------*/
-
-#ifndef _PPC970_H_
-#define _PPC970_H_
-
-/*----------------------------------------------------------------------------+
-| When timers are running based on CPU speed this is the timer to CPU frequency
-| ratio.
-+----------------------------------------------------------------------------*/
-#define PPC970_TB_RATIO 8
-
-/*----------------------------------------------------------------------------+
-| Cache line size.
-+----------------------------------------------------------------------------*/
-#define CACHE_LINE_SIZE_L1 128
-#define CACHE_LINE_SIZE_L2 128
-
-/*----------------------------------------------------------------------------+
-| SLB size.
-+----------------------------------------------------------------------------*/
-#define SLB_SIZE 64
-
-/*----------------------------------------------------------------------------+
-| TLB size.
-+----------------------------------------------------------------------------*/
-#define TLB_SIZE 1024
-
-/*----------------------------------------------------------------------------+
-| Special Purpose Registers. Xer (64), lr (64), ctr (64), srr0 (64), srr1 (64)
-| sprg0 (64), sprg1 (64), sprg2 (64), sprg3 (64), pvr (32) tblr (64), tbur (32)
-| registers are defined in as_archppc.h.
-+----------------------------------------------------------------------------*/
-#define SPR_ACCR 0x001D /* 64-bit read/write $*/
-#define SPR_ASR 0x0118 /* 64-bit read/write, write hypervisor only */
-#define SPR_DABR 0x03F5 /* 64-bit read/write, write hypervisor only */
-#define SPR_DABRX 0x03F7 /* 64-bit read/write, write hypervisor only */
-#define SPR_DAR 0x0013 /* 64-bit read/write */
-#define SPR_DEC 0x0016 /* 32-bit read/write */
-#define SPR_DSISR 0x0012 /* 32-bit read/write */
-#define SPR_HDEC 0x0136 /* 64-bit read/write, write hypervisor only */
-#define SPR_HID0 0x03F0 /* 64-bit read/write, write hypervisor only */
-#define SPR_HID1 0x03F1 /* 64-bit read/write, write hypervisor only */
-#define SPR_HID4 0x03F4 /* 64-bit read/write, write hypervisor only */
-#define SPR_HID5 0x03F6 /* 64-bit read/write, write hypervisor only */
-#define SPR_HIOR 0x0137 /* 64-bit read/write */
-#define SPR_HSPRG0 0x0130 /* 64-bit read/write, write hypervisor only */
-#define SPR_HSPRG1 0x0131 /* 64-bit read/write, write hypervisor only */
-#define SPR_HSRR0 0x013A /* 64-bit read/write, write hypervisor only */
-#define SPR_HSRR1 0x013B /* 64-bit read/write, write hypervisor only */
-#define SPR_IMC 0x030F /* 64-bit read/write */
-#define SPR_MMCR0 0x031B /* 64-bit read/write */
-#define SPR_MMCR1 0x031E /* 64-bit read/write */
-#define SPR_MMCRA 0x0312 /* 64-bit read/write */
-#define SPR_PIR 0x03FF /* 32-bit read */
-#define SPR_PMC1 0x0313 /* 32-bit read/write */
-#define SPR_PMC2 0x0314 /* 32-bit read/write */
-#define SPR_PMC3 0x0315 /* 32-bit read/write */
-#define SPR_PMC4 0x0316 /* 32-bit read/write */
-#define SPR_PMC5 0x0317 /* 32-bit read/write */
-#define SPR_PMC6 0x0318 /* 32-bit read/write */
-#define SPR_PMC7 0x0319 /* 32-bit read/write */
-#define SPR_PMC8 0x031A /* 32-bit read/write */
-#define SPR_SCOMC 0x0114 /* 64-bit read/write, write hypervisor only */
-#define SPR_SCOMD 0x0115 /* 64-bit read/write, write hypervisor only */
-#define SPR_SDAR 0x031D /* 64-bit read/write */
-#define SPR_SDR1 0x0019 /* 64-bit read/write, write hypervisor only */
-#define SPR_SIAR 0x031C /* 64-bit read/write */
-#define SPR_TBL_WRITE 0x011C /* 32-bit write */
-#define SPR_TBU_WRITE 0x011D /* 32-bit write */
-#define SPR_TRACE 0x03FE /* 64-bit read $*/
-#define SPR_TRIG0 0x03D0 /* 64-bit write */
-#define SPR_TRIG1 0x03D1 /* 64-bit write */
-#define SPR_TRIG2 0x03D2 /* 64-bit write */
-#define SPR_VRSAVE 0x0100 /* 64-bit read/write $*/
-
-/*----------------------------------------------------------------------------+
-| Vector status and control register is accessed using the mfvscr and mtvscr
-| instructions.
-+----------------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------------+
-| Machine State Register. MSR_EE, MSR_PR, MSR_FP, MSR_ME, MSR_FE0, MSR_FE1,
-| register bits are defined in as_archppc.h. This is a 64-bit register.
-+----------------------------------------------------------------------------*/
-#define MSR_SF 0x8000000000000000 /* 64/32 bit mode indicator */
-#define MSR_HV 0x1000000000000000 /* hypervisor mode */
-#define MSR_VMX 0x0000000002000000 /* vmx unit available */
-#define MSR_POW 0x0000000000040000 /* power management enable */
-#define MSR_SE 0x0000000000000400 /* single step */
-#define MSR_BE 0x0000000000000200 /* branch trace */
-#define MSR_IS 0x0000000000000020 /* instruction address space */
-#define MSR_DS 0x0000000000000010 /* data address space */
-#define MSR_PM 0x0000000000000004 /* performance monitor */
-#define MSR_RI 0x0000000000000002 /* recoverable interrupt */
-
-/*----------------------------------------------------------------------------+
-| HID0 bits.
-+----------------------------------------------------------------------------*/
-#define HID0_ONEPPC 0x8000000000000000
-#define HID0_SINGLE 0x4000000000000000
-#define HID0_ISYNC_SC 0x2000000000000000
-#define HID0_SERIAL_G 0x1000000000000000
-#define HID0_DEEP_NAP 0x0100000000000000
-#define HID0_NAP 0x0040000000000000
-#define HID0_DPM 0x0010000000000000
-#define HID0_TR_GR 0x0004000000000000
-#define HID0_TR_DIS 0x0002000000000000
-#define HID0_NHR 0x0001000000000000
-#define HID0_INORDER 0x0000800000000000
-#define HID0_ENH_TR 0x0000400000000000
-#define HID0_TB_CTRL 0x0000200000000000
-#define HID0_EXT_TB_EN 0x0000100000000000
-#define HID0_CIABR_EN 0x0000020000000000
-#define HID0_HDEC_EN 0x0000010000000000
-#define HID0_EB_THERM 0x0000008000000000
-#define HID0_EN_ATTN 0x0000000100000000
-#define HID0_EN_MAC 0x0000000080000000
-
-/*----------------------------------------------------------------------------+
-| HID1 bits.
-+----------------------------------------------------------------------------*/
-#define HID1_BHT_PM 0xE000000000000000
-#define HID1_BHT_STATIC 0x0000000000000000
-#define HID1_BHT_GLOBAL 0x4000000000000000
-#define HID1_BHT_LOCAL 0x8000000000000000
-#define HID1_BHT_GL_LO 0xC000000000000000
-#define HID1_BHT_GL_CO 0x6000000000000000
-#define HID1_BHT_FULL 0xE000000000000000
-#define HID1_EN_LS 0x1000000000000000
-#define HID1_EN_CC 0x0800000000000000
-#define HID1_EN_IC 0x0400000000000000
-#define HID1_PF_MASK 0x0180000000000000
-#define HID1_PF_NSA 0x0080000000000000
-#define HID1_PF_NSA_P 0x0100000000000000
-#define HID1_PF_DIS 0x0180000000000000
-#define HID1_EN_ICBI 0x0040000000000000
-#define HID1_EN_IF_CACH 0x0020000000000000
-#define HID1_EN_IC_REC 0x0010000000000000
-#define HID1_EN_ID_REC 0x0008000000000000
-#define HID1_EN_ER_REC 0x0004000000000000
-#define HID1_IC_PE 0x0002000000000000
-#define HID1_ICD0_PE 0x0001000000000000
-#define HID1_ICD1_PE 0x0000800000000000
-#define HID1_IER_PE 0x0000400000000000
-#define HID1_EN_SP_ITW 0x0000200000000000
-#define HID1_S_CHICKEN 0x0000100000000000
-
-/*----------------------------------------------------------------------------+
-| HID4 bits.
-+----------------------------------------------------------------------------*/
-#define HID4_LPES0 0x8000000000000000
-#define HID4_RMLR12_MSK 0x6000000000000000
-#define HID4_LPID25_MSK 0x1E00000000000000
-#define HID4_RMOR_MASK 0x01FFFE0000000000
-#define HID4_RM_CI 0x0000010000000000
-#define HID4_FORCE_AI 0x0000008000000000
-#define HID4_DIS_PERF 0x0000004000000000
-#define HID4_RES_PERF 0x0000002000000000
-#define HID4_EN_SP_DTW 0x0000001000000000
-#define HID4_L1DC_FLSH 0x0000000800000000
-#define HID4_D_DERAT_P1 0x0000000400000000
-#define HID4_D_DERAT_P2 0x0000000200000000
-#define HID4_D_DERAT_G 0x0000000100000000
-#define HID4_D_DERAT_S1 0x0000000040000000
-#define HID4_D_DERAT_S2 0x0000000080000000
-#define HID4_DC_TP_S1 0x0000000020000000
-#define HID4_DC_TP_S2 0x0000000010000000
-#define HID4_DC_TP_GEN 0x0000000008000000
-#define HID4_DC_SET1 0x0000000004000000
-#define HID4_DC_SET2 0x0000000002000000
-#define HID4_DC_DP_S1 0x0000000001000000
-#define HID4_DC_DP_S2 0x0000000000800000
-#define HID4_DC_DP_GEN 0x0000000000400000
-#define HID4_R_TAG1P_CH 0x0000000000200000
-#define HID4_R_TAG2P_CH 0x0000000000100000
-#define HID4_TLB_PC1 0x0000000000080000
-#define HID4_TLB_PC2 0x0000000000040000
-#define HID4_TLB_PC3 0x0000000000020000
-#define HID4_TLB_PC4 0x0000000000010000
-#define HID4_TLB_P_GEN 0x0000000000008000
-#define HID4_TLB_SET1 0x0000000000003800
-#define HID4_TLB_SET2 0x0000000000005800
-#define HID4_TLB_SET3 0x0000000000006800
-#define HID4_TLB_SET4 0x0000000000007000
-#define HID4_DIS_SLBPC 0x0000000000000400
-#define HID4_DIS_SLBPG 0x0000000000000200
-#define HID4_MCK_INJ 0x0000000000000100
-#define HID4_DIS_STFWD 0x0000000000000080
-#define HID4_LPES1 0x0000000000000040
-#define HID4_RMLR0_MSK 0x0000000000000020
-#define HID4_DIS_SPLARX 0x0000000000000008
-#define HID4_LP_PG_EN 0x0000000000000004
-#define HID4_LPID01_MSK 0x0000000000000003
-
-/*----------------------------------------------------------------------------+
-| HID5 bits.
-+----------------------------------------------------------------------------*/
-#define HID5_HRMOR_MASK 0x00000000FFFF0000
-#define HID5_DC_MCK 0x0000000000002000
-#define HID5_DIS_PWRSAV 0x0000000000001000
-#define HID5_FORCE_G 0x0000000000000800
-#define HID5_DC_REPL 0x0000000000000400
-#define HID5_HWR_STMS 0x0000000000000200
-#define HID5_DST_NOOP 0x0000000000000100
-#define HID5_DCBZ_SIZE 0x0000000000000080
-#define HID5_DCBZ32_ILL 0x0000000000000040
-#define HID5_TLB_MAP 0x0000000000000020
-#define HID5_IMQ_PORT 0x0000000000000010
-#define HID5_LMP_SIZE0 0x0000000000000008
-#define HID5_DPFLOOD 0x0000000000000004
-#define HID5_TCH_NOP 0x0000000000000002
-#define HID5_LMP_SIZE1 0x0000000000000001
-
-/*----------------------------------------------------------------------------+
-| Specific SRR1 bit definitions for Machine Check.
-+----------------------------------------------------------------------------*/
-#define SRR1_IFU_UNREC 0x0000000000200000
-#define SRR1_LOAD_STORE 0x0000000000100000
-#define SRR1_SLB_PARITY 0x0000000000040000
-#define SRR1_TLB_PARITY 0x0000000000080000
-#define SRR1_ITLB_RELOA 0x00000000000C0000
-#define SRR1_RI 0x0000000000000002
-
-#endif /* _PPC970_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-/*
- * This file contains all the macros and symbols which define
- * a PowerPC assembly language environment.
- */
-#ifndef __PPC_ASM_TMPL__
-#define __PPC_ASM_TMPL__
-
-/***************************************************************************
- *
- * These definitions simplify the ugly declarations necessary for GOT
- * definitions.
- *
- * Stolen from prepboot/bootldr.h, (C) 1998 Gabriel Paubert, paubert@iram.es
- *
- * Uses r14 to access the GOT
- */
-
-#define START_GOT \
- .section ".got2","aw"; \
-.LCTOC1 = .+32768
-
-#define END_GOT \
- .text
-
-#define GET_GOT \
- bl 1f ; \
- .text 2 ; \
-0: .long .LCTOC1-1f ; \
- .text ; \
-1: mflr r14 ; \
- lwz r0,0b-1b(r14) ; \
- add r14,r0,r14 ;
-
-#define GOT_ENTRY(NAME) .L_ ## NAME = . - .LCTOC1 ; .long NAME
-
-#define GOT(NAME) .L_ ## NAME (r14)
-
-
-/***************************************************************************
- * Register names
- */
-#define r0 0
-#define r1 1
-#define r2 2
-#define r3 3
-#define r4 4
-#define r5 5
-#define r6 6
-#define r7 7
-#define r8 8
-#define r9 9
-#define r10 10
-#define r11 11
-#define r12 12
-#define r13 13
-#define r14 14
-#define r15 15
-#define r16 16
-#define r17 17
-#define r18 18
-#define r19 19
-#define r20 20
-#define r21 21
-#define r22 22
-#define r23 23
-#define r24 24
-#define r25 25
-#define r26 26
-#define r27 27
-#define r28 28
-#define r29 29
-#define r30 30
-#define r31 31
-
-/*
- * FP register names
- */
-#define fr0 0
-#define fr1 1
-#define fr2 2
-#define fr3 3
-#define fr4 4
-#define fr5 5
-#define fr6 6
-#define fr7 7
-#define fr8 8
-#define fr9 9
-#define fr10 10
-#define fr11 11
-#define fr12 12
-#define fr13 13
-#define fr14 14
-#define fr15 15
-#define fr16 16
-#define fr17 17
-#define fr18 18
-#define fr19 19
-#define fr20 20
-#define fr21 21
-#define fr22 22
-#define fr23 23
-#define fr24 24
-#define fr25 25
-#define fr26 26
-#define fr27 27
-#define fr28 28
-#define fr29 29
-#define fr30 30
-#define fr31 31
-
-/* Some special registers */
-
-#define TBRU 269 /* Time base Upper/Lower (Reading) */
-#define TBRL 268
-#define TBWU 284 /* Time base Upper/Lower (Writing) */
-#define TBWL 285
-#define XER 1
-#define LR 8
-#define CTR 9
-#define HID0 1008 /* Hardware Implementation */
-#define PVR 287 /* Processor Version */
-#define SDR1 25 /* MMU hash base register */
-#define DAR 19 /* Data Address Register */
-#define SPR0 272 /* Supervisor Private Registers */
-#define SPRG0 272
-#define SPR1 273
-#define SPRG1 273
-#define SPR2 274
-#define SPRG2 274
-#define SPR3 275
-#define SPRG3 275
-#define DSISR 18
-#define SRR0 26 /* Saved Registers (exception) */
-#define SRR1 27
-#define DEC 22 /* Decrementer */
-#define EAR 282 /* External Address Register */
-#define ICR 148 /* Interrupt Cause Register (37-44) */
-#define DER 149
-#define COUNTA 150 /* Breakpoint Counter (37-44) */
-#define COUNTB 151 /* Breakpoint Counter (37-44) */
-#define LCTRL1 156 /* Load/Store Support (37-40) */
-#define LCTRL2 157 /* Load/Store Support (37-41) */
-#define ICTRL 158
-
-/* Registers in the processor's internal memory map that we use.
-*/
-#define IMMR 0xff000000
-
-#define SYPCR 0x00000004
-#define BR0 0x00000100
-#define OR0 0x00000104
-#define BR1 0x00000108
-#define OR1 0x0000010c
-#define BR2 0x00000110
-#define OR2 0x00000114
-#define BR3 0x00000118
-#define OR3 0x0000011c
-#define BR4 0x00000120
-#define OR4 0x00000124
-
-#define MAR 0x00000164
-#define MCR 0x00000168
-#define MAMR 0x00000170
-#define MBMR 0x00000174
-#define MSTAT 0x00000178
-#define MPTPR 0x0000017a
-#define MDR 0x0000017c
-
-#define TBSCR 0x00000200
-#define TBREFF0 0x00000204
-
-#define PLPRCR 0x00000284
-
-#define curptr r2
-
-#define SYNC \
- sync; \
- isync
-
-/*
- * Macros for storing registers into and loading registers from
- * exception frames.
- */
-#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
-#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
-#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
-#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
-#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
-#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
-#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
-#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
-#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
-#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
-
-/*
- * GCC sometimes accesses words at negative offsets from the stack
- * pointer, although the SysV ABI says it shouldn't. To cope with
- * this, we leave this much untouched space on the stack on exception
- * entry.
- */
-#define STACK_UNDERHEAD 64
-
-#if 0 /* we don't use virtual addresses in PPCBOOT */
-#define tophys(rd,rs,rt) addis rd,rs,-KERNELBASE@h
-#define tovirt(rd,rs,rt) addis rd,rs,KERNELBASE@h
-#else
-#define tophys(rd,rs,rt) mr rd,rs
-#define tovirt(rd,rs,rt) mr rd,rs
-#endif
-
-/*
- * Exception entry code. This code runs with address translation
- * turned off, i.e. using physical addresses.
- * We assume sprg3 has the physical address of the current
- * task's thread_struct.
- */
-#define EXCEPTION_PROLOG \
- mtspr SPRG0,r20; \
- mtspr SPRG1,r21; \
- mfcr r20; \
- tophys(r21,r1,r21); /* use tophys(kernel sp) otherwise */ \
- subi r21,r21,INT_FRAME_SIZE+STACK_UNDERHEAD; /* alloc exc. frame */\
-1: stw r20,_CCR(r21); /* save registers */ \
- stw r22,GPR22(r21); \
- stw r23,GPR23(r21); \
- mfspr r20,SPRG0; \
- stw r20,GPR20(r21); \
- mfspr r22,SPRG1; \
- stw r22,GPR21(r21); \
- mflr r20; \
- stw r20,_LINK(r21); \
- mfctr r22; \
- stw r22,_CTR(r21); \
- mfspr r20,XER; \
- stw r20,_XER(r21); \
- mfspr r22,SRR0; \
- mfspr r23,SRR1; \
- stw r0,GPR0(r21); \
- stw r1,GPR1(r21); \
- stw r2,GPR2(r21); \
- stw r1,0(r21); \
- tovirt(r1,r21,r1); /* set new kernel sp */ \
- SAVE_4GPRS(3, r21);
-/*
- * Note: code which follows this uses cr0.eq (set if from kernel),
- * r21, r22 (SRR0), and r23 (SRR1).
- */
-
-/*
- * Exception vectors.
- *
- * The data words for `hdlr' and `int_return' are initialized with
- * OFFSET values only; they must be relocated first before they can
- * be used!
- */
-#define STD_EXCEPTION(n, label, hdlr) \
- . = n; \
-label: \
- EXCEPTION_PROLOG; \
- lwz r3,GOT(transfer_to_handler); \
- mtlr r3; \
- addi r3,r1,STACK_FRAME_OVERHEAD; \
- li r20,MSR_KERNEL; \
- blrl ; \
-.L_ ## label : \
- .long hdlr - _start + EXC_OFF_SYS_RESET; \
- .long int_return - _start + EXC_OFF_SYS_RESET
-
-
-#endif /* __PPC_ASM_TMPL__ */
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* In the MSR, not all bits are interesting to us
- 16 - EE - External interrupts
- 17 - PR - Privilege level
- 18 - FP - Floating Point available
- 19 - ME - Machine check exception enable
- 20 - FE0 - Floating exception mode 0
- 23 - FE1 - Floating exception mode 1
- MSR_MASK is the bits we do not change.
- */
-
-#define MSR_MASK 0xfff8008c
-#define MSR_EE 0x00008000
-#define MSR_PR 0x00004000
-#define MSR_FP 0x00002000
-#define MSR_ME 0x00001000
-#define MSR_FE0 0x00000800
-#define MSR_FE1 0x00000100
-
-#define MSR_DEFAULT (MSR_FP | MSR_IR | MSR_DR)
-
-/*
- * BAT defines
- */
-
-/*
- * BL field in upper BAT register
- */
-#define BAT_BL_128K 0x00000000
-#define BAT_BL_256K 0x00000004
-#define BAT_BL_512K 0x0000000C
-#define BAT_BL_1M 0x0000001C
-#define BAT_BL_2M 0x0000003C
-#define BAT_BL_4M 0x0000007C
-#define BAT_BL_8M 0x000000FC
-#define BAT_BL_16M 0x000001FC
-#define BAT_BL_32M 0x000003FC
-#define BAT_BL_64M 0x000007FC
-#define BAT_BL_128M 0x00000FFC
-#define BAT_BL_256M 0x00001FFC
-
-/*
- * Supervisor/user valid mode in upper BAT register
- */
-#define BAT_VALID_SUPERVISOR 0x00000002
-#define BAT_VALID_USER 0x00000001
-#define BAT_INVALID 0x00000000
-
-/*
- * WIMG bit setting in lower BAT register
- */
-#define BAT_WRITE_THROUGH 0x00000040
-#define BAT_CACHE_INHIBITED 0x00000020
-#define BAT_COHERENT 0x00000010
-#define BAT_GUARDED 0x00000008
-
-/*
- * Protection bits in lower BAT register
- */
-#define BAT_NO_ACCESS 0x00000000
-#define BAT_READ_ONLY 0x00000001
-#define BAT_READ_WRITE 0x00000002
-
-/* Processor Version Register */
-
-/* Processor Version Register (PVR) field extraction */
-
-#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
-#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
-
-/*
- * IBM has further subdivided the standard PowerPC 16-bit version and
- * revision subfields of the PVR for the PowerPC 403s into the following:
- */
-
-#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */
-#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */
-#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */
-#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */
-#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
-#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
-
-/* Processor Version Numbers */
-
-#define PVR_403GA 0x00200000
-#define PVR_403GB 0x00200100
-#define PVR_403GC 0x00200200
-#define PVR_403GCX 0x00201400
-#define PVR_405GP 0x40110000
-#define PVR_405GP_RB 0x40110040
-#define PVR_405GP_RC 0x40110082
-#define PVR_405GP_RD 0x401100C4
-#define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */
-#define PVR_405CR_RA 0x40110041
-#define PVR_405CR_RB 0x401100C5
-#define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */
-#define PVR_405GPR_RB 0x50910951
-#define PVR_440GP_RB 0x40120440
-#define PVR_440GP_RC 0x40120481
-#define PVR_405EP_RB 0x51210950
-#define PVR_601 0x00010000
-#define PVR_602 0x00050000
-#define PVR_603 0x00030000
-#define PVR_603e 0x00060000
-#define PVR_603ev 0x00070000
-#define PVR_603r 0x00071000
-#define PVR_604 0x00040000
-#define PVR_604e 0x00090000
-#define PVR_604r 0x000A0000
-#define PVR_620 0x00140000
-#define PVR_740 0x00080000
-#define PVR_750 PVR_740
-#define PVR_740P 0x10080000
-#define PVR_750P PVR_740P
-/*
- * For the 8xx processors, all of them report the same PVR family for
- * the PowerPC core. The various versions of these processors must be
- * differentiated by the version number in the Communication Processor
- * Module (CPM).
- */
-#define PVR_821 0x00500000
-#define PVR_823 PVR_821
-#define PVR_850 PVR_821
-#define PVR_860 PVR_821
-#define PVR_7400 0x000C0000
-#define PVR_8240 0x00810100
-#define PVR_8260 PVR_8240
-
-/*----------------------------------------------------------------------------+
-| Processor Version Register (PVR) values
-+----------------------------------------------------------------------------*/
-#define PVR_970 0x0039 /* 970 any revision*/
-#define PVR_970DD_1_0 0x00391100 /* 970 DD1.0 */
-#define PVR_970FX 0x003C /* 970FX any revision*/
-#define PVR_970FX_DD_2_0 0x003C0200 /* 970FX DD2.0 */
-#define PVR_970FX_DD_2_1 0x003C0201 /* 970FX DD2.1 */
-#define PVR_970FX_DD_3_0 0x003C0300 /* 970FX DD3.0 */
-#define PVR_RESERVED 0x000000F0 /* reserved nibble */
-
-#define SPR_SRR0 0x01a
-#define SPR_SRR1 0x01b
-#define SPR_SPRG0 0x110
-#define SPR_SPRG1 0x111
-#define SPR_SPRG2 0x112
-#define SPR_SPRG3 0x113
-#define SPR_PVR 0x11f
-#define SPR_TBLR 0x10c
-#define SPR_TBUR 0x10d
-
-#ifdef __PPC64__
-#define LOAD_64BIT_VAL(ra,value) addis ra,r0,value@highest; \
- ori ra,ra,value@higher; \
- sldi ra,ra,32; \
- oris ra,ra,value@h; \
- ori ra,ra,value@l
-#define TLBIEL(rb) .long 0x7C000000|\
- (rb<<11)|(274<<1)
-#define HRFID() .long 0x4C000000|\
- (274<<1)
-#endif
-
-#ifndef ASM
-unsigned __getmsr(void);
-void __setmsr(unsigned value);
-unsigned __gethid0(void);
-unsigned __gethid1(void);
-void __sethid0(unsigned value);
-unsigned __getpvr(void);
-#endif
-
+++ /dev/null
-#ifndef _PRINTK_H
-#define _PRINTK_H
-#include <console/loglevel.h>
-
-extern int do_printk(int, const char *, ...);
-
-#define printk_emerg(fmt, arg...) do_printk(BIOS_EMERG ,fmt, ##arg)
-#define printk_alert(fmt, arg...) do_printk(BIOS_ALERT ,fmt, ##arg)
-#define printk_crit(fmt, arg...) do_printk(BIOS_CRIT ,fmt, ##arg)
-#define printk_err(fmt, arg...) do_printk(BIOS_ERR ,fmt, ##arg)
-#define printk_warning(fmt, arg...) do_printk(BIOS_WARNING ,fmt, ##arg)
-#define printk_notice(fmt, arg...) do_printk(BIOS_NOTICE ,fmt, ##arg)
-#define printk_info(fmt, arg...) do_printk(BIOS_INFO ,fmt, ##arg)
-#define printk_debug(fmt, arg...) do_printk(BIOS_DEBUG ,fmt, ##arg)
-#define printk_spew(fmt, arg...) do_printk(BIOS_SPEW ,fmt, ##arg)
-
-#endif /* _PRINTK_H */
-
+++ /dev/null
-#ifndef _SDRAM_H
-#define _SDRAM_H
-
-/*
- * Provided for all PPC boards to do SDRAM initialization. This
- * happens prior to entry into hardwaremain().
- */
-extern void memory_init(void);
-#endif /* _SDRAM_H */
+++ /dev/null
-#ifndef PPC_STDDEF_H
-#define PPC_STDDEF_H
-
-typedef long ptrdiff_t;
-typedef unsigned long size_t;
-typedef long ssize_t;
-
-typedef int wchar_t;
-typedef unsigned int wint_t;
-
-#define NULL 0
-
-#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
-
-#endif /* PPC_STDDEF_H */
+++ /dev/null
-#ifndef PPC_STDINT_H
-#define PPC_STDINT_H
-
-/* Exact integral types */
-typedef unsigned char uint8_t;
-typedef signed char int8_t;
-
-typedef unsigned short uint16_t;
-typedef signed short int16_t;
-
-typedef unsigned int uint32_t;
-typedef signed int int32_t;
-
-typedef unsigned long long uint64_t;
-typedef signed long long int64_t;
-
-/* Small types */
-typedef unsigned char uint_least8_t;
-typedef signed char int_least8_t;
-
-typedef unsigned short uint_least16_t;
-typedef signed short int_least16_t;
-
-typedef unsigned int uint_least32_t;
-typedef signed int int_least32_t;
-
-typedef unsigned long long uint_least64_t;
-typedef signed long long int_least64_t;
-
-/* Fast Types */
-typedef unsigned char uint_fast8_t;
-typedef signed char int_fast8_t;
-
-typedef unsigned int uint_fast16_t;
-typedef signed int int_fast16_t;
-
-typedef unsigned int uint_fast32_t;
-typedef signed int int_fast32_t;
-
-typedef unsigned long long uint_fast64_t;
-typedef signed long long int_fast64_t;
-
-/* Types for `void *' pointers. */
-typedef int intptr_t;
-typedef unsigned int uintptr_t;
-
-/* Largest integral types */
-typedef long long int intmax_t;
-typedef unsigned long long uintmax_t;
-
-typedef uint8_t u8;
-typedef uint16_t u16;
-typedef uint32_t u32;
-typedef uint64_t u64;
-
-#endif /* PPC_STDINT_H */
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _TIMER_H
-#define __TIMER_H
-
-unsigned long get_hz(void);
-unsigned long ticks_since_boot(void);
-void sleep_ticks(unsigned long);
-void udelay(int);
-
-#endif
+++ /dev/null
-init crt0.S.lb
-initobject ppc_main.o
+++ /dev/null
-/* Copyright 2000 AG Electronics Ltd. */
-/* This code is distributed without warranty under the GPL v2 (see COPYING) */
-
-#define ASM
-#include "ppcreg.h"
-#include <ppc_asm.tmpl>
-
-.section ".rom.reset", "ax", @progbits
-
-.globl _start
-_start:
- b system_reset
-
-.section ".rom.exception_vectors", "ax", @progbits
-
-%%EXCEPTION_VECTOR_TABLE%%
-
-.section ".rom.data", "a", @progbits
-.section ".rom.text", "ax", @progbits
-
-system_reset:
-
- /*
- * Do processor family initialization
- */
-%%FAMILY_INIT%%
-
- /*
- * Do processor specific initialization
- */
-%%PROCESSOR_INIT%%
-
-#if CONFIG_USE_DCACHE_RAM == 1
-#define DCACHE_RAM_END (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - 1)
- /*
- * Initialize data cache blocks
- * (assumes cache block size of 32 bytes)
- *
- * NOTE: This may need to be moved to FAMILY_INIT if
- * dcbz is not supported on all CPU's
- */
- lis r1, CONFIG_DCACHE_RAM_BASE@h
- ori r1, r1, CONFIG_DCACHE_RAM_BASE@l
- li r3, (CONFIG_DCACHE_RAM_SIZE / 32)
- mtctr r3
-0: dcbz r0, r1
- addi r1, r1, 32
- bdnz 0b
-
- /*
- * Set up stack in cache. The SP must be 16-byte (4-word) aligned
- * for SYSV EABI or 8-byte (2-word) aligned for PPC EABI, so we make
- * it 16-byte aligned to cover both cases. Also we have to ensure that
- * the first word is located within the cache.
- */
- lis r1, (CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE)@h
- ori r1, r1, (CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE)@l
- lis r0, 0
- stwu r0, -4(r1)
- stwu r0, -4(r1)
- stwu r0, -4(r1)
- stwu r0, -4(r1)
-
-#if 0
- /*
- * Clear stack
- */
- lis r4, CONFIG_DCACHE_RAM_BASE@h
- ori r4, r4, CONFIG_DCACHE_RAM_BASE@l
- lis r7, DCACHE_RAM_END@h
- ori r7, r7, DCACHE_RAM_END@l
- lis r5, 0
-1: stwx r5, 0, r4
- addi r4, r4, 4
- cmp 0, 0, r4, r7
- ble 1b
- sync
-#endif
-
- /*
- * Set up the EABI pointers, before we enter any C code
- */
- lis r13, _SDA_BASE_@h
- ori r13, r13, _SDA_BASE_@l
- lis r2, _SDA2_BASE_@h
- ori r2, r2, _SDA2_BASE_@l
-
- /*
- * load start address into SRR0 for rfi
- */
- lis r3, ppc_main@h
- ori r3, r3, ppc_main@l
- mtspr SRR0, r3
-
- /*
- * load the current MSR into SRR1 so that it will be copied
- * back into MSR on rfi
- */
- mfmsr r4
- mtspr SRR1, r4 // load SRR1 with r4
-
- /*
- * If something returns after rfi then die
- */
- lis r3, dead@h
- ori r3, r3, dead@l
- mtlr r3
-
- /*
- * Complete rest of initialization in C (ppc_main)
- */
- rfi
-#endif /* CONFIG_USE_DCACHE_RAM */
-
- /*
- * Stop here if something goes wrong
- */
-dead:
- b dead
- /*NOTREACHED*/
-
-/* Remove need for ecrti.o and ectrn.o */
-.globl __init
-__init:
-.globl __fini
-__fini:
-.globl __CTOR_LIST__
-__CTOR_LIST__:
-.globl __CTOR_END__
-__CTOR_END__:
-.globl __DTOR_LIST__
-__DTOR_LIST__:
-.globl __DTOR_END__
-__DTOR_END__:
- blr
-
-%%NORTHBRIDGE_INIT%%
+++ /dev/null
-/*
- * Memory map:
- *
- * CONFIG_ROMBASE : start of ROM
- * CONFIG_RESET : reset vector (may be at top of ROM)
- * _EXCEPTIONS_VECTORS : exception table
- *
- * CONFIG_ROMSTART : coreboot text
- * : payload text
- *
- * CONFIG_RAMBASE : address to copy payload
- */
-
-/*
- * Written by Johan Rydberg, based on work by Daniel Kahlin.
- * Rewritten by Eric Biederman
- * Re-rewritten by Greg Watson for PPC
- */
-
-/*
- * We use ELF as output format. So that we can
- * debug the code in some form.
- */
-
-OUTPUT_FORMAT("elf32-powerpc")
-ENTRY(_start)
-
-TARGET(binary)
-INPUT(coreboot_ram.rom)
-SECTIONS
-{
- /*
- * Absolute location of base of ROM
- */
- . = CONFIG_ROMBASE;
-
- /*
- * Absolute location of reset vector. This may actually be at the
- * the top of ROM.
- */
- . = CONFIG_RESET;
- .reset . : {
- *(.rom.reset);
- . = ALIGN(16);
- }
-
- /*
- * Absolute location of exception vector table.
- */
- . = CONFIG_EXCEPTION_VECTORS;
- .exception_vectors . : {
- *(.rom.exception_vectors);
- . = ALIGN(16);
- }
-
- /*
- * Absolute location of coreboot initialization code in ROM.
- */
- . = CONFIG_ROMSTART;
- .rom . : {
- _rom = .;
- *(.rom.text);
- *(.text);
- *(.rom.data);
- *(.rodata);
- *(EXCLUDE_FILE(coreboot_ram.rom) .data);
- . = ALIGN(16);
- _erom = .;
- }
- _lrom = LOADADDR(.rom);
- _elrom = LOADADDR(.rom) + SIZEOF(.rom);
-
- /*
- * Ram is the coreboot code that runs from RAM.
- */
- .ram . : {
- _ram = . ;
- coreboot_ram.rom(*)
- _eram = . ;
- }
-
- .sdata : {
- _SDA_BASE_ = .;
- *(.sdata)
- }
-
- .sdata2 : {
- _SDA2_BASE_ = .;
- *(.sdata2)
- }
-
-
-
- /*
- * Absolute location of where coreboot will be relocated in RAM.
- */
- _iseg = CONFIG_RAMBASE;
- _eiseg = _iseg + SIZEOF(.ram);
- _liseg = _ram;
- _eliseg = _eram;
-
- /DISCARD/ : {
- *(.comment)
- *(.note)
- }
-}
+++ /dev/null
-/*
- * Copyright (C) 2003 by Greg Watson, Los Alamos National Laboratory
- * gwatson@lanl.gov
- */
-
-#include <board.h>
-#include <sdram.h>
-#include <cbfs.h>
-
-/*
- * At this point we're running out of flash with our
- * stack in cache ram. We need to do the following:
- *
- * - turn on real memory
- * - relocate our payload into real memory
- * - start hardwaremain() which does remainder of setup
- */
-
-extern void flush_dcache(void);
-
-void ppc_main(void)
-{
- void (*payload)(void);
-
- /*
- * very early board initialization
- */
- board_init();
-
- /*
- * turn on memory
- */
- memory_init();
-
- /*
- * final initialization before jumping to payload
- */
- board_init2();
-
- /*
- * Flush cache now that memory is enabled.
- */
- flush_dcache();
-
- /*
- * Relocate payload (text & data)
- */
- payload = cbfs_load_stage("fallback/coreboot_ram");
- payload();
-
- /* NOT REACHED */
-}
+++ /dev/null
-object c_start.S
-object pci_ppc_conf1_ops.o
-object pci_dev.o
-object timer.o
-object cpuid.o
-object cpu.o
-object ppc.o
-object timebase.S
-object floats.S
-object div64.S
-object abort.o
-initobject pci_dev.o
-initobject printk_init.o
-initobject timebase.S
-initobject timer.o
-initobject floats.S
-initobject div64.S
-initobject ppc.o
-initobject abort.o
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* gcc produces calls to an abort function in their trampoline code on powerpc
- * 32bit platforms.
- * This trampoline code is emitted for example in nested functions.
- */
-
-void abort(void)
-{
- /* We would want to call die() here, but it might not be available at
- * this point, so for now we have to die silently.
- */
- for (;;) ;
-}
-
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/*
- * The assumption is that we're located in ROM and we have a fake stack
- * located in cache. Our task is to turn on memory proper, the finish
- * configuring the machine.
- */
-
-#define ASM
-#include "ppcreg.h"
-#include <ppc_asm.tmpl>
-
-.section ".text"
-.globl _start
-
-_start:
- /*
- * init stack pointer to real ram now that memory is on
- * Note: We use the last 8 bytes on the stack to hold struct cpu_info,
- * Which are initialized to zero as we clear the stack.
- */
- li r0, 0
- lis r1, _estack@ha
- addi r1, r1, _estack@l
- stwu r0,-64(r1)
- stwu r1,-24(r1)
-
- /*
- * Clear stack
- */
- lis r4, _stack@ha
- addi r4, r4, _stack@l
- lis r7, _estack@ha
- addi r7, r7, _estack@l
- lis r5, 0
-1: stwx r5, 0, r4
- addi r4, r4, 4
- cmp 0, 0, r4, r7
- ble 1b
- sync
-
- /*
- * Clear bss
- */
- lis r4, _bss@ha
- addi r4, r4, _bss@l
- lis r7, _ebss@ha
- addi r7, r7, _ebss@l
- lis r5, 0
-1: stwx r5, 0, r4
- addi r4, r4, 4
- cmp 0, 0, r4, r7
- ble 1b
- sync
-
- /*
- * Set up the EABI pointers, before we enter any C code
- */
- lis r13, _SDA_BASE_@ha
- addi r13, r13, _SDA_BASE_@l
- lis r2, _SDA2_BASE_@ha
- addi r2, r2, _SDA2_BASE_@l
-
- /*
- * load start address into SRR0 for rfi
- */
- lis r3, hardwaremain@ha
- addi r3, r3, hardwaremain@l
- mtspr SRR0, r3
-
- /*
- * load the current MSR into SRR1 so that it will be copied
- * back into MSR on rfi
- */
- mfmsr r4
- mtspr SRR1, r4 // load SRR1 with r4
-
- /*
- * If something returns after rfi then die
- */
- lis r3, dead@ha
- addi r3, r3, dead@l
- mtlr r3
-
- /*
- * Complete rest of initialization in C (hardwaremain)
- */
- rfi
-
- /*
- * Stop here if something goes wrong
- */
-dead:
- b dead
- /*NOTREACHED*/
-
-/* Remove need for ecrti.o and ectrn.o */
-.globl __init
-__init:
-.globl __fini
-__fini:
-.globl __CTOR_LIST__
-__CTOR_LIST__:
-.globl __CTOR_END__
-__CTOR_END__:
-.globl __DTOR_LIST__
-__DTOR_LIST__:
-.globl __DTOR_END__
-__DTOR_END__:
- blr
+++ /dev/null
-#include <console/console.h>
-#include <arch/io.h>
-#include <string.h>
-#include <device/device.h>
-#include <cpu/cpu.h>
-#include <cpu/ppc/cpuid.h>
-#include "ppc.h"
-#include "ppcreg.h"
-
-#if 0
-static void set_cpu_ops(struct device *cpu)
-{
- struct cpu_driver *driver;
- cpu->ops = 0;
- for (driver = cpu_drivers; driver < ecpu_drivers; driver++) {
- struct cpu_device_id *id;
- for(id = driver->id_table; id->pvr != 0; id++) {
- if (cpu->device == id->pvr)
- {
- goto found;
- }
- }
- }
- die("Unknown cpu");
- return;
- found:
- cpu->ops = driver->ops;
-}
-#endif
-
-void cpu_initialize(void)
-{
- /* Because we busy wait at the printk spinlock.
- * It is important to keep the number of printed messages
- * from secondary cpus to a minimum, when debugging is
- * disabled.
- */
- struct device *cpu;
- struct cpu_info *info;
- info = cpu_info();
-
- printk_notice("Initializing CPU #%d\n", info->index);
-
- cpu = info->cpu;
- if (!cpu) {
- die("CPU: missing cpu device structure");
- }
-
- /* Find what type of cpu we are dealing with */
- cpu->vendor = 0; /* PPC cpus do not have a vendor field */
- cpu->device = ppc_getpvr();
- display_cpuid(cpu);
-
-#if 0
- /* Lookup the cpu's operations */
- set_cpu_ops(cpu);
-
- /* Initialize the cpu */
- if (cpu->ops && cpu->ops->init) {
- cpu->enabled = 1;
- cpu->initialized = 1;
- cpu->ops->init();
- }
-#endif
- /* Turn on caching if we haven't already */
-
- printk_info("CPU #%d initialized\n", info->index);
- return;
-}
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include "ppc.h"
-#include "ppcreg.h"
-#include <device/device.h>
-#include <console/console.h>
-
-void display_cpuid(struct device *cpu)
-{
- unsigned type = cpu->device >> 16;
- unsigned version = cpu->device & 0xffff;
- const char *cpu_string = 0;
- switch(type) {
- case 0x0001:
- cpu_string = "601";
- break;
- case 0x0003:
- cpu_string = "603";
- break;
- case 0x0004:
- cpu_string = "604";
- break;
- case 0x0006:
- cpu_string = "603e";
- break;
- case 0x0007:
- cpu_string = "603ev";
- break;
- case 0x0008:
- cpu_string = "750";
- break;
- case 0x0009:
- cpu_string = "604e";
- break;
- case 0x000a:
- cpu_string = "604ev5 (MachV)";
- break;
- case 0x000c:
- cpu_string = "7400";
- break;
- case 0x0032:
- cpu_string = "821";
- break;
- case 0x0050:
- cpu_string = "860";
- break;
- case 0x4011:
- cpu_string = "405GP";
- break;
- case 0x5091:
- cpu_string = "405GPr";
- break;
- case 0x5121:
- cpu_string = "405EP";
- break;
- case 0x800c:
- cpu_string = "7410";
- break;
- }
- if (cpu_string)
- printk_info("PowerPC %s", cpu_string);
- else
- printk_info("PowerPC unknown (0x%x)", type);
- printk_info(" CPU, version %d.%d\n", version >> 8, version & 0xff);
-}
-
+++ /dev/null
-/*
- * Divide a 64-bit unsigned number by a 32-bit unsigned number.
- * This routine assumes that the top 32 bits of the dividend are
- * non-zero to start with.
- * On entry, r3 points to the dividend, which get overwritten with
- * the 64-bit quotient, and r4 contains the divisor.
- * On exit, r3 contains the remainder.
- *
- * Copyright (C) 2002 Paul Mackerras, IBM Corp.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#include <ppc_asm.tmpl>
-
- .globl __div64_32
-__div64_32:
- lwz r5,0(r3) # get the dividend into r5/r6
- lwz r6,4(r3)
- cmplw r5,r4
- li r7,0
- li r8,0
- blt 1f
- divwu r7,r5,r4 # if dividend.hi >= divisor,
- mullw r0,r7,r4 # quotient.hi = dividend.hi / divisor
- subf. r5,r0,r5 # dividend.hi %= divisor
- beq 3f
-1: mr r11,r5 # here dividend.hi != 0
- andis. r0,r5,0xc000
- bne 2f
- cntlzw r0,r5 # we are shifting the dividend right
- li r10,-1 # to make it < 2^32, and shifting
- srw r10,r10,r0 # the divisor right the same amount,
- add r9,r4,r10 # rounding up (so the estimate cannot
- andc r11,r6,r10 # ever be too large, only too small)
- andc r9,r9,r10
- or r11,r5,r11
- rotlw r9,r9,r0
- rotlw r11,r11,r0
- divwu r11,r11,r9 # then we divide the shifted quantities
-2: mullw r10,r11,r4 # to get an estimate of the quotient,
- mulhwu r9,r11,r4 # multiply the estimate by the divisor,
- subfc r6,r10,r6 # take the product from the divisor,
- add r8,r8,r11 # and add the estimate to the accumulated
- subfe. r5,r9,r5 # quotient
- bne 1b
-3: cmplw r6,r4
- blt 4f
- divwu r0,r6,r4 # perform the remaining 32-bit division
- mullw r10,r0,r4 # and get the remainder
- add r8,r8,r0
- subf r6,r10,r6
-4: stw r7,0(r3) # return the quotient in *r3
- stw r8,4(r3)
- mr r3,r6 # return the remainder in r3
- blr
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 1999-2000 AG Electronics Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <ppc_asm.tmpl>
-
- .globl ppc_init_float_registers
-
-ppc_init_float_registers:
- lfd fr0, 0(r3)
- lfd fr1, 0(r3)
- lfd fr2, 0(r3)
- lfd fr3, 0(r3)
- lfd fr4, 0(r3)
- lfd fr5, 0(r3)
- lfd fr6, 0(r3)
- lfd fr7, 0(r3)
- lfd fr8, 0(r3)
- lfd fr9, 0(r3)
- lfd fr10, 0(r3)
- lfd fr11, 0(r3)
- lfd fr12, 0(r3)
- lfd fr13, 0(r3)
- lfd fr14, 0(r3)
- lfd fr15, 0(r3)
- lfd fr16, 0(r3)
- lfd fr17, 0(r3)
- lfd fr18, 0(r3)
- lfd fr19, 0(r3)
- lfd fr20, 0(r3)
- lfd fr21, 0(r3)
- lfd fr22, 0(r3)
- lfd fr23, 0(r3)
- lfd fr24, 0(r3)
- lfd fr25, 0(r3)
- lfd fr26, 0(r3)
- lfd fr27, 0(r3)
- lfd fr28, 0(r3)
- lfd fr29, 0(r3)
- lfd fr30, 0(r3)
- lfd fr31, 0(r3)
- blr
-
- .end
-
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 1999-2000 AG Electronics Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* .text*/
- .globl _init_float_registers
-
-_init_float_registers:
- lfd 0, 0(3)
- lfd 1, 0(3)
- lfd 2, 0(3)
- lfd 3, 0(3)
- lfd 4, 0(3)
- lfd 5, 0(3)
- lfd 6, 0(3)
- lfd 7, 0(3)
- lfd 8, 0(3)
- lfd 9, 0(3)
- lfd 10, 0(3)
- lfd 11, 0(3)
- lfd 12, 0(3)
- lfd 13, 0(3)
- lfd 14, 0(3)
- lfd 15, 0(3)
- lfd 16, 0(3)
- lfd 17, 0(3)
- lfd 18, 0(3)
- lfd 19, 0(3)
- lfd 20, 0(3)
- lfd 21, 0(3)
- lfd 22, 0(3)
- lfd 23, 0(3)
- lfd 24, 0(3)
- lfd 25, 0(3)
- lfd 26, 0(3)
- lfd 27, 0(3)
- lfd 28, 0(3)
- lfd 29, 0(3)
- lfd 30, 0(3)
- lfd 31, 0(3)
- blr
- .end
-
+++ /dev/null
-#include <arch/io.h>
-#include <arch/pciconf.h>
-
-/*
- * Direct access to PCI hardware...
- */
-
-uint8_t pci_ppc_read_config8(unsigned char bus, int devfn, int where)
-{
- uint8_t res;
-
- out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
- res = in_8((unsigned char *)CONFIG_PCIC0_CFGDATA + (where & 3));
- return res;
-}
-
-uint16_t pci_ppc_read_config16(unsigned char bus, int devfn, int where)
-{
- uint16_t res;
-
- out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
- res = in_le16((unsigned short *)CONFIG_PCIC0_CFGDATA + (where & 2));
- return res;
-}
-
-uint32_t pci_ppc_read_config32(unsigned char bus, int devfn, int where)
-{
- uint32_t res;
-
- out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
- res = in_le32((unsigned *)CONFIG_PCIC0_CFGDATA);
- return res;
-}
-
-int pci_ppc_write_config8(unsigned char bus, int devfn, int where, uint8_t data)
-{
- out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
- out_8((unsigned char *)CONFIG_PCIC0_CFGDATA + (where & 3), data);
- return 0;
-}
-
-int pci_ppc_write_config16(unsigned char bus, int devfn, int where, uint16_t data)
-{
- out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
- out_le16((unsigned short *)CONFIG_PCIC0_CFGDATA + (where & 2), data);
- return 0;
-}
-
-int pci_ppc_write_config32(unsigned char bus, int devfn, int where, uint32_t data)
-{
- out_le32((unsigned *)CONFIG_PCIC0_CFGADDR, CONFIG_CMD(bus, devfn, where));
- out_le32((unsigned *)CONFIG_PCIC0_CFGDATA, data);
- return 0;
-}
+++ /dev/null
-#include <console/console.h>
-#include <arch/pciconf.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-
-static uint8_t ppc_conf1_read_config8(struct bus *pbus, unsigned char bus, int devfn, int where)
-{
- return pci_ppc_read_config8(bus, devfn, where);
-}
-
-static uint16_t ppc_conf1_read_config16(struct bus *pbus, unsigned char bus, int devfn, int where)
-{
- return pci_ppc_read_config16(bus, devfn, where);
-}
-
-static uint32_t ppc_conf1_read_config32(struct bus *pbus, unsigned char bus, int devfn, int where)
-{
- return pci_ppc_read_config32(bus, devfn, where);
-}
-
-static void ppc_conf1_write_config8(struct bus *pbus, unsigned char bus, int devfn, int where, uint8_t val)
-{
- pci_ppc_write_config8(bus, devfn, where, val);
-}
-
-static void ppc_conf1_write_config16(struct bus *pbus, unsigned char bus, int devfn, int where, uint16_t val)
-{
- pci_ppc_write_config16(bus, devfn, where, val);
-}
-
-static void ppc_conf1_write_config32(struct bus *pbus, unsigned char bus, int devfn, int where, uint32_t val)
-{
- pci_ppc_write_config32(bus, devfn, where, val);
-}
-
-const struct pci_bus_operations pci_ppc_conf1 =
-{
- .read8 = ppc_conf1_read_config8,
- .read16 = ppc_conf1_read_config16,
- .read32 = ppc_conf1_read_config32,
- .write8 = ppc_conf1_write_config8,
- .write16 = ppc_conf1_write_config16,
- .write32 = ppc_conf1_write_config32,
-};
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include "ppc.h"
-#include "ppcreg.h"
-
-unsigned ppc_getmsr(void)
-{
- unsigned result;
- __asm__ volatile ("mfmsr %0" : "=r" (result));
- return result;
-}
-
-unsigned ppc_gethid0(void)
-{
- unsigned result;
- __asm__ volatile ("mfspr %0,1008" : "=r" (result));
- return result;
-}
-
-unsigned ppc_gethid1(void)
-{
- unsigned result;
- __asm__ volatile ("mfspr %0,1009" : "=r" (result));
- return result;
-}
-
-void ppc_sethid0(unsigned value)
-{
- __asm__ volatile ("mtspr 1008,%0" : : "r" (value));
-}
-
-unsigned ppc_getpvr(void)
-{
- unsigned result;
- __asm__("mfspr %0, 287" : "=r" (result));
- return result;
-}
-
-void ppc_setmsr(unsigned value)
-{
- __asm__ volatile ("mtmsr %0; sync" :: "r" (value));
-}
-
-void ppc_set1015(unsigned value)
-{
- __asm__ volatile ("mtspr 1015,%0" : : "r" (value));
-}
-
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <stdarg.h>
-#include <console/vtxprintf.h>
-#include <console/loglevel.h>
-#include <uart8250.h>
-
-int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
-
-void console_tx_byte(unsigned char byte)
-{
- if (byte == '\n')
- uart8250_tx_byte(CONFIG_TTYS0_BASE, '\r');
-
- uart8250_tx_byte(CONFIG_TTYS0_BASE, byte);
-}
-
-int do_printk(int msg_level, const char *fmt, ...)
-{
- va_list args;
- int i;
-
- if (msg_level >= console_loglevel) {
- return 0;
- }
-
- va_start(args, fmt);
- i = vtxprintf(console_tx_byte, fmt, args);
- va_end(args);
-
- return i;
-}
+++ /dev/null
-/*
- * (C) Copyright 2000, 2001
- * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
- * base on code by
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-#include <ppc_asm.tmpl>
-
- .text
-/*
- * unsigned long long _get_ticks(void);
- */
- .globl _get_ticks
-_get_ticks:
-1: mftbu r3
- mftb r4
- mftbu r5
- cmpw 0,r3,r5
- bne 1b
- blr
-
-/*
- * Delay for a number of ticks
- */
- .globl _wait_ticks
-_wait_ticks:
- mflr r8 /* save link register */
- mr r7, r3 /* save tick count */
- bl _get_ticks /* Get start time */
-
- /* Calculate end time */
- addc r7, r4, r7 /* Compute end time lower */
- addze r6, r3 /* and end time upper */
-
-1: bl _get_ticks /* Get current time */
- subfc r4, r4, r7 /* Subtract current time from end time */
- subfe. r3, r3, r6
- bge 1b /* Loop until time expired */
-
- mtlr r8 /* restore link register */
- blr
-
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <ppc.h>
-#include <timer.h>
-#include <clock.h>
-
-unsigned long get_hz(void)
-{
- return get_timer_freq();
-}
-
-unsigned long ticks_since_boot(void)
-{
- extern unsigned long _get_ticks(void);
- return _get_ticks();
-}
-
-void udelay(int usecs)
-{
- extern void _wait_ticks(unsigned long);
- unsigned long ticksperusec = get_hz() / 1000000;
-
- _wait_ticks(ticksperusec * usecs);
-}
+++ /dev/null
-#ifndef CPU_PPC_CPUID_H
-#define CPU_PPC_CPUID_H
-
-void display_cpuid(device_t dev);
-
-#endif /* CPU_PPC_CPUID_H */
projects / coreboot.git / commitdiff