1 /*----------------------------------------------------------------------------+
3 | This source code has been made available to you by IBM on an AS-IS
4 | basis. Anyone receiving this source is licensed under IBM
5 | copyrights to use it in any way he or she deems fit, including
6 | copying it, modifying it, compiling it, and redistributing it either
7 | with or without modifications. No license under IBM patents or
8 | patent applications is to be implied by the copyright license.
10 | Any user of this software should understand that IBM cannot provide
11 | technical support for this software and will not be responsible for
12 | any consequences resulting from the use of this software.
14 | Any person who transfers this source code or any derivative work
15 | must include the IBM copyright notice, this paragraph, and the
16 | preceding two paragraphs in the transferred software.
18 | COPYRIGHT I B M CORPORATION 1999
19 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 +----------------------------------------------------------------------------*/
25 /*--------------------------------------------------------------------- */
26 /* Special Purpose Registers */
27 /*--------------------------------------------------------------------- */
28 #define srr2 0x3de /* save/restore register 2 */
29 #define srr3 0x3df /* save/restore register 3 */
30 #define dbsr 0x3f0 /* debug status register */
31 #define dbcr0 0x3f2 /* debug control register 0 */
32 #define dbcr1 0x3bd /* debug control register 1 */
33 #define iac1 0x3f4 /* instruction address comparator 1 */
34 #define iac2 0x3f5 /* instruction address comparator 2 */
35 #define iac3 0x3b4 /* instruction address comparator 3 */
36 #define iac4 0x3b5 /* instruction address comparator 4 */
37 #define dac1 0x3f6 /* data address comparator 1 */
38 #define dac2 0x3f7 /* data address comparator 2 */
39 #define dccr 0x3fa /* data cache control register */
40 #define iccr 0x3fb /* instruction cache control register */
41 #define esr 0x3d4 /* execption syndrome register */
42 #define dear 0x3d5 /* data exeption address register */
43 #define evpr 0x3d6 /* exeption vector prefix register */
44 #define tsr 0x3d8 /* timer status register */
45 #define tcr 0x3da /* timer control register */
46 #define pit 0x3db /* programmable interval timer */
47 #define sgr 0x3b9 /* storage guarded reg */
48 #define dcwr 0x3ba /* data cache write-thru reg*/
49 #define sler 0x3bb /* storage little-endian reg */
50 #define cdbcr 0x3d7 /* cache debug cntrl reg */
51 #define icdbdr 0x3d3 /* instr cache dbug data reg*/
52 #define ccr0 0x3b3 /* core configuration register */
53 #define dvc1 0x3b6 /* data value compare register 1 */
54 #define dvc2 0x3b7 /* data value compare register 2 */
55 #define pid 0x3b1 /* process ID */
56 #define su0r 0x3bc /* storage user-defined register 0 */
57 #define zpr 0x3b0 /* zone protection regsiter */
59 #define tbl 0x11c /* time base lower - privileged write */
60 #define tbu 0x11d /* time base upper - privileged write */
62 #define sprg4r 0x104 /* Special purpose general 4 - read only */
63 #define sprg5r 0x105 /* Special purpose general 5 - read only */
64 #define sprg6r 0x106 /* Special purpose general 6 - read only */
65 #define sprg7r 0x107 /* Special purpose general 7 - read only */
66 #define sprg4w 0x114 /* Special purpose general 4 - write only */
67 #define sprg5w 0x115 /* Special purpose general 5 - write only */
68 #define sprg6w 0x116 /* Special purpose general 6 - write only */
69 #define sprg7w 0x117 /* Special purpose general 7 - write only */
71 /*----------------------------------------------------------------------------+
72 | Machine State Register. MSR_EE, MSR_PR, MSR_FP, MSR_ME, MSR_FE0, MSR_FE1,
73 +----------------------------------------------------------------------------*/
74 #define MSR_APE 0x00080000 /* wait state enable */
75 #define MSR_WE 0x00040000 /* wait state enable */
76 #define MSR_CE 0x00020000 /* critical interrupt enable */
77 #define MSR_DWE 0x00000400 /* debug wait enable */
78 #define MSR_DE 0x00000200 /* debug interrupt enable */
79 #define MSR_IR 0x00000020 /* instruction relocale */
80 #define MSR_DR 0x00000010 /* data relocale */
82 /******************************************************************************
83 * Special for PPC405GP
84 ******************************************************************************/
86 /******************************************************************************
88 ******************************************************************************/
89 #define DMA_DCR_BASE 0x100
90 #define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */
91 #define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */
92 #define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */
93 #define dmasa0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */
94 #define dmasb0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */
95 #define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */
96 #define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */
97 #define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */
98 #define dmasa1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */
99 #define dmasb1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */
100 #define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */
101 #define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */
102 #define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */
103 #define dmasa2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */
104 #define dmasb2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */
105 #define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */
106 #define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */
107 #define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */
108 #define dmasa3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */
109 #define dmasb3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */
110 #define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */
111 #define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */
112 #define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */
114 /******************************************************************************
115 * Universal interrupt controller
116 ******************************************************************************/
117 #define UIC_DCR_BASE 0xc0
118 #define uicsr (UIC_DCR_BASE+0x0) /* UIC status */
119 #define uicsrs (UIC_DCR_BASE+0x1) /* UIC status set */
120 #define uicer (UIC_DCR_BASE+0x2) /* UIC enable */
121 #define uiccr (UIC_DCR_BASE+0x3) /* UIC critical */
122 #define uicpr (UIC_DCR_BASE+0x4) /* UIC polarity */
123 #define uictr (UIC_DCR_BASE+0x5) /* UIC triggering */
124 #define uicmsr (UIC_DCR_BASE+0x6) /* UIC masked status */
125 #define uicvr (UIC_DCR_BASE+0x7) /* UIC vector */
126 #define uicvcr (UIC_DCR_BASE+0x8) /* UIC vector configuration */
128 /*-----------------------------------------------------------------------------+
129 | Universal interrupt controller interrupts
130 +-----------------------------------------------------------------------------*/
131 #define UIC_UART0 0x80000000 /* UART 0 */
132 #define UIC_UART1 0x40000000 /* UART 1 */
133 #define UIC_IIC 0x20000000 /* IIC */
134 #define UIC_EXT_MAST 0x10000000 /* External Master */
135 #define UIC_PCI 0x08000000 /* PCI write to command reg */
136 #define UIC_DMA0 0x04000000 /* DMA chan. 0 */
137 #define UIC_DMA1 0x02000000 /* DMA chan. 1 */
138 #define UIC_DMA2 0x01000000 /* DMA chan. 2 */
139 #define UIC_DMA3 0x00800000 /* DMA chan. 3 */
140 #define UIC_EMAC_WAKE 0x00400000 /* EMAC wake up */
141 #define UIC_MAL_SERR 0x00200000 /* MAL SERR */
142 #define UIC_MAL_TXEOB 0x00100000 /* MAL TXEOB */
143 #define UIC_MAL_RXEOB 0x00080000 /* MAL RXEOB */
144 #define UIC_MAL_TXDE 0x00040000 /* MAL TXDE */
145 #define UIC_MAL_RXDE 0x00020000 /* MAL RXDE */
146 #define UIC_ENET 0x00010000 /* Ethernet */
147 #define UIC_EXT_PCI_SERR 0x00008000 /* External PCI SERR# */
148 #define UIC_ECC_CE 0x00004000 /* ECC Correctable Error */
149 #define UIC_PCI_PM 0x00002000 /* PCI Power Management */
150 #define UIC_EXT0 0x00000040 /* External interrupt 0 */
151 #define UIC_EXT1 0x00000020 /* External interrupt 1 */
152 #define UIC_EXT2 0x00000010 /* External interrupt 2 */
153 #define UIC_EXT3 0x00000008 /* External interrupt 3 */
154 #define UIC_EXT4 0x00000004 /* External interrupt 4 */
155 #define UIC_EXT5 0x00000002 /* External interrupt 5 */
156 #define UIC_EXT6 0x00000001 /* External interrupt 6 */
158 /******************************************************************************
160 ******************************************************************************/
161 #define SDRAM_DCR_BASE 0x10
162 #define memcfga (SDRAM_DCR_BASE+0x0) /* Memory configuration address reg */
163 #define memcfgd (SDRAM_DCR_BASE+0x1) /* Memory configuration data reg */
164 /* values for memcfga register - indirect addressing of these regs */
166 #define mem_besra 0x00 /* bus error syndrome reg a */
167 #define mem_besrsa 0x04 /* bus error syndrome reg set a */
168 #define mem_besrb 0x08 /* bus error syndrome reg b */
169 #define mem_besrsb 0x0c /* bus error syndrome reg set b */
170 #define mem_bear 0x10 /* bus error address reg */
172 #define mem_mcopt1 0x20 /* memory controller options 1 */
173 #define mem_rtr 0x30 /* refresh timer reg */
174 #define mem_pmit 0x34 /* power management idle timer */
175 #define mem_mb0cf 0x40 /* memory bank 0 configuration */
176 #define mem_mb1cf 0x44 /* memory bank 1 configuration */
177 #define mem_mb2cf 0x48 /* memory bank 2 configuration */
178 #define mem_mb3cf 0x4c /* memory bank 3 configuration */
179 #define mem_sdtr1 0x80 /* timing reg 1 */
181 #define mem_ecccf 0x94 /* ECC configuration */
182 #define mem_eccerr 0x98 /* ECC error status */
185 /******************************************************************************
186 * Decompression Controller
187 ******************************************************************************/
188 #define DECOMP_DCR_BASE 0x14
189 #define kiar (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */
190 #define kidr (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */
191 /* values for kiar register - indirect addressing of these regs */
192 #define kitor0 0x00 /* index table origin register 0 */
193 #define kitor1 0x01 /* index table origin register 1 */
194 #define kitor2 0x02 /* index table origin register 2 */
195 #define kitor3 0x03 /* index table origin register 3 */
196 #define kaddr0 0x04 /* address decode definition regsiter 0 */
197 #define kaddr1 0x05 /* address decode definition regsiter 1 */
198 #define kconf 0x40 /* decompression core config register */
199 #define kid 0x41 /* decompression core ID register */
200 #define kver 0x42 /* decompression core version # reg */
201 #define kpear 0x50 /* bus error addr reg (PLB addr) */
202 #define kbear 0x51 /* bus error addr reg (DCP to EBIU addr)*/
203 #define kesr0 0x52 /* bus error status reg 0 (R/clear) */
204 #define kesr0s 0x53 /* bus error status reg 0 (set) */
205 /* There are 0x400 of the following registers, from krom0 to krom3ff*/
206 /* Only the first one is given here. */
207 #define krom0 0x400 /* SRAM/ROM read/write */
209 /******************************************************************************
211 ******************************************************************************/
212 #define POWERMAN_DCR_BASE 0xb8
213 #define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */
214 #define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */
215 #define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */
217 /******************************************************************************
218 * Extrnal Bus Controller
219 ******************************************************************************/
220 #define EBC_DCR_BASE 0x12
221 #define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */
222 #define ebccfgd (EBC_DCR_BASE+0x1) /* External bus controller data reg */
223 /* values for ebccfga register - indirect addressing of these regs */
224 #define pb0cr 0x00 /* periph bank 0 config reg */
225 #define pb1cr 0x01 /* periph bank 1 config reg */
226 #define pb2cr 0x02 /* periph bank 2 config reg */
227 #define pb3cr 0x03 /* periph bank 3 config reg */
228 #define pb4cr 0x04 /* periph bank 4 config reg */
229 #define pb5cr 0x05 /* periph bank 5 config reg */
230 #define pb6cr 0x06 /* periph bank 6 config reg */
231 #define pb7cr 0x07 /* periph bank 7 config reg */
232 #define pb0ap 0x10 /* periph bank 0 access parameters */
233 #define pb1ap 0x11 /* periph bank 1 access parameters */
234 #define pb2ap 0x12 /* periph bank 2 access parameters */
235 #define pb3ap 0x13 /* periph bank 3 access parameters */
236 #define pb4ap 0x14 /* periph bank 4 access parameters */
237 #define pb5ap 0x15 /* periph bank 5 access parameters */
238 #define pb6ap 0x16 /* periph bank 6 access parameters */
239 #define pb7ap 0x17 /* periph bank 7 access parameters */
240 #define pbear 0x20 /* periph bus error addr reg */
241 #define pbesr0 0x21 /* periph bus error status reg 0 */
242 #define pbesr1 0x22 /* periph bus error status reg 1 */
243 #define epcr 0x23 /* external periph control reg */
245 /******************************************************************************
247 ******************************************************************************/
248 #define CNTRL_DCR_BASE 0x0b0
249 #define CPC0_PLLMR (CNTRL_DCR_BASE+0x0) /* PLL mode register */
250 #define CPC0_CR0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */
251 #define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */
252 #define CPC0_PSR (CNTRL_DCR_BASE+0x4) /* strap register */
254 #define ecr (0xaa) /* edge conditioner register (405gpr) */
256 /* Bit definitions */
257 #define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */
258 #define PLLMR_FWD_DIV_BYPASS 0xE0000000
259 #define PLLMR_FWD_DIV_3 0xA0000000
260 #define PLLMR_FWD_DIV_4 0x80000000
261 #define PLLMR_FWD_DIV_6 0x40000000
263 #define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */
264 #define PLLMR_FB_DIV_1 0x02000000
265 #define PLLMR_FB_DIV_2 0x04000000
266 #define PLLMR_FB_DIV_3 0x06000000
267 #define PLLMR_FB_DIV_4 0x08000000
269 #define PLLMR_TUNING_MASK 0x01F80000
271 #define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */
272 #define PLLMR_CPU_PLB_DIV_1 0x00000000
273 #define PLLMR_CPU_PLB_DIV_2 0x00020000
274 #define PLLMR_CPU_PLB_DIV_3 0x00040000
275 #define PLLMR_CPU_PLB_DIV_4 0x00060000
277 #define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */
278 #define PLLMR_OPB_PLB_DIV_1 0x00000000
279 #define PLLMR_OPB_PLB_DIV_2 0x00008000
280 #define PLLMR_OPB_PLB_DIV_3 0x00010000
281 #define PLLMR_OPB_PLB_DIV_4 0x00018000
283 #define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */
284 #define PLLMR_PCI_PLB_DIV_1 0x00000000
285 #define PLLMR_PCI_PLB_DIV_2 0x00002000
286 #define PLLMR_PCI_PLB_DIV_3 0x00004000
287 #define PLLMR_PCI_PLB_DIV_4 0x00006000
289 #define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */
290 #define PLLMR_EXB_PLB_DIV_2 0x00000000
291 #define PLLMR_EXB_PLB_DIV_3 0x00000800
292 #define PLLMR_EXB_PLB_DIV_4 0x00001000
293 #define PLLMR_EXB_PLB_DIV_5 0x00001800
295 /* definitions for PPC405GPr (new mode strapping) */
296 #define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */
298 #define PSR_PLL_FWD_MASK 0xC0000000
299 #define PSR_PLL_FDBACK_MASK 0x30000000
300 #define PSR_PLL_TUNING_MASK 0x0E000000
301 #define PSR_PLB_CPU_MASK 0x01800000
302 #define PSR_OPB_PLB_MASK 0x00600000
303 #define PSR_PCI_PLB_MASK 0x00180000
304 #define PSR_EB_PLB_MASK 0x00060000
305 #define PSR_ROM_WIDTH_MASK 0x00018000
306 #define PSR_ROM_LOC 0x00004000
307 #define PSR_PCI_ASYNC_EN 0x00001000
308 #define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */
309 #define PSR_PCI_ARBIT_EN 0x00000400
310 #define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */
313 * PLL Voltage Controlled Oscillator (VCO) definitions
314 * Maximum and minimum values (in MHz) for correct PLL operation.
319 /******************************************************************************
320 * Memory Access Layer
321 ******************************************************************************/
322 #define MAL_DCR_BASE 0x180
323 #define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
324 #define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */
325 #define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
326 #define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
327 #define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */
328 #define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
329 #define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
330 #define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
331 #define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */
332 #define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
333 #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
334 #define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
335 #define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */
336 #define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */
337 #define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
338 #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
340 /*-----------------------------------------------------------------------------
341 | IIC Register Offsets
342 '----------------------------------------------------------------------------*/
343 #define IICMDBUF 0x00
344 #define IICSDBUF 0x02
345 #define IICLMADR 0x04
346 #define IICHMADR 0x05
348 #define IICMDCNTL 0x07
350 #define IICEXTSTS 0x09
351 #define IICLSADR 0x0A
352 #define IICHSADR 0x0B
353 #define IICCLKDIV 0x0C
354 #define IICINTRMSK 0x0D
355 #define IICXFRCNT 0x0E
356 #define IICXTCNTLSS 0x0F
357 #define IICDIRECTCNTL 0x10
359 /*-----------------------------------------------------------------------------
360 | UART Register Offsets
361 '----------------------------------------------------------------------------*/
362 #define DATA_REG 0x00
365 #define INT_ENABLE 0x01
366 #define FIFO_CONTROL 0x02
367 #define LINE_CONTROL 0x03
368 #define MODEM_CONTROL 0x04
369 #define LINE_STATUS 0x05
370 #define MODEM_STATUS 0x06
373 /******************************************************************************
375 ******************************************************************************/
376 #define OCM_DCR_BASE 0x018
377 #define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */
378 #define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */
379 #define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */
380 #define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */
382 /******************************************************************************
383 * GPIO macro register defines
384 ******************************************************************************/
385 #define GPIO_BASE 0xEF600700
386 #define GPIO0_OR (GPIO_BASE+0x0)
387 #define GPIO0_TCR (GPIO_BASE+0x4)
388 #define GPIO0_OSRH (GPIO_BASE+0x8)
389 #define GPIO0_OSRL (GPIO_BASE+0xC)
390 #define GPIO0_TSRH (GPIO_BASE+0x10)
391 #define GPIO0_TSRL (GPIO_BASE+0x14)
392 #define GPIO0_ODR (GPIO_BASE+0x18)
393 #define GPIO0_IR (GPIO_BASE+0x1C)
394 #define GPIO0_RR1 (GPIO_BASE+0x20)
395 #define GPIO0_RR2 (GPIO_BASE+0x24)
396 #define GPIO0_ISR1H (GPIO_BASE+0x30)
397 #define GPIO0_ISR1L (GPIO_BASE+0x34)
398 #define GPIO0_ISR2H (GPIO_BASE+0x38)
399 #define GPIO0_ISR2L (GPIO_BASE+0x3C)
403 * Macro for accessing the indirect EBC register
405 #define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
406 #define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd)
408 struct ppc4xx_sys_info
410 unsigned long pllFwdDiv;
411 unsigned long pllFwdDivB;
412 unsigned long pllFbkDiv;
413 unsigned long pllPlbDiv;
414 unsigned long pllPciDiv;
415 unsigned long pllExtBusDiv;
416 unsigned long pllOpbDiv;
417 unsigned long freqVCOMhz; /* in MHz */
418 unsigned long freqProcessor;
419 unsigned long freqPLB;
420 unsigned long freqPCI;
421 unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
422 unsigned long pciClkSync; /* PCI clock is synchronous */
425 #endif /* __PPC4XX_H__ */
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