3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
25 * This file contains all the macros and symbols which define
26 * a PowerPC assembly language environment.
28 #ifndef __PPC_ASM_TMPL__
29 #define __PPC_ASM_TMPL__
31 /***************************************************************************
33 * These definitions simplify the ugly declarations necessary for GOT
36 * Stolen from prepboot/bootldr.h, (C) 1998 Gabriel Paubert, paubert@iram.es
38 * Uses r14 to access the GOT
42 .section ".got2","aw"; \
51 0: .long .LCTOC1-1f ; \
57 #define GOT_ENTRY(NAME) .L_ ## NAME = . - .LCTOC1 ; .long NAME
59 #define GOT(NAME) .L_ ## NAME (r14)
62 /***************************************************************************
134 /* Some special registers */
136 #define TBRU 269 /* Time base Upper/Lower (Reading) */
138 #define TBWU 284 /* Time base Upper/Lower (Writing) */
143 #define HID0 1008 /* Hardware Implementation */
144 #define PVR 287 /* Processor Version */
145 #define SDR1 25 /* MMU hash base register */
146 #define DAR 19 /* Data Address Register */
147 #define SPR0 272 /* Supervisor Private Registers */
156 #define SRR0 26 /* Saved Registers (exception) */
158 #define DEC 22 /* Decrementer */
159 #define EAR 282 /* External Address Register */
160 #define ICR 148 /* Interrupt Cause Register (37-44) */
162 #define COUNTA 150 /* Breakpoint Counter (37-44) */
163 #define COUNTB 151 /* Breakpoint Counter (37-44) */
164 #define LCTRL1 156 /* Load/Store Support (37-40) */
165 #define LCTRL2 157 /* Load/Store Support (37-41) */
168 /* Registers in the processor's internal memory map that we use.
170 #define IMMR 0xff000000
172 #define SYPCR 0x00000004
173 #define BR0 0x00000100
174 #define OR0 0x00000104
175 #define BR1 0x00000108
176 #define OR1 0x0000010c
177 #define BR2 0x00000110
178 #define OR2 0x00000114
179 #define BR3 0x00000118
180 #define OR3 0x0000011c
181 #define BR4 0x00000120
182 #define OR4 0x00000124
184 #define MAR 0x00000164
185 #define MCR 0x00000168
186 #define MAMR 0x00000170
187 #define MBMR 0x00000174
188 #define MSTAT 0x00000178
189 #define MPTPR 0x0000017a
190 #define MDR 0x0000017c
192 #define TBSCR 0x00000200
193 #define TBREFF0 0x00000204
195 #define PLPRCR 0x00000284
204 * Macros for storing registers into and loading registers from
207 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
208 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
209 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
210 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
211 #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
212 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
213 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
214 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
215 #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
216 #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
219 * GCC sometimes accesses words at negative offsets from the stack
220 * pointer, although the SysV ABI says it shouldn't. To cope with
221 * this, we leave this much untouched space on the stack on exception
224 #define STACK_UNDERHEAD 64
226 #if 0 /* we don't use virtual addresses in PPCBOOT */
227 #define tophys(rd,rs,rt) addis rd,rs,-KERNELBASE@h
228 #define tovirt(rd,rs,rt) addis rd,rs,KERNELBASE@h
230 #define tophys(rd,rs,rt) mr rd,rs
231 #define tovirt(rd,rs,rt) mr rd,rs
235 * Exception entry code. This code runs with address translation
236 * turned off, i.e. using physical addresses.
237 * We assume sprg3 has the physical address of the current
238 * task's thread_struct.
240 #define EXCEPTION_PROLOG \
244 tophys(r21,r1,r21); /* use tophys(kernel sp) otherwise */ \
245 subi r21,r21,INT_FRAME_SIZE+STACK_UNDERHEAD; /* alloc exc. frame */\
246 1: stw r20,_CCR(r21); /* save registers */ \
247 stw r22,GPR22(r21); \
248 stw r23,GPR23(r21); \
250 stw r20,GPR20(r21); \
252 stw r22,GPR21(r21); \
254 stw r20,_LINK(r21); \
265 tovirt(r1,r21,r1); /* set new kernel sp */ \
268 * Note: code which follows this uses cr0.eq (set if from kernel),
269 * r21, r22 (SRR0), and r23 (SRR1).
275 * The data words for `hdlr' and `int_return' are initialized with
276 * OFFSET values only; they must be relocated first before they can
279 #define STD_EXCEPTION(n, label, hdlr) \
283 lwz r3,GOT(transfer_to_handler); \
285 addi r3,r1,STACK_FRAME_OVERHEAD; \
289 .long hdlr - _start + EXC_OFF_SYS_RESET; \
290 .long int_return - _start + EXC_OFF_SYS_RESET
293 #endif /* __PPC_ASM_TMPL__ */