Add TINY_BOOTBLOCK support for the SiS966 southbridge.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6184 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index 50c52b67c5525714f5b9f88ddaf5979082fce810..da6eb7701e2d50f59c0a0d54e98713dd101083fe 100644 (file)
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -40,7 +40,6 @@
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/sis/sis966/sis966.h"
 #include "southbridge/sis/sis966/early_smbus.c"
-#include "southbridge/sis/sis966/enable_rom.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -131,7 +130,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                /* Allow the HT devices to be found */
                enumerate_ht_chain();
                sio_setup();
-               sis966_enable_rom();
         }
 
         if (bist == 0)

diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig
index bbb5ee971b394f43e4ddf5b804d469b5e4df56d3..867d08c347337d2221ef7964d69eaf8fb8df6288 100644 (file)
--- a/src/southbridge/sis/sis966/Kconfig
+++ b/src/southbridge/sis/sis966/Kconfig
@@ -2,6 +2,11 @@ config SOUTHBRIDGE_SIS_SIS966
        bool
        select IOAPIC
        select HAVE_USBDEBUG
+       select TINY_BOOTBLOCK
+
+config BOOTBLOCK_SOUTHBRIDGE_INIT
+       string
+       default "southbridge/sis/sis966/bootblock.c" if SOUTHBRIDGE_SIS_SIS966
 
 config ID_SECTION_OFFSET
        hex

diff --git a/src/southbridge/sis/sis966/bootblock.c b/src/southbridge/sis/sis966/bootblock.c
new file mode 100644 (file)
index 0000000..1ff3cda
--- /dev/null
+++ b/src/southbridge/sis/sis966/bootblock.c
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Tyan Computer
+ * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
+ * Copyright (C) 2006,2007 AMD
+ * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
+ * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
+ * Written by Morgan Tsai <my_tsai@sis.com> for SiS.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_ids.h>
+#include "sis966.h"
+
+static void sis966_enable_rom(void)
+{
+       device_t addr;
+
+       /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */
+       addr = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS,
+                                       PCI_DEVICE_ID_SIS_SIS966_LPC), 0);
+
+       /* Set the 4MB enable bit(s). */
+       pci_write_config8(addr, 0x40, pci_read_config8(addr, 0x40) | 0x11);
+}
+
+static void bootblock_southbridge_init(void)
+{
+       sis966_enable_rom();
+}

diff --git a/src/southbridge/sis/sis966/enable_rom.c b/src/southbridge/sis/sis966/enable_rom.c
deleted file mode 100644 (file)
index 63ef616..0000000
--- a/src/southbridge/sis/sis966/enable_rom.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Tyan Computer
- * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
- * Copyright (C) 2006,2007 AMD
- * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
- * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
- * Written by Morgan Tsai <my_tsai@sis.com> for SiS.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
-       #define SIS966_DEVN_BASE        CONFIG_HT_CHAIN_END_UNITID_BASE
-#else
-       #define SIS966_DEVN_BASE        CONFIG_HT_CHAIN_UNITID_BASE
-#endif
-
-static void sis966_enable_rom(void)
-{
-       device_t addr;
-
-       /* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */
-       addr = pci_locate_device(PCI_ID(0x1039, 0x0966), 0);
-
-       /* Set the 4MB enable bit bit */
-       pci_write_config8(addr, 0x40, pci_read_config8(addr, 0x40) | 0x11);
-}

diff --git a/src/southbridge/sis/sis966/enable_usbdebug.c b/src/southbridge/sis/sis966/enable_usbdebug.c
index a82e941b3a3fbe13e936d891514eb321cbf7ef6f..fb20c960f392e03c6565ee32ba39cceb21e3358d 100644 (file)
--- a/src/southbridge/sis/sis966/enable_usbdebug.c
+++ b/src/southbridge/sis/sis966/enable_usbdebug.c
@@ -30,12 +30,6 @@
 #include <device/pci_def.h>
 #include "sis966.h"
 
-#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
-#define SIS966_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
-#else
-#define SIS966_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
-#endif
-
 void set_debug_port(unsigned int port)
 {
        u32 dword;

diff --git a/src/southbridge/sis/sis966/ide.c b/src/southbridge/sis/sis966/ide.c
index c57be5ade7426052c9e04d3b333cb1e03cc23147..90ea002a5a4cd29c19ae75ab31653bf4cd00e389 100644 (file)
--- a/src/southbridge/sis/sis966/ide.c
+++ b/src/southbridge/sis/sis966/ide.c
@@ -30,6 +30,7 @@
 #include <device/pci_ops.h>
 #include <arch/io.h>
 #include "sis966.h"
+#include "chip.h"
 
 uint8_t        SiS_SiS5513_init[49][3]={
 {0x04, 0xFF, 0x05},

diff --git a/src/southbridge/sis/sis966/sis966.h b/src/southbridge/sis/sis966/sis966.h
index 324beef3c9e0f51dc5b06de1c4c1a3697decae76..a451bf7e55629918fb1abfb40fce675aadbd8f75 100644 (file)
--- a/src/southbridge/sis/sis966/sis966.h
+++ b/src/southbridge/sis/sis966/sis966.h
@@ -22,6 +22,12 @@
 #ifndef SIS966_H
 #define SIS966_H
 
+#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
+#define SIS966_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
+#else
+#define SIS966_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
+#endif
+
 #define DEBUG_AZA 0
 #define DEBUG_NIC 0
 #define DEBUG_IDE 0
@@ -29,9 +35,12 @@
 #define DEBUG_USB 0
 #define DEBUG_USB2 0
 
-#include "chip.h"
-
+#if !defined(__ROMCC__)
 void sis966_enable(device_t dev);
+#endif
+
+#if defined(__PRE_RAM__) && !defined(__ROMCC__)
 void sis966_enable_usbdebug(unsigned int port);
+#endif
 
 #endif /* SIS966_H */