src/southbridge/sis/sis966/ide.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2004 Tyan Computer
   5  * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
   6  * Copyright (C) 2006,2007 AMD
   7  * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
   8  * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
   9  * Written by Morgan Tsai <my_tsai@sis.com> for SiS.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  24  */
  25
  26 #include <console/console.h>
  27 #include <device/device.h>
  28 #include <device/pci.h>
  29 #include <device/pci_ids.h>
  30 #include <device/pci_ops.h>
  31 #include <arch/io.h>
  32 #include "sis966.h"
  33 #include "chip.h"
  34
  35 uint8_t SiS_SiS5513_init[49][3]={
  36 {0x04, 0xFF, 0x05},
  37 {0x0D, 0xFF, 0x80},
  38 {0x2C, 0xFF, 0x39},
  39 {0x2D, 0xFF, 0x10},
  40 {0x2E, 0xFF, 0x13},
  41 {0x2F, 0xFF, 0x55},
  42 {0x50, 0xFF, 0xA2},
  43 {0x51, 0xFF, 0x21},
  44 {0x53, 0xFF, 0x21},
  45 {0x54, 0xFF, 0x2A},
  46 {0x55, 0xFF, 0x96},
  47 {0x52, 0xFF, 0xA2},
  48 {0x56, 0xFF, 0x81},
  49 {0x57, 0xFF, 0xC0},
  50 {0x60, 0xFF, 0xFB},
  51 {0x61, 0xFF, 0xAA},
  52 {0x62, 0xFF, 0xFB},
  53 {0x63, 0xFF, 0xAA},
  54 {0x81, 0xFF, 0xB3},
  55 {0x82, 0xFF, 0x72},
  56 {0x83, 0xFF, 0x40},
  57 {0x85, 0xFF, 0xB3},
  58 {0x86, 0xFF, 0x72},
  59 {0x87, 0xFF, 0x40},
  60 {0x94, 0xFF, 0xC0},
  61 {0x95, 0xFF, 0x08},
  62 {0x96, 0xFF, 0xC0},
  63 {0x97, 0xFF, 0x08},
  64 {0x98, 0xFF, 0xCC},
  65 {0x99, 0xFF, 0x04},
  66 {0x9A, 0xFF, 0x0C},
  67 {0x9B, 0xFF, 0x14},
  68 {0xA0, 0xFF, 0x11},
  69 {0x57, 0xFF, 0xD0},
  70
  71 {0xD8, 0xFE, 0x01},    // Com reset
  72 {0xC8, 0xFE, 0x01},
  73 {0xC4, 0xFF, 0xFF},    // Clear status
  74 {0xC5, 0xFF, 0xFF},
  75 {0xC6, 0xFF, 0xFF},
  76 {0xC7, 0xFF, 0xFF},
  77 {0xD4, 0xFF, 0xFF},
  78 {0xD5, 0xFF, 0xFF},
  79 {0xD6, 0xFF, 0xFF},
  80 {0xD7, 0xFF, 0xFF},
  81
  82
  83 {0x2C, 0xFF, 0x39},     // set subsystem ID
  84 {0x2D, 0xFF, 0x10},
  85 {0x2E, 0xFF, 0x13},
  86 {0x2F, 0xFF, 0x55},
  87
  88
  89 {0x00, 0x00, 0x00}                                      //End of table
  90 };
  91
  92 static void ide_init(struct device *dev)
  93 {
  94         struct southbridge_sis_sis966_config *conf;
  95         /* Enable ide devices so the linux ide driver will work */
  96         uint32_t dword;
  97         uint16_t word;
  98         uint8_t byte;
  99         conf = dev->chip_info;
 100
 101
 102
 103 print_debug("IDE_INIT:---------->\n");
 104
 105
 106 //-------------- enable IDE (SiS5513) -------------------------
 107 {
 108         uint8_t  temp8;
 109         int i=0;
 110         while(SiS_SiS5513_init[i][0] != 0)
 111         {
 112                 temp8 = pci_read_config8(dev, SiS_SiS5513_init[i][0]);
 113                 temp8 &= SiS_SiS5513_init[i][1];
 114                 temp8 |= SiS_SiS5513_init[i][2];
 115                 pci_write_config8(dev, SiS_SiS5513_init[i][0], temp8);
 116                 i++;
 117         };
 118 }
 119 //-----------------------------------------------------------
 120
 121         word = pci_read_config16(dev, 0x50);
 122         /* Ensure prefetch is disabled */
 123         word &= ~((1 << 15) | (1 << 13));
 124         if (conf->ide1_enable) {
 125                 /* Enable secondary ide interface */
 126                 word |= (1<<0);
 127                 printk(BIOS_DEBUG, "IDE1 \t");
 128         }
 129         if (conf->ide0_enable) {
 130                 /* Enable primary ide interface */
 131                 word |= (1<<1);
 132                 printk(BIOS_DEBUG, "IDE0\n");
 133         }
 134
 135         word |= (1<<12);
 136         word |= (1<<14);
 137
 138         pci_write_config16(dev, 0x50, word);
 139
 140
 141         byte = 0x20 ; // Latency: 64-->32
 142         pci_write_config8(dev, 0xd, byte);
 143
 144         dword = pci_read_config32(dev, 0xf8);
 145         dword |= 12;
 146         pci_write_config32(dev, 0xf8, dword);
 147 #if CONFIG_PCI_ROM_RUN == 1
 148         pci_dev_init(dev);
 149 #endif
 150
 151 #if DEBUG_IDE
 152 {
 153         int i;
 154
 155         print_debug("****** IDE PCI config ******");
 156         print_debug("\n    03020100  07060504  0B0A0908  0F0E0D0C");
 157
 158         for(i=0;i<0xff;i+=4){
 159                 if((i%16)==0){
 160                         print_debug("\n");
 161                         print_debug_hex8(i);
 162                         print_debug(": ");
 163                 }
 164                 print_debug_hex32(pci_read_config32(dev,i));
 165                 print_debug("  ");
 166         }
 167         print_debug("\n");
 168 }
 169 #endif
 170 print_debug("IDE_INIT:<----------\n");
 171 }
 172
 173 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 174 {
 175         pci_write_config32(dev, 0x40,
 176                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 177 }
 178 static struct pci_operations lops_pci = {
 179         .set_subsystem  = lpci_set_subsystem,
 180 };
 181
 182 static struct device_operations ide_ops  = {
 183         .read_resources = pci_dev_read_resources,
 184         .set_resources  = pci_dev_set_resources,
 185         .enable_resources       = pci_dev_enable_resources,
 186         .init           = ide_init,
 187         .scan_bus       = 0,
 188 //      .enable         = sis966_enable,
 189         .ops_pci        = &lops_pci,
 190 };
 191
 192 static const struct pci_driver ide_driver __pci_driver = {
 193         .ops    = &ide_ops,
 194         .vendor = PCI_VENDOR_ID_SIS,
 195         .device = PCI_DEVICE_ID_SIS_SIS966_IDE,
 196 };
 197