From: Uwe Hermann Date: Fri, 15 Oct 2010 07:47:51 +0000 (+0000) Subject: Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets. X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=coreboot.git;a=commitdiff_plain;h=af8b2b91b48229d804f1f391e294467cd91adef5 Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets. This CAR implementation hardcodes the Cache-as-RAM base address to: 0xd0000 - CacheSize so the DCACHE_RAM_BASE is never actually used for this implementation and these sockets. Signed-off-by: Uwe Hermann Acked-by: Peter Stuge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5953 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index d10de589e..45c94ac6f 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -21,11 +21,6 @@ config CPU_INTEL_SLOT_1 bool select CACHE_AS_RAM -config DCACHE_RAM_BASE - hex - default 0xc0000 - depends on CPU_INTEL_SLOT_1 - config DCACHE_RAM_SIZE hex default 0x01000 diff --git a/src/cpu/intel/slot_2/Kconfig b/src/cpu/intel/slot_2/Kconfig index 49f3cb1d5..2862431f0 100644 --- a/src/cpu/intel/slot_2/Kconfig +++ b/src/cpu/intel/slot_2/Kconfig @@ -20,11 +20,6 @@ config CPU_INTEL_SLOT_2 bool -config DCACHE_RAM_BASE - hex - default 0xc0000 - depends on CPU_INTEL_SLOT_2 - config DCACHE_RAM_SIZE hex default 0x01000 diff --git a/src/cpu/intel/socket_FC_PGA370/Kconfig b/src/cpu/intel/socket_FC_PGA370/Kconfig index f3987783a..88541a837 100644 --- a/src/cpu/intel/socket_FC_PGA370/Kconfig +++ b/src/cpu/intel/socket_FC_PGA370/Kconfig @@ -26,11 +26,6 @@ config CPU_INTEL_SOCKET_FC_PGA370 select CACHE_AS_RAM select TINY_BOOTBLOCK -config DCACHE_RAM_BASE - hex - default 0xffdf8000 - depends on CPU_INTEL_SOCKET_FC_PGA370 - config DCACHE_RAM_SIZE hex default 0x8000 diff --git a/src/cpu/intel/socket_PGA370/Kconfig b/src/cpu/intel/socket_PGA370/Kconfig index bfabfb847..adfb5f3a7 100644 --- a/src/cpu/intel/socket_PGA370/Kconfig +++ b/src/cpu/intel/socket_PGA370/Kconfig @@ -30,10 +30,6 @@ config SSE2 bool default n -config DCACHE_RAM_BASE - hex - default 0xc0000 - config DCACHE_RAM_SIZE hex default 0x01000