2 * This file is part of the coreboot project.
4 * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
5 * Copyright (C) 2007-2008 coresystems GmbH
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <cpu/x86/stack.h>
22 #include <cpu/x86/mtrr.h>
23 #include <cpu/x86/post_code.h>
25 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
26 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
28 /* Save the BIST result. */
34 /* Send INIT IPI to all excluding ourself. */
35 movl $0x000C4500, %eax
36 movl $0xFEE00300, %esi
39 /* Disable prefetchers */
42 orl $((1 << 9) | (1 << 19)), %eax
43 orl $((1 << 5) | (1 << 7)), %edx
46 /* Zero out all fixed range and variable range MTRRs. */
47 movl $mtrr_table, %esi
48 movl $((mtrr_table_end - mtrr_table) / 2), %edi
59 /* Configure the default memory type to uncacheable. */
60 movl $MTRRdefType_MSR, %ecx
62 andl $(~0x00000cff), %eax
65 /* Set Cache-as-RAM base address. */
66 movl $(MTRRphysBase_MSR(0)), %ecx
67 movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
71 /* Set Cache-as-RAM mask. */
72 movl $(MTRRphysMask_MSR(0)), %ecx
73 movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
74 movl $0x0000000f, %edx
78 movl $MTRRdefType_MSR, %ecx
80 orl $MTRRdefTypeEn, %eax
83 /* Enable L2 cache. */
89 /* Enable cache (CR0.CD = 0, CR0.NW = 0). */
91 andl $(~((1 << 30) | (1 << 29))), %eax
95 /* Clear the cache memory reagion. */
96 movl $CACHE_AS_RAM_BASE, %esi
98 movl $(CACHE_AS_RAM_SIZE / 4), %ecx
99 // movl $0x23322332, %eax
103 /* Enable Cache-as-RAM mode by disabling cache. */
108 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
109 /* Enable cache for our code in Flash because we do XIP here */
110 movl $MTRRphysBase_MSR(1), %ecx
113 * IMPORTANT: The following calculation _must_ be done at runtime. See
114 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
116 movl $copy_and_run, %eax
117 andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
118 orl $MTRR_TYPE_WRBACK, %eax
121 movl $MTRRphysMask_MSR(1), %ecx
122 movl $0x0000000f, %edx
123 movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
125 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
129 andl $(~((1 << 30) | (1 << 29))), %eax
132 /* Set up the stack pointer. */
134 /* Leave some space for the struct ehci_debug_info. */
135 movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax
137 movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax
141 /* Restore the BIST result. */
148 /* Call romstage.c main function. */
163 movl $MTRRdefType_MSR, %ecx
165 andl $(~MTRRdefTypeEn), %eax
174 movl $MTRRphysBase_MSR(0), %ecx
176 movl $MTRRphysMask_MSR(0), %ecx
178 movl $MTRRphysBase_MSR(1), %ecx
180 movl $MTRRphysMask_MSR(1), %ecx
188 andl $~((1 << 30) | (1 << 29)), %eax
200 /* Enable Write Back and Speculative Reads for the first 1MB. */
201 movl $MTRRphysBase_MSR(0), %ecx
202 movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax
205 movl $MTRRphysMask_MSR(0), %ecx
206 movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax
207 movl $0x0000000f, %edx // 36bit address space
212 /* And enable cache again after setting MTRRs. */
214 andl $~((1 << 30) | (1 << 29)), %eax
220 movl $MTRRdefType_MSR, %ecx
222 orl $MTRRdefTypeEn, %eax
227 /* Enable prefetchers */
230 andl $~((1 << 9) | (1 << 19)), %eax
231 andl $~((1 << 5) | (1 << 7)), %edx
234 /* Invalidate the cache again. */
239 /* Clear boot_complete flag. */
242 post_code(POST_PREPARE_RAMSTAGE)
243 cld /* Clear direction flag. */
247 movl $ROMSTAGE_STACK, %esp
253 post_code(POST_DEAD_CODE)
259 .word 0x250, 0x258, 0x259
260 .word 0x268, 0x269, 0x26A
261 .word 0x26B, 0x26C, 0x26D
264 .word 0x200, 0x201, 0x202, 0x203
265 .word 0x204, 0x205, 0x206, 0x207
266 .word 0x208, 0x209, 0x20A, 0x20B
267 .word 0x20C, 0x20D, 0x20E, 0x20F