}
#define PCI_DEV_INVALID (0xffffffffU)
-static device_t pci_io_locate_device(unsigned pci_id, device_t dev)
+static inline device_t pci_io_locate_device(unsigned pci_id, device_t dev)
{
for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) {
unsigned int id;
return PCI_DEV_INVALID;
}
-static device_t pci_locate_device(unsigned pci_id, device_t dev)
+static inline device_t pci_locate_device(unsigned pci_id, device_t dev)
{
for(; dev <= PCI_DEV(255|(((1<<CONFIG_PCI_BUS_SEGN_BITS)-1)<<8), 31, 7); dev += PCI_DEV(0,0,1)) {
unsigned int id;
return PCI_DEV_INVALID;
}
-static device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus)
+static inline device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus)
{
device_t dev, last;
$(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/smm.ld $(obj)/ldoptions
$(CC) $(LDFLAGS) -nostdlib -nostartfiles -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o
- $(CONFIG_CROSS_COMPILE)nm -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map
+ $(NM) -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map
$(OBJCOPY) -O binary $(obj)/cpu/x86/smm/smm.elf $(obj)/cpu/x86/smm/smm
$(obj)/cpu/x86/smm/smm_bin.c: $(obj)/cpu/x86/smm/smm
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
-void southbridge_smi_set_eos(void);
-
typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore;
/* SMI multiprocessing semaphore */
uart_tx_byte(byte);
}
-void uart_init(void)
+#if CONFIG_DEBUG_SMI
+static void uart_init(void)
{
/* disable interrupts */
outb(0x0, CONFIG_TTYS0_BASE + UART_IER);
outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM);
outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
}
+#endif
void console_init(void)
{
/* SMI handler function prototypes */
+void smi_handler(u32 smm_revision);
+
void io_trap_handler(int smif);
int southbridge_io_trap_handler(int smif);
int mainboard_io_trap_handler(int smif);
+void southbridge_smi_set_eos(void);
+
void __attribute__((weak)) cpu_smi_handler(unsigned int node, smm_state_save_area_t *state_save);
void __attribute__((weak)) northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save);
void __attribute__((weak)) southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save);
};
typedef struct tsc_struct tsc_t;
-static tsc_t rdtsc(void)
+static inline tsc_t rdtsc(void)
{
tsc_t res;
__asm__ __volatile__ (
#include <device/device.h>
#include <console/console.h>
#include <boot/tables.h>
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
#include <x86emu/x86emu.h>
+#endif
#include <pc80/mc146818rtc.h>
#include <arch/io.h>
#include <arch/coreboot_tables.h>
#include <arch/io.h>
#include <arch/romcc_io.h>
#include <console/console.h>
+#include <cpu/x86/smm.h>
#include "../../../southbridge/intel/i82801gx/i82801gx_nvs.h"
/* The southbridge SMI handler checks whether gnvs has a
#undef IOTRAP
}
-typedef void (*smi_handler)(unsigned int node,
+typedef void (*smi_handler_t)(unsigned int node,
smm_state_save_area_t *state_save);
-smi_handler southbridge_smi[32] = {
+smi_handler_t southbridge_smi[32] = {
NULL, // [0] reserved
NULL, // [1] reserved
NULL, // [2] BIOS_STS
#undef IOTRAP
}
-typedef void (*smi_handler)(unsigned int node,
+typedef void (*smi_handler_t)(unsigned int node,
smm_state_save_area_t *state_save);
-smi_handler southbridge_smi[32] = {
+smi_handler_t southbridge_smi[32] = {
NULL, // [0] reserved
NULL, // [1] reserved
NULL, // [2] BIOS_STS