2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <device/device.h>
22 #include <console/console.h>
23 #include <boot/tables.h>
24 #include <x86emu/x86emu.h>
25 #include <pc80/mc146818rtc.h>
27 #include <arch/coreboot_tables.h>
30 int add_mainboard_resources(struct lb_memory *mem)
32 return add_northbridge_resources(mem);
35 #if CONFIG_PCI_OPTION_ROM_RUN_YABEL
36 static int int15_handler(void)
38 #define BOOT_DISPLAY_DEFAULT 0
39 #define BOOT_DISPLAY_CRT (1 << 0)
40 #define BOOT_DISPLAY_TV (1 << 1)
41 #define BOOT_DISPLAY_EFP (1 << 2)
42 #define BOOT_DISPLAY_LCD (1 << 3)
43 #define BOOT_DISPLAY_CRT2 (1 << 4)
44 #define BOOT_DISPLAY_TV2 (1 << 5)
45 #define BOOT_DISPLAY_EFP2 (1 << 6)
46 #define BOOT_DISPLAY_LCD2 (1 << 7)
48 printk_debug("%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
49 __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
52 case 0x5f35: /* Boot Display */
53 M.x86.R_AX = 0x005f; // Success
54 M.x86.R_CL = BOOT_DISPLAY_DEFAULT;
56 case 0x5f40: /* Boot Panel Type */
57 // M.x86.R_AX = 0x015f; // Supported but failed
58 M.x86.R_AX = 0x005f; // Success
59 M.x86.R_CL = 3; // Display ID
62 /* Interrupt was not handled */
66 /* Interrupt handled */
70 static void int15_install(void)
72 typedef int (* yabel_handleIntFunc)(void);
73 extern yabel_handleIntFunc yabel_intFuncArray[256];
74 yabel_intFuncArray[0x15] = int15_handler;
78 /* Hardware Monitor */
80 static u16 hwm_base = 0xa00;
82 static void hwm_write(u8 reg, u8 value)
84 outb(reg, hwm_base + 0x05);
85 outb(value, hwm_base + 0x06);
88 static void hwm_bank(u8 bank)
90 hwm_write(0x4e, bank);
93 #define FAN_CRUISE_CONTROL_DISABLED 0
94 #define FAN_CRUISE_CONTROL_SPEED 1
95 #define FAN_CRUISE_CONTROL_THERMAL 2
97 #define FAN_SPEED_5625 0
98 //#define FAN_TEMPERATURE_30DEGC 0
105 // FANIN Target Speed Register
106 // FANIN = 337500 / RPM
107 struct fan_speed fan_speeds[] = {
108 { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 },
109 { 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 },
110 { 0x80, 2636 }, { 0x8d, 2393 }, { 0x9b, 2177 }, { 0xaa, 1985 },
111 { 0xba, 1814 }, { 0xcb, 1662 }, { 0xdd, 1527 }, { 0xf0, 1406 }
119 struct temperature temperatures[] = {
120 { 30, 86 }, { 33, 91 }, { 36, 96 }, { 39, 102 },
121 { 42, 107 }, { 45, 113 }, { 48, 118 }, { 51, 123 },
122 { 54, 129 }, { 57, 134 }, { 60, 140 }, { 63, 145 },
123 { 66, 150 }, { 69, 156 }, { 72, 161 }, { 75, 167 }
126 static void hwm_setup(void)
128 int cpufan_control = 0, sysfan_control = 0;
129 int cpufan_speed = 0, sysfan_speed = 0;
130 int cpufan_temperature = 0, sysfan_temperature = 0;
132 if (get_option(&cpufan_control, "cpufan_cruise_control") < 0)
133 cpufan_control = FAN_CRUISE_CONTROL_DISABLED;
134 if (get_option(&cpufan_speed, "cpufan_speed") < 0)
135 cpufan_speed = FAN_SPEED_5625;
136 //if (get_option(&cpufan_temperature, "cpufan_temperature") < 0)
137 // cpufan_temperature = FAN_TEMPERATURE_30DEGC;
139 if (get_option(&sysfan_control, "sysfan_cruise_control") < 0)
140 sysfan_control = FAN_CRUISE_CONTROL_DISABLED;
141 if (get_option(&sysfan_speed, "sysfan_speed") < 0)
142 sysfan_speed = FAN_SPEED_5625;
143 //if (get_option(&sysfan_temperature, "sysfan_temperature") < 0)
144 // sysfan_temperature = FAN_TEMPERATURE_30DEGC;
146 // hwm_write(0x31, 0x20); // AVCC high limit
147 // hwm_write(0x34, 0x06); // VIN2 low limit
150 hwm_write(0x59, 0x20); // Diode Selection
151 hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor
154 hwm_write(0x54, 0xf1); // SYSTIN temperature offset
155 hwm_write(0x55, 0x19); // CPUTIN temperature offset
156 hwm_write(0x56, 0xfc); // AUXTIN temperature offset
158 hwm_bank(0x80); // Default
161 // 00 FANOUT is Manual Mode
162 // 01 FANOUT is Thermal Cruise Mode
163 // 10 FANOUT is Fan Speed Cruise Mode
164 switch (cpufan_control) {
165 case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 4); break;
166 case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break;
168 switch (sysfan_control) {
169 case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 2); break;
170 case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break;
172 // This register must be written first
173 hwm_write(0x04, fan_config);
175 switch (cpufan_control) {
176 case FAN_CRUISE_CONTROL_SPEED:
177 printk_debug("Fan Cruise Control setting CPU fan to %d RPM\n",
178 fan_speeds[cpufan_speed].fan_speed);
179 hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed
181 case FAN_CRUISE_CONTROL_THERMAL:
182 printk_debug("Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n",
183 temperatures[cpufan_temperature].deg_celsius,
184 temperatures[cpufan_temperature].deg_fahrenheit);
185 hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature
189 switch (sysfan_control) {
190 case FAN_CRUISE_CONTROL_SPEED:
191 printk_debug("Fan Cruise Control setting system fan to %d RPM\n",
192 fan_speeds[sysfan_speed].fan_speed);
193 hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed
195 case FAN_CRUISE_CONTROL_THERMAL:
196 printk_debug("Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n",
197 temperatures[sysfan_temperature].deg_celsius,
198 temperatures[sysfan_temperature].deg_fahrenheit);
199 hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature
203 hwm_write(0x0e, 0x02); // Fan Output Step Down Time
204 hwm_write(0x0f, 0x02); // Fan Output Step Up Time
206 hwm_write(0x47, 0xaf); // FAN divisor register
207 hwm_write(0x4b, 0x84); // AUXFANIN speed divisor
209 hwm_write(0x40, 0x01); // Init, but no SMI#
214 extern u32 * cim_verb_data;
215 extern u32 cim_verb_data_size;
217 static void verb_setup(void)
219 // Default VERB is fine on this mainboard.
220 cim_verb_data = NULL;
221 cim_verb_data_size = 0;
224 // mainboard_enable is executed as first thing after
225 // enumerate_buses().
227 static void mainboard_enable(device_t dev)
229 #if CONFIG_PCI_OPTION_ROM_RUN_YABEL
230 /* Install custom int15 handler for VGA OPROM */
237 struct chip_operations mainboard_ops = {
238 CHIP_NAME("Kontron 986LCD-M Mainboard")
239 .enable_dev = mainboard_enable,