1 #ifndef ARCH_ROMCC_IO_H
2 #define ARCH_ROMCC_IO_H 1
7 static inline __attribute__((always_inline)) uint8_t read8(unsigned long addr)
9 return *((volatile uint8_t *)(addr));
12 static inline __attribute__((always_inline)) uint16_t read16(unsigned long addr)
14 return *((volatile uint16_t *)(addr));
17 static inline __attribute__((always_inline)) uint32_t read32(unsigned long addr)
19 return *((volatile uint32_t *)(addr));
22 static inline __attribute__((always_inline)) void write8(unsigned long addr, uint8_t value)
24 *((volatile uint8_t *)(addr)) = value;
27 static inline __attribute__((always_inline)) void write16(unsigned long addr, uint16_t value)
29 *((volatile uint16_t *)(addr)) = value;
32 static inline __attribute__((always_inline)) void write32(unsigned long addr, uint32_t value)
34 *((volatile uint32_t *)(addr)) = value;
38 #if CONFIG_MMCONF_SUPPORT
40 #include <arch/mmio_conf.h>
44 static inline int log2(int value)
52 : "=r" (r) : "r" (value));
56 static inline int log2f(int value)
64 : "=r" (r) : "r" (value));
69 #define PCI_ADDR(SEGBUS, DEV, FN, WHERE) ( \
70 (((SEGBUS) & 0xFFF) << 20) | \
71 (((DEV) & 0x1F) << 15) | \
72 (((FN) & 0x07) << 12) | \
75 #define PCI_DEV(SEGBUS, DEV, FN) ( \
76 (((SEGBUS) & 0xFFF) << 20) | \
77 (((DEV) & 0x1F) << 15) | \
78 (((FN) & 0x07) << 12))
80 #define PCI_ID(VENDOR_ID, DEVICE_ID) \
81 ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
84 #define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC))
86 typedef unsigned device_t; /* pci and pci_mmio need to have different ways to have dev */
88 /* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G,
89 * We don't need to set %fs, and %gs anymore
90 * Before that We need to use %gs, and leave %fs to other RAM access
93 static inline __attribute__((always_inline)) uint8_t pci_io_read_config8(device_t dev, unsigned where)
96 #if CONFIG_PCI_IO_CFG_EXT == 0
97 addr = (dev>>4) | where;
99 addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); //seg == 0
101 outl(0x80000000 | (addr & ~3), 0xCF8);
102 return inb(0xCFC + (addr & 3));
105 #if CONFIG_MMCONF_SUPPORT
106 static inline __attribute__((always_inline)) uint8_t pci_mmio_read_config8(device_t dev, unsigned where)
109 addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
113 static inline __attribute__((always_inline)) uint8_t pci_read_config8(device_t dev, unsigned where)
115 #if CONFIG_MMCONF_SUPPORT_DEFAULT
116 return pci_mmio_read_config8(dev, where);
118 return pci_io_read_config8(dev, where);
122 static inline __attribute__((always_inline)) uint16_t pci_io_read_config16(device_t dev, unsigned where)
125 #if CONFIG_PCI_IO_CFG_EXT == 0
126 addr = (dev>>4) | where;
128 addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
130 outl(0x80000000 | (addr & ~3), 0xCF8);
131 return inw(0xCFC + (addr & 2));
134 #if CONFIG_MMCONF_SUPPORT
135 static inline __attribute__((always_inline)) uint16_t pci_mmio_read_config16(device_t dev, unsigned where)
138 addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
139 return read16x(addr);
143 static inline __attribute__((always_inline)) uint16_t pci_read_config16(device_t dev, unsigned where)
145 #if CONFIG_MMCONF_SUPPORT_DEFAULT
146 return pci_mmio_read_config16(dev, where);
148 return pci_io_read_config16(dev, where);
153 static inline __attribute__((always_inline)) uint32_t pci_io_read_config32(device_t dev, unsigned where)
156 #if CONFIG_PCI_IO_CFG_EXT == 0
157 addr = (dev>>4) | where;
159 addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
161 outl(0x80000000 | (addr & ~3), 0xCF8);
165 #if CONFIG_MMCONF_SUPPORT
166 static inline __attribute__((always_inline)) uint32_t pci_mmio_read_config32(device_t dev, unsigned where)
169 addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
170 return read32x(addr);
174 static inline __attribute__((always_inline)) uint32_t pci_read_config32(device_t dev, unsigned where)
176 #if CONFIG_MMCONF_SUPPORT_DEFAULT
177 return pci_mmio_read_config32(dev, where);
179 return pci_io_read_config32(dev, where);
183 static inline __attribute__((always_inline)) void pci_io_write_config8(device_t dev, unsigned where, uint8_t value)
186 #if CONFIG_PCI_IO_CFG_EXT == 0
187 addr = (dev>>4) | where;
189 addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
191 outl(0x80000000 | (addr & ~3), 0xCF8);
192 outb(value, 0xCFC + (addr & 3));
195 #if CONFIG_MMCONF_SUPPORT
196 static inline __attribute__((always_inline)) void pci_mmio_write_config8(device_t dev, unsigned where, uint8_t value)
199 addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
200 write8x(addr, value);
204 static inline __attribute__((always_inline)) void pci_write_config8(device_t dev, unsigned where, uint8_t value)
206 #if CONFIG_MMCONF_SUPPORT_DEFAULT
207 pci_mmio_write_config8(dev, where, value);
209 pci_io_write_config8(dev, where, value);
214 static inline __attribute__((always_inline)) void pci_io_write_config16(device_t dev, unsigned where, uint16_t value)
217 #if CONFIG_PCI_IO_CFG_EXT == 0
218 addr = (dev>>4) | where;
220 addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
222 outl(0x80000000 | (addr & ~3), 0xCF8);
223 outw(value, 0xCFC + (addr & 2));
226 #if CONFIG_MMCONF_SUPPORT
227 static inline __attribute__((always_inline)) void pci_mmio_write_config16(device_t dev, unsigned where, uint16_t value)
230 addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
231 write16x(addr, value);
235 static inline __attribute__((always_inline)) void pci_write_config16(device_t dev, unsigned where, uint16_t value)
237 #if CONFIG_MMCONF_SUPPORT_DEFAULT
238 pci_mmio_write_config16(dev, where, value);
240 pci_io_write_config16(dev, where, value);
245 static inline __attribute__((always_inline)) void pci_io_write_config32(device_t dev, unsigned where, uint32_t value)
248 #if CONFIG_PCI_IO_CFG_EXT == 0
249 addr = (dev>>4) | where;
251 addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
253 outl(0x80000000 | (addr & ~3), 0xCF8);
257 #if CONFIG_MMCONF_SUPPORT
258 static inline __attribute__((always_inline)) void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t value)
261 addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
262 write32x(addr, value);
266 static inline __attribute__((always_inline)) void pci_write_config32(device_t dev, unsigned where, uint32_t value)
268 #if CONFIG_MMCONF_SUPPORT_DEFAULT
269 pci_mmio_write_config32(dev, where, value);
271 pci_io_write_config32(dev, where, value);
275 #define PCI_DEV_INVALID (0xffffffffU)
276 static inline device_t pci_io_locate_device(unsigned pci_id, device_t dev)
278 for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) {
280 id = pci_io_read_config32(dev, 0);
285 return PCI_DEV_INVALID;
288 static inline device_t pci_locate_device(unsigned pci_id, device_t dev)
290 for(; dev <= PCI_DEV(255|(((1<<CONFIG_PCI_BUS_SEGN_BITS)-1)<<8), 31, 7); dev += PCI_DEV(0,0,1)) {
292 id = pci_read_config32(dev, 0);
297 return PCI_DEV_INVALID;
300 static inline device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus)
304 dev = PCI_DEV(bus, 0, 0);
305 last = PCI_DEV(bus, 31, 7);
307 for(; dev <=last; dev += PCI_DEV(0,0,1)) {
309 id = pci_read_config32(dev, 0);
314 return PCI_DEV_INVALID;
317 /* Generic functions for pnp devices */
318 static inline __attribute__((always_inline)) void pnp_write_config(device_t dev, uint8_t reg, uint8_t value)
320 unsigned port = dev >> 8;
322 outb(value, port +1);
325 static inline __attribute__((always_inline)) uint8_t pnp_read_config(device_t dev, uint8_t reg)
327 unsigned port = dev >> 8;
332 static inline __attribute__((always_inline)) void pnp_set_logical_device(device_t dev)
334 unsigned device = dev & 0xff;
335 pnp_write_config(dev, 0x07, device);
338 static inline __attribute__((always_inline)) void pnp_set_enable(device_t dev, int enable)
340 pnp_write_config(dev, 0x30, enable?0x1:0x0);
343 static inline __attribute__((always_inline)) int pnp_read_enable(device_t dev)
345 return !!pnp_read_config(dev, 0x30);
348 static inline __attribute__((always_inline)) void pnp_set_iobase(device_t dev, unsigned index, unsigned iobase)
350 pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff);
351 pnp_write_config(dev, index + 1, iobase & 0xff);
354 static inline __attribute__((always_inline)) uint16_t pnp_read_iobase(device_t dev, unsigned index)
356 return ((uint16_t)(pnp_read_config(dev, index)) << 8) | pnp_read_config(dev, index + 1);
359 static inline __attribute__((always_inline)) void pnp_set_irq(device_t dev, unsigned index, unsigned irq)
361 pnp_write_config(dev, index, irq);
364 static inline __attribute__((always_inline)) void pnp_set_drq(device_t dev, unsigned index, unsigned drq)
366 pnp_write_config(dev, index, drq & 0xff);
369 #endif /* ARCH_ROMCC_IO_H */