# Misc options
###############################################
-define CONFIG_CHIP_NAME
- default 0
- export always
- comment "Compile in the chip name"
-end
-
define CONFIG_GDB_STUB
default 0
export used
-uses CONFIG_CHIP_NAME
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
object socket_754.o
dir /cpu/amd/model_fxx
-uses CONFIG_CHIP_NAME
-
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
object socket_939.o
-uses CONFIG_CHIP_NAME
-
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
object socket_940.o
-uses CONFIG_CHIP_NAME
uses K8_REV_F_SUPPORT
uses K8_HT_FREQ_1G_SUPPORT
uses DIMM_SUPPORT
uses CPU_SOCKET_TYPE
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
default K8_REV_F_SUPPORT=1
#Opteron K8 1G HT Support
-uses CONFIG_CHIP_NAME
uses K8_REV_F_SUPPORT
uses K8_HT_FREQ_1G_SUPPORT
uses DIMM_SUPPORT
uses CPU_SOCKET_TYPE
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
default K8_REV_F_SUPPORT=1
#Opteron K8 1G HT Support
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
-uses CONFIG_CHIP_NAME
uses PCI_IO_CFG_EXT
uses MMCONF_SUPPORT
uses HT3_SUPPORT
uses PCI_BUS_SEGN_BITS
uses CAR_FAM10
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
default PCI_IO_CFG_EXT=1
-uses CONFIG_CHIP_NAME
uses K8_REV_F_SUPPORT
uses K8_HT_FREQ_1G_SUPPORT
uses DIMM_SUPPORT
uses CPU_SOCKET_TYPE
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
default K8_REV_F_SUPPORT=1
#Opteron K8 1G HT Support
-uses CONFIG_CHIP_NAME
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
object socket_mPGA604_533Mhz.o
dir /cpu/intel/model_f2x
static void debug_init(device_t dev)
{
-#if CONFIG_CHIP_NAME
device_t parent;
-#endif
+
if (!dev->enabled)
return;
switch(dev->path.pnp.device) {
-#if CONFIG_CHIP_NAME
case 0:
parent = dev->bus->dev;
printk_debug("DEBUG: %s", dev_path(parent));
printk_debug("\n");
}
break;
-#endif
case 1:
print_pci_regs_all();
}
struct chip_operations drivers_pci_onboard_ops = {
-#if CONFIG_CHIP_NAME == 1
CHIP_NAME("Onboard PCI")
-#endif
.enable_dev = onboard_enable,
};
/* Chip operations */
struct chip_operations {
void (*enable_dev)(struct device *dev);
-#if CONFIG_CHIP_NAME == 1
char *name;
-#endif
};
-#if CONFIG_CHIP_NAME == 1
#define CHIP_NAME(X) .name = X,
-#else
-#define CHIP_NAME(X)
-#endif
struct bus;
##
## Include the secondary Configuration files
##
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
#The variables belong to mainboard are defined here.
uses CC
uses HOSTCC
uses OBJCOPY
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
default CONFIG_MAX_PHYSICAL_CPUS=1
default CONFIG_LOGICAL_CPUS=1
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000
#endif
}
-/*
-* CONFIG_CHIP_NAME defined in Option.lb.
-*/
struct chip_operations mainboard_ops = {
CHIP_NAME("AMD DBM690T Mainboard")
.enable_dev = dbm690t_enable,
##
## Include the secondary Configuration files
##
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
#The variables belong to mainboard are defined here.
uses CC
uses HOSTCC
uses OBJCOPY
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
default CONFIG_MAX_PHYSICAL_CPUS=1
default CONFIG_LOGICAL_CPUS=1
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000
#endif
}
-/*
-* CONFIG_CHIP_NAME defined in Option.lb.
-*/
struct chip_operations mainboard_ops = {
CHIP_NAME("AMD Pistachio Mainboard")
.enable_dev = pistachio_enable,
##
## Include the secondary Configuration files
##
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
# sample config for amd/serengeti_cheetah
chip northbridge/amd/amdk8/root_complex
uses CC
uses HOSTCC
uses OBJCOPY
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
default APIC_ID_OFFSET=0x8
default LIFT_BSP_APIC_ID=1
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
#2G
#default HW_MEM_HOLE_SIZEK=0x200000
#include <device/device.h>
#include "chip.h"
-#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("AMD Serengeti Cheetah Mainboard")
};
-#endif
##
## Include the secondary Configuration files
##
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
dir /southbridge/amd/amd8151
uses CC
uses HOSTCC
uses OBJCOPY
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
default APIC_ID_OFFSET=0x00
default LIFT_BSP_APIC_ID=1
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
#2G
#default HW_MEM_HOLE_SIZEK=0x200000
#include <device/pci_ops.h>
#include "chip.h"
-#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("AMD family 10 Cheetah mainboard")
};
-#endif
mainboardinit ./auto.inc
end
end
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
chip northbridge/amd/amdk8/root_complex # Root complex
device apic_cluster 0 on # APIC cluster
uses CONFIG_CONSOLE_BTEXT
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
#include <device/device.h>
#include "chip.h"
-#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("ASUS A8N-E Mainboard")
};
-#endif
end
end
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
chip northbridge/amd/amdk8/root_complex # Root complex
device apic_cluster 0 on # APIC cluster
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
# bx_b001- uses K8_HW_MEM_HOLE_SIZEK
default CONFIG_MAX_PHYSICAL_CPUS = 1
default CONFIG_LOGICAL_CPUS = 1
default HAVE_ACPI_TABLES = 1
-# default CONFIG_CHIP_NAME = 1
# 1G memory hole
# bx_b001- default K8_HW_MEM_HOLE_SIZEK = 0x100000
#include <device/pci_ids.h>
#include "chip.h"
-#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("ASUS A8V-E SE Mainboard")
};
-#endif
end
end
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
chip northbridge/amd/amdk8/root_complex # Root complex
device apic_cluster 0 on # APIC cluster
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
# bx_b001- uses K8_HW_MEM_HOLE_SIZEK
default HAVE_HIGH_TABLES = 1
default HAVE_LOW_TABLES = 0
-# default CONFIG_CHIP_NAME = 1
-
# 1G memory hole
# bx_b001- default K8_HW_MEM_HOLE_SIZEK = 0x100000
return 0;
}
-#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("ASUS M2V-MX SE Mainboard")
};
-#endif
uses CONFIG_PCI_ROM_RUN
uses CONFIG_CONSOLE_VGA
uses CONFIG_MAX_PCI_BUSES
-uses CONFIG_CHIP_NAME
uses CONFIG_VIDEO_MB
uses CONFIG_IOAPIC
default CONFIG_CONSOLE_SERIAL8250 = 1
default CONFIG_PCI_ROM_RUN = 0
default CONFIG_CONSOLE_VGA = 0
-default CONFIG_CHIP_NAME = 1
default HAVE_FALLBACK_BOOT = 1
default HAVE_MP_TABLE = 0
default CONFIG_UDELAY_TSC = 1
##
## Include the secondary Configuration files
##
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
# sample config for broadcom/blast
chip northbridge/amd/amdk8/root_complex
uses CC
uses HOSTCC
uses OBJCOPY
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000
#include <device/device.h>
#include "chip.h"
-#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("Broadcom Blast Mainboard")
};
-#endif
##
## Include the secondary Configuration files
##
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
uses CC
uses HOSTCC
uses OBJCOPY
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_USBDEBUG_DIRECT
uses CONFIG_PCI_ROM_RUN
default APIC_ID_OFFSET=0x10
default LIFT_BSP_APIC_ID=1
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
#2G
#default HW_MEM_HOLE_SIZEK=0x200000
#include <device/pci_ops.h>
#include "chip.h"
-#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("GIGABYTE GA-2761GXDK Mainboard")
};
-#endif
##
## Include the secondary Configuration files
##
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
uses CC
uses HOSTCC
uses OBJCOPY
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_USBDEBUG_DIRECT
uses CONFIG_PCI_ROM_RUN
default APIC_ID_OFFSET=0x10
default LIFT_BSP_APIC_ID=1
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
#2G
#default HW_MEM_HOLE_SIZEK=0x200000
#include <device/pci_ops.h>
#include "chip.h"
-#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("GIGABYTE GA-M57SLI Mainboard")
};
-#endif
##
dir /pc80
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
# based on sample config for tyan/s2735
chip northbridge/intel/e7501
uses CC
uses HOSTCC
uses OBJCOPY
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses DEBUG
default DEBUG=1
# default CPU_OPT="-g"
-default CONFIG_CHIP_NAME=1
### End Options.lb
#
#include <device/device.h>
#include "chip.h"
-#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("Intel Xeon E7501 DevKit Mainboard")
};
-#endif
##
## Include the secondary Configuration files
##
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
dir /southbridge/amd/amd8132
uses CC
uses HOSTCC
uses OBJCOPY
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
default APIC_ID_OFFSET=0x10
default LIFT_BSP_APIC_ID=1
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
#2G
#default HW_MEM_HOLE_SIZEK=0x200000
#include <device/device.h>
#include "chip.h"
-#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("IWILL DK8-HTX Mainboard")
};
-#endif
-
uses CONFIG_CONSOLE_VGA
uses CONFIG_MAX_PCI_BUSES
uses TTYS0_BAUD
-uses CONFIG_CHIP_NAME
uses CONFIG_VIDEO_MB
uses CONFIG_IOAPIC
default CONFIG_CONSOLE_SERIAL8250 = 1
default CONFIG_PCI_ROM_RUN = 0
default CONFIG_CONSOLE_VGA = 0
-default CONFIG_CHIP_NAME = 1
default HAVE_FALLBACK_BOOT = 1
default HAVE_MP_TABLE = 0
default CONFIG_UDELAY_TSC = 1
uses _ROMBASE
uses STACK_SIZE
uses HEAP_SIZE
-uses CONFIG_CHIP_NAME
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
## Select power on after power fail setting
default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-##
-## chip name
-##
-default CONFIG_CHIP_NAME=1
-
#
# ROMFS
#
##
## Include the secondary configuration files
##
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
chip northbridge/amd/amdk8/root_complex # Root complex
device apic_cluster 0 on # APIC cluster
uses CONFIG_CONSOLE_BTEXT
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
#include <device/device.h>
#include "chip.h"
-#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("MSI MS7135 Mainboard")
};
-#endif
end
end
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
chip northbridge/amd/amdk8/root_complex # Root complex
device apic_cluster 0 on # APIC cluster
uses CC
uses HOSTCC
uses OBJCOPY
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses CONFIG_USBDEBUG_DIRECT
default ENABLE_APIC_EXT_ID = 0
default APIC_ID_OFFSET = 0x10
default LIFT_BSP_APIC_ID = 1
-default CONFIG_CHIP_NAME = 1
# Move the default coreboot CMOS range off of AMD RTC registers.
default LB_CKS_RANGE_START = 49
#include <device/device.h>
#include "chip.h"
-#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("MSI K9N Neo (MS-7260) Mainboard")
};
-#endif
##
## Include the secondary Configuration files
##
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
# sample config for amd/serengeti_cheetah
chip northbridge/amd/amdk8/root_complex
uses CC
uses HOSTCC
uses OBJCOPY
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
default APIC_ID_OFFSET=0x8
default LIFT_BSP_APIC_ID=1
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
#2G
#default HW_MEM_HOLE_SIZEK=0x200000
#include <device/pci_ops.h>
#include "chip.h"
-#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("MSI MS-9185 Mainboard")
};
-#endif
##
## Include the secondary Configuration files
##
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
# sample config for msi/ms9282
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
#bx_b001- uses K8_HW_MEM_HOLE_SIZEK
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1
-#CHIP_NAME ?
-#default CONFIG_CHIP_NAME=1
-
#1G memory hole
#bx_b001- default K8_HW_MEM_HOLE_SIZEK=0x100000
#include <device/pci_ops.h>
#include "chip.h"
-#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("MSI MS-9282 Mainboard")
};
-#endif
uses CC
uses HOSTCC
uses OBJCOPY
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000
##
## Include the secondary Configuration files
##
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
uses CC
uses HOSTCC
uses OBJCOPY
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_USBDEBUG_DIRECT
uses CONFIG_PCI_ROM_RUN
default APIC_ID_OFFSET=0x10
default LIFT_BSP_APIC_ID=1
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
#2G
#default HW_MEM_HOLE_SIZEK=0x200000
#include <device/pci_ops.h>
#include "chip.h"
-#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("NVIDIA l1_2pvv Mainboard")
};
-#endif
##
## Include the secondary Configuration files
##
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
# sample config for tyan/s2895
chip northbridge/amd/amdk8/root_complex
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1
-#CHIP_NAME ?
-#default CONFIG_CHIP_NAME=1
-
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000
#include <device/device.h>
#include "chip.h"
-#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("Sun Ultra 40 Mainboard")
};
-#endif
##
## Include the secondary Configuration files
##
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
uses CC
uses HOSTCC
uses OBJCOPY
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
default APIC_ID_OFFSET=0x10
default LIFT_BSP_APIC_ID=1
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
#2G
#default HW_MEM_HOLE_SIZEK=0x200000
#include <device/pci_ops.h>
#include "chip.h"
-#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("Supermicro H8DME Mainboard")
};
-#endif
##
## Include the secondary Configuration files
##
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
uses CC
uses HOSTCC
uses OBJCOPY
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
default APIC_ID_OFFSET=0x10
default LIFT_BSP_APIC_ID=1
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
#2G
#default HW_MEM_HOLE_SIZEK=0x200000
#include <device/pci_ops.h>
#include "chip.h"
-#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("Supermicro H8DMR Mainboard")
};
-#endif
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_SERIAL8250
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
-default CONFIG_CHIP_NAME = 1
-
-
-
#
# ROMFS
#
##
## Include the secondary Configuration files
##
-if CONFIG_CHIP_NAME
- config chip.h
-end
-
+config chip.h
# sample config for tyan/s2735
chip northbridge/intel/e7501
uses CONFIG_CONSOLE_BTEXT
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
#include <device/device.h>
#include "chip.h"
-#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S2735 Mainboard")
};
-#endif
##
## Include the secondary Configuration files
##
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
# sample config for tyan/s2850
chip northbridge/amd/amdk8/root_complex
uses CC
uses HOSTCC
uses OBJCOPY
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
default CONFIG_MAX_PHYSICAL_CPUS=1
default CONFIG_LOGICAL_CPUS=1
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000
#include <device/device.h>
#include "chip.h"
-#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S2850 Mainboard")
};
-#endif
##
## Include the secondary Configuration files
##
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
# sample config for tyan/s2875
chip northbridge/amd/amdk8/root_complex
uses CC
uses HOSTCC
uses OBJCOPY
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000
#include <device/device.h>
#include "chip.h"
-#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S2875 Mainboard")
};
-#endif
##
## Include the secondary Configuration files
##
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
# sample config for tyan/s2880
chip northbridge/amd/amdk8/root_complex
uses CC
uses HOSTCC
uses OBJCOPY
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=0
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000
#include <device/device.h>
#include "chip.h"
-#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S2880 Mainboard")
};
-#endif
##
## Include the secondary Configuration files
##
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
# sample config for tyan/s2881
chip northbridge/amd/amdk8/root_complex
uses CC
uses HOSTCC
uses OBJCOPY
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
##HT Unit ID offset, default is 1, the typical one
default HT_CHAIN_UNITID_BASE=0x0a
dev->ops = &mainboard_operations;
}
-#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S2881 Mainboard")
.enable_dev = enable_dev,
};
-#endif
##
## Include the secondary Configuration files
##
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
# sample config for tyan/s2882
chip northbridge/amd/amdk8/root_complex
uses CC
uses HOSTCC
uses OBJCOPY
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000
#include <device/device.h>
#include "chip.h"
-#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S2882 Mainboard")
};
-#endif
##
## Include the secondary Configuration files
##
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
# sample config for tyan/s2885
chip northbridge/amd/amdk8/root_complex
uses CC
uses HOSTCC
uses OBJCOPY
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
##HT Unit ID offset, default is 1, the typical one
default HT_CHAIN_UNITID_BASE=0x0a
#include <device/device.h>
#include "chip.h"
-#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S2885 Mainboard")
};
-#endif
##
## Include the secondary Configuration files
##
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
# sample config for tyan/s2891
chip northbridge/amd/amdk8/root_complex
uses CONFIG_CONSOLE_BTEXT
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_VGA_ROM_RUN
uses CONFIG_PCI_ROM_RUN
}
-#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S2891 Mainboard")
};
-#endif
##
## Include the secondary Configuration files
##
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
# sample config for tyan/s2892
chip northbridge/amd/amdk8/root_complex
uses CONFIG_CONSOLE_BTEXT
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_VGA_ROM_RUN
uses CONFIG_PCI_ROM_RUN
}
-#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S2892 Mainboard")
};
-#endif
##
## Include the secondary Configuration files
##
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
# sample config for tyan/s2895
chip northbridge/amd/amdk8/root_complex
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_VGA_ROM_RUN
uses CONFIG_PCI_ROM_RUN
default SERIAL_CPU_INIT=0
-#CHIP_NAME ?
-#default CONFIG_CHIP_NAME=1
-
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000
}
-#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S2895 Mainboard")
};
-#endif
##
## Include the secondary Configuration files
##
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
uses CC
uses HOSTCC
uses OBJCOPY
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_USBDEBUG_DIRECT
uses CONFIG_PCI_ROM_RUN
default APIC_ID_OFFSET=0x10
default LIFT_BSP_APIC_ID=1
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
#2G
#default HW_MEM_HOLE_SIZEK=0x200000
#include <device/pci_ops.h>
#include "chip.h"
-#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S2912 Mainboard")
};
-#endif
##
## Include the secondary Configuration files
##
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
dir /southbridge/nvidia/mcp55
uses CC
uses HOSTCC
uses OBJCOPY
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_USBDEBUG_DIRECT
uses CONFIG_PCI_ROM_RUN
default APIC_ID_OFFSET=0x00
default LIFT_BSP_APIC_ID=1
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
#2G
#default HW_MEM_HOLE_SIZEK=0x200000
#include <device/pci_ops.h>
#include "chip.h"
-#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S2912 Mainboard (Family 10)")
};
-#endif
##
## Include the secondary Configuration files
##
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
# sample config for tyan/s4880
chip northbridge/amd/amdk8/root_complex
uses CC
uses HOSTCC
uses OBJCOPY
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
default CONFIG_MAX_PHYSICAL_CPUS=4
default CONFIG_LOGICAL_CPUS=1
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000
#include <device/device.h>
#include "chip.h"
-#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S4880 Mainboard")
};
-#endif
##
## Include the secondary Configuration files
##
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
# sample config for tyan/s4882
chip northbridge/amd/amdk8/root_complex
uses CC
uses HOSTCC
uses OBJCOPY
-uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
default CONFIG_MAX_PHYSICAL_CPUS=4
default CONFIG_LOGICAL_CPUS=1
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000
#include <device/device.h>
#include "chip.h"
-#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S4882 Mainboard")
};
-#endif
uses CONFIG_CONSOLE_VGA
uses CONFIG_MAX_PCI_BUSES
uses TTYS0_BAUD
-uses CONFIG_CHIP_NAME
uses CONFIG_VIDEO_MB
uses CONFIG_IOAPIC
default CONFIG_CONSOLE_SERIAL8250 = 1
default CONFIG_PCI_ROM_RUN = 0
default CONFIG_CONSOLE_VGA = 0
-default CONFIG_CHIP_NAME = 1
default HAVE_FALLBACK_BOOT = 1
default HAVE_MP_TABLE = 0
default CONFIG_UDELAY_TSC = 1
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
-uses CONFIG_CHIP_NAME
uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
# This defaults to 8 data bits, 1 stop bit, and no parity
default TTYS0_LCS=0x3
-default CONFIG_CHIP_NAME=1
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
-uses CONFIG_CHIP_NAME
uses CONFIG_VIDEO_MB
uses CONFIG_IOAPIC
default CONFIG_CONSOLE_SERIAL8250 = 1
default CONFIG_PCI_ROM_RUN = 0
default CONFIG_CONSOLE_VGA = 0
-default CONFIG_CHIP_NAME = 1
default HAVE_FALLBACK_BOOT = 1
default CONFIG_SMP = 1
default HAVE_MP_TABLE = 1
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
-uses CONFIG_CHIP_NAME
uses AGP_APERTURE_SIZE
uses HAVE_ACPI_TABLES
default AGP_APERTURE_SIZE=0x4000000
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
driver northbridge.o
driver misc_control.o
.device = 0x1200,
};
-#if CONFIG_CHIP_NAME == 1
-
struct chip_operations northbridge_amd_amdfam10_ops = {
CHIP_NAME("AMD FAM10 Northbridge")
.enable_dev = 0,
};
-#endif
-
static void pci_domain_read_resources(device_t dev)
{
struct resource *resource;
-uses CONFIG_CHIP_NAME
uses AGP_APERTURE_SIZE
uses HAVE_ACPI_TABLES
default AGP_APERTURE_SIZE=0x4000000
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
driver northbridge.o
driver misc_control.o
.device = 0x1100,
};
-#if CONFIG_CHIP_NAME == 1
-
struct chip_operations northbridge_amd_amdk8_ops = {
CHIP_NAME("AMD K8 Northbridge")
.enable_dev = 0,
};
-#endif
-
static void pci_domain_read_resources(device_t dev)
{
struct resource *resource;
projects / coreboot.git / commitdiff