5 uses HAVE_FALLBACK_BOOT
9 uses CONFIG_LOGICAL_CPUS
10 uses CONFIG_MAX_PHYSICAL_CPUS
13 uses CONFIG_ROM_PAYLOAD
14 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
15 uses CONFIG_PRECOMPRESSED_PAYLOAD
19 uses LB_CKS_RANGE_START
22 uses MAINBOARD_PART_NUMBER
25 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
26 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
31 uses DEFAULT_CONSOLE_LOGLEVEL
32 uses MAXIMUM_CONSOLE_LOGLEVEL
33 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
34 uses CONFIG_CONSOLE_SERIAL8250
35 uses CONFIG_UDELAY_TSC
36 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
43 uses CONFIG_CONSOLE_VGA
44 uses CONFIG_PCI_ROM_RUN
49 ## The default definitions are used for these
50 uses CONFIG_ROM_PAYLOAD_START
53 ## These are defined in target Config.lb, don't add here
54 uses USE_FALLBACK_IMAGE
58 uses COREBOOT_EXTRA_VERSION
60 ## These are defined in mainboard Config.lb, don't add here
62 uses ROM_SECTION_OFFSET
72 ## ROM_SIZE is the size of boot ROM that this board will use.
74 default ROM_SIZE=2097152
75 default ROM_IMAGE_SIZE = 65536
78 ## Build code for the fallback boot?
80 default HAVE_FALLBACK_BOOT=1
81 default FALLBACK_SIZE=131072
84 ## Delay timer options
86 default CONFIG_UDELAY_TSC=1
87 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
90 ## Build code to export a programmable irq routing table
92 default HAVE_PIRQ_TABLE=1
93 default IRQ_SLOT_COUNT=12
96 ## Build code to export an x86 MP table
97 ## Useful for specifying IRQ routing values
99 default HAVE_MP_TABLE=1
101 ## Build code to export ACPI tables?
102 default HAVE_ACPI_TABLES=1
105 ## Build code to export a CMOS option table?
107 default HAVE_OPTION_TABLE=0
109 ## CMOS checksum definitions (units == bytes)
110 ## These must match the checksum record in cmos.layout
111 default LB_CKS_RANGE_START=128
112 default LB_CKS_RANGE_END=130
113 default LB_CKS_LOC=131
116 ## Build code for SMP support
117 ## Only worry about 2 micro processors
118 ## NOTE: CONFIG_MAX_CPUS is the number of LOGICAL CPUs,
119 ## so if CONFIG_LOGICAL_CPUS is 1, CONFIG_MAX_CPUS should be 4.
122 default CONFIG_MAX_CPUS=2
123 default CONFIG_LOGICAL_CPUS=0
124 default CONFIG_MAX_PHYSICAL_CPUS=2
127 # NOTE: to initialize VGA, need to copy the VGA option ROM from the factory BIOS
129 default CONFIG_CONSOLE_VGA=0
130 default CONFIG_PCI_ROM_RUN=0
133 ## Build code to setup a generic IOAPIC
135 default CONFIG_IOAPIC=1
138 ## Motherboard identification
140 default MAINBOARD_PART_NUMBER="EIDXE7501DEVKIT"
141 default MAINBOARD_VENDOR="Intel"
142 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
143 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2480
146 ### coreboot layout values
150 ## Use a small 8K stack
152 default STACK_SIZE=0x2000
155 ## Use a small 16K heap
157 default HEAP_SIZE=0x4000
160 ## CMOS settings not currently supported due to conflicts with factory BIOS
162 default USE_OPTION_TABLE = 0
165 ## Coreboot C code runs at this location in RAM
167 default _RAMBASE=0x00004000
170 ## Load the payload from the ROM
172 default CONFIG_ROM_PAYLOAD = 1
175 ### Defaults of options that you may want to override in the target config file
179 ## The default compiler
181 default CC="$(CROSS_COMPILE)gcc -m32"
185 ## Disable the gdb stub by default
187 default CONFIG_GDB_STUB=0
190 ## The Serial Console
193 # To Enable the Serial Console
194 default CONFIG_CONSOLE_SERIAL8250=1
196 ## Select the serial console baud rate
197 default TTYS0_BAUD=115200
198 #default TTYS0_BAUD=57600
199 #default TTYS0_BAUD=38400
200 #default TTYS0_BAUD=19200
201 #default TTYS0_BAUD=9600
202 #default TTYS0_BAUD=4800
203 #default TTYS0_BAUD=2400
204 #default TTYS0_BAUD=1200
206 # Select the serial console base port
207 default TTYS0_BASE=0x3f8
209 # Select the serial protocol
210 # This defaults to 8 data bits, 1 stop bit, and no parity
211 default TTYS0_LCS=0x3
214 ### Select the coreboot loglevel
216 ## EMERG 1 system is unusable
217 ## ALERT 2 action must be taken immediately
218 ## CRIT 3 critical conditions
219 ## ERR 4 error conditions
220 ## WARNING 5 warning conditions
221 ## NOTICE 6 normal but significant condition
222 ## INFO 7 informational
223 ## DEBUG 8 debug-level messages
224 ## SPEW 9 Way too many details
226 ## Request this level of debugging output
227 default DEFAULT_CONSOLE_LOGLEVEL=8
228 ## At a maximum only compile in this level of debugging
229 default MAXIMUM_CONSOLE_LOGLEVEL=8
232 ## Select power on after power fail setting
233 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
235 ## Things we may not have
239 # default CPU_OPT="-g"
246 default CONFIG_ROMFS=0