src/mainboard/sunw/ultra40/Config.lb

   1 ##
   2 ## Compute the location and size of where this firmware image
   3 ## (coreboot plus bootloader) will live in the boot rom chip.
   4 ##
   5 if USE_FALLBACK_IMAGE
   6         default ROM_SECTION_SIZE   = FALLBACK_SIZE
   7         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
   8 else
   9         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
  10         default ROM_SECTION_OFFSET = 0
  11 end
  12
  13 ##
  14 ## Compute the start location and size size of
  15 ## The coreboot bootloader.
  16 ##
  17 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  18 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  19 default CONFIG_ROM_PAYLOAD     = 1
  20
  21 ##
  22 ## Compute where this copy of coreboot will start in the boot rom
  23 ##
  24 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
  25
  26 ##
  27 ## Compute a range of ROM that can cached to speed up coreboot,
  28 ## execution speed.
  29 ##
  30 ## XIP_ROM_SIZE must be a power of 2.
  31 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  32 ##
  33 default XIP_ROM_SIZE=65536
  34 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
  35
  36 arch i386 end
  37
  38
  39 ##
  40 ## Build the objects we have code for in this directory.
  41 ##
  42
  43 driver mainboard.o
  44 #needed by irq_tables and mptable and acpi_tables
  45 object get_bus_conf.o
  46
  47 if HAVE_MP_TABLE object mptable.o end
  48 if HAVE_PIRQ_TABLE object irq_tables.o end
  49 #object reset.o
  50 if USE_DCACHE_RAM
  51
  52         if CONFIG_USE_INIT
  53                 makerule ./auto.o
  54                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  55                         action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
  56                 end
  57         else
  58                 makerule ./auto.inc
  59                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  60                         action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@"
  61                         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  62                         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
  63                 end
  64         end
  65
  66 else
  67         ##
  68         ## Romcc output
  69         ##
  70         makerule ./failover.E
  71                 depends "$(MAINBOARD)/failover.c ../romcc"
  72                 action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  73         end
  74
  75         makerule ./failover.inc
  76                 depends "$(MAINBOARD)/failover.c ../romcc"
  77                 action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  78         end
  79
  80         makerule ./auto.E
  81                 depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
  82                 action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  83         end
  84
  85         makerule ./auto.inc
  86                 depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
  87                 action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  88         end
  89
  90 end
  91
  92 ##
  93 ## Build our 16 bit and 32 bit coreboot entry code
  94 ##
  95 if USE_FALLBACK_IMAGE
  96         mainboardinit cpu/x86/16bit/entry16.inc
  97         ldscript /cpu/x86/16bit/entry16.lds
  98 end
  99
 100 mainboardinit cpu/x86/32bit/entry32.inc
 101
 102 if USE_DCACHE_RAM
 103         if CONFIG_USE_INIT
 104                 ldscript /cpu/x86/32bit/entry32.lds
 105         end
 106
 107         if CONFIG_USE_INIT
 108                 ldscript /cpu/amd/car/cache_as_ram.lds
 109         end
 110 end
 111
 112
 113 ##
 114 ## Build our reset vector (This is where coreboot is entered)
 115 ##
 116 if USE_FALLBACK_IMAGE
 117         mainboardinit cpu/x86/16bit/reset16.inc
 118         ldscript /cpu/x86/16bit/reset16.lds
 119 else
 120         mainboardinit cpu/x86/32bit/reset32.inc
 121         ldscript /cpu/x86/32bit/reset32.lds
 122 end
 123
 124 if USE_DCACHE_RAM
 125 else
 126         ### Should this be in the northbridge code?
 127         mainboardinit arch/i386/lib/cpu_reset.inc
 128 end
 129
 130 ##
 131 ## Include an id string (For safe flashing)
 132 ##
 133 mainboardinit southbridge/nvidia/ck804/id.inc
 134 ldscript /southbridge/nvidia/ck804/id.lds
 135
 136 ##
 137 ## ROMSTRAP table for CK804
 138 ##
 139 if USE_FALLBACK_IMAGE
 140         mainboardinit southbridge/nvidia/ck804/romstrap.inc
 141         ldscript /southbridge/nvidia/ck804/romstrap.lds
 142 end
 143
 144
 145
 146 if USE_DCACHE_RAM
 147         ##
 148         ## Setup Cache-As-Ram
 149         ##
 150         mainboardinit cpu/amd/car/cache_as_ram.inc
 151 end
 152
 153 ###
 154 ### This is the early phase of coreboot startup
 155 ### Things are delicate and we test to see if we should
 156 ### failover to another image.
 157 ###
 158 if USE_FALLBACK_IMAGE
 159         ldscript /arch/i386/lib/failover.lds
 160         if USE_DCACHE_RAM
 161         else
 162                 mainboardinit ./failover.inc
 163         end
 164 end
 165
 166 ##
 167 ## Setup RAM
 168 ##
 169 if USE_DCACHE_RAM
 170
 171         if CONFIG_USE_INIT
 172                 initobject auto.o
 173         else
 174                 mainboardinit ./auto.inc
 175         end
 176
 177 else
 178         # ROMCC
 179         mainboardinit cpu/x86/fpu/enable_fpu.inc
 180         mainboardinit cpu/x86/mmx/enable_mmx.inc
 181         mainboardinit cpu/x86/sse/enable_sse.inc
 182         mainboardinit ./auto.inc
 183         mainboardinit cpu/x86/sse/disable_sse.inc
 184         mainboardinit cpu/x86/mmx/disable_mmx.inc
 185
 186 end
 187
 188 ##
 189 ## Include the secondary Configuration files
 190 ##
 191 config chip.h
 192
 193 # sample config for tyan/s2895
 194 chip northbridge/amd/amdk8/root_complex
 195         device apic_cluster 0 on
 196                 chip cpu/amd/socket_940
 197                         device apic 0 on end
 198                 end
 199         end
 200         device pci_domain 0 on
 201                 chip northbridge/amd/amdk8 #mc0
 202                         device pci 18.0 on end # link 0
 203                         device pci 18.0 on # link1
 204                                 #  devices on link 0, link 0 == LDT 0
 205                                 chip southbridge/nvidia/ck804
 206                                         device pci 0.0 on end   # HT
 207                                         device pci 1.0 on # LPC
 208                                                 chip superio/smsc/lpc47m10x
 209                                                         device pnp 2e.0 off #  Floppy
 210                                                                  io 0x60 = 0x3f0
 211                                                                 irq 0x70 = 6
 212                                                                 drq 0x74 = 2
 213                                                         end
 214                                                         device pnp 2e.3 off #  Parallel Port
 215                                                                  io 0x60 = 0x378
 216                                                                 irq 0x70 = 7
 217                                                         end
 218                                                         device pnp 2e.4 on #  Com1
 219                                                                 io 0x60 = 0x3f8
 220                                                                 irq 0x70 = 4
 221                                                         end
 222                                                         device pnp 2e.5 off #  Com2
 223                                                                 io 0x60 = 0x2f8
 224                                                                 irq 0x70 = 3
 225                                                         end
 226                                                         device pnp 2e.7 off #  Keyboard
 227                                                                 io 0x60 = 0x60
 228                                                                 io 0x62 = 0x64
 229                                                                 irq 0x70 = 1
 230                                                                 irq 0x72 = 12
 231                                                         end
 232                                                 end
 233                                         end
 234                                         device pci 1.1 on # SM 0
 235                                                 chip drivers/generic/generic #dimm 0-0-0
 236                                                         device i2c 50 on end
 237                                                 end
 238                                                 chip drivers/generic/generic #dimm 0-0-1
 239                                                         device i2c 51 on end
 240                                                 end
 241                                                 chip drivers/generic/generic #dimm 0-1-0
 242                                                         device i2c 52 on end
 243                                                 end
 244                                                 chip drivers/generic/generic #dimm 0-1-1
 245                                                         device i2c 53 on end
 246                                                 end
 247                                                 chip drivers/generic/generic #dimm 1-0-0
 248                                                         device i2c 54 on end
 249                                                 end
 250                                                 chip drivers/generic/generic #dimm 1-0-1
 251                                                         device i2c 55 on end
 252                                                 end
 253                                                 chip drivers/generic/generic #dimm 1-1-0
 254                                                         device i2c 56 on end
 255                                                 end
 256                                                 chip drivers/generic/generic #dimm 1-1-1
 257                                                         device i2c 57 on end
 258                                                 end
 259                                         end # SM
 260                                         device pci 1.1 on # SM 1
 261 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
 262 #                                                chip drivers/generic/generic #PCIXA Slot1
 263 #                                                        device i2c 50 on end
 264 #                                                end
 265 #                                                chip drivers/generic/generic #PCIXB Slot1
 266 #                                                        device i2c 51 on end
 267 #                                                end
 268 #                                                chip drivers/generic/generic #PCIXB Slot2
 269 #                                                        device i2c 52 on end
 270 #                                                end
 271 #                                                chip drivers/generic/generic #PCI Slot1
 272 #                                                        device i2c 53 on end
 273 #                                                end
 274 #                                                chip drivers/generic/generic #Master CK804 PCI-E
 275 #                                                        device i2c 54 on end
 276 #                                                end
 277 #                                                chip drivers/generic/generic #Slave CK804 PCI-E
 278 #                                                        device i2c 55 on end
 279 #                                                end
 280                                                 chip drivers/generic/generic #MAC EEPROM
 281                                                         device i2c 51 on end
 282                                                 end
 283
 284                                         end # SM
 285                                         device pci 2.0 on end # USB 1.1
 286                                         device pci 2.1 on end # USB 2
 287                                         device pci 4.0 on end # ACI
 288                                         device pci 4.1 off end # MCI
 289                                         device pci 6.0 on end # IDE
 290                                         device pci 7.0 on end # SATA 1
 291                                         device pci 8.0 on end # SATA 0
 292                                         device pci 9.0 on end # PCI
 293                                         device pci a.0 on end # NIC
 294                                         device pci b.0 off end # PCI E 3
 295                                         device pci c.0 off end # PCI E 2
 296                                         device pci d.0 off end # PCI E 1
 297                                         device pci e.0 on end # PCI E 0
 298                                         register "ide0_enable" = "1"
 299                                         register "ide1_enable" = "1"
 300                                         register "sata0_enable" = "1"
 301                                         register "sata1_enable" = "1"
 302 #                                       register "nic_rom_address" = "0xfff80000" # 64k
 303 #                                       register "raid_rom_address" = "0xfff90000"
 304                                         register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 305                                         register "mac_eeprom_addr" = "0x51"
 306                                 end
 307                         end #  device pci 18.0
 308                         device pci 18.0 on end # link 2
 309                         device pci 18.1 on end
 310                         device pci 18.2 on end
 311                         device pci 18.3 on end
 312                 end # mc0
 313
 314                 chip northbridge/amd/amdk8
 315                         device pci 19.0 on end # link 0
 316                 device pci 19.0 on
 317                                 #  devices on link 1, link 1 == LDT 1
 318                                 chip southbridge/nvidia/ck804
 319                                         device pci 0.0 on end   # HT
 320                                         device pci 1.0 on end   # LPC
 321                                         device pci 1.1 off end # SM
 322                                         device pci 2.0 off end # USB 1.1
 323                                         device pci 2.1 off end # USB 2
 324                                         device pci 4.0 off end # ACI
 325                                         device pci 4.1 off end # MCI
 326                                         device pci 6.0 off end # IDE
 327                                         device pci 7.0 off end # SATA 1
 328                                         device pci 8.0 off end # SATA 0
 329                                         device pci 9.0 off end # PCI
 330                                         device pci a.0 on end # NIC
 331                                         device pci b.0 off end # PCI E 3
 332                                         device pci c.0 off end # PCI E 2
 333                                         device pci d.0 off end # PCI E 1
 334                                         device pci e.0 on end # PCI E 0
 335 #                                       register "nic_rom_address" = "0xfff80000" # 64k
 336                                         register "mac_eeprom_smbus" = "3"
 337                                         register "mac_eeprom_addr" = "0x51"
 338                                 end
 339                         end #  device pci 19.0
 340
 341                         device pci 19.0 on end
 342                         device pci 19.1 on end
 343                         device pci 19.2 on end
 344                         device pci 19.3 on end
 345                 end
 346         end # PCI domain
 347
 348 end #root_complex