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pci1x2x: remove latency/bridge control/cacheline size settings
[coreboot.git]
/
src
/
southbridge
/
ti
/
pci1x2x
/
chip.h
2011-04-20
Sven Schnelle
pci1x2x: remove latency/bridge control/cacheline size...
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2011-04-20
Sven Schnelle
pci1x2x: use devicetree register configuration
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