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HEAD
pci1x2x: remove latency/bridge control/cacheline size settings
[coreboot.git]
/
src
/
southbridge
/
ti
/
pci1x2x
/
chip.h
1
#ifndef SOUTHBRIDGE_TI_PCI1X2X_H
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#define SOUTHBRIDGE_TI_PCI1X2X_H
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4
extern struct chip_operations southbridge_ti_pci1x2x_ops;
5
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struct southbridge_ti_pci1x2x_config {
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int scr;
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int mrr;
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};
10
#endif