pci1x2x: remove latency/bridge control/cacheline size settings
[coreboot.git] / src / southbridge / ti / pci1x2x / chip.h
1 #ifndef SOUTHBRIDGE_TI_PCI1X2X_H
2 #define SOUTHBRIDGE_TI_PCI1X2X_H
3
4 extern struct chip_operations southbridge_ti_pci1x2x_ops;
5
6 struct southbridge_ti_pci1x2x_config {
7         int scr;
8         int mrr;
9 };
10 #endif