cpu/src/core_top.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.common_pkg.all;
   6 use work.core_pkg.all;
   7 use work.extension_pkg.all;
   8
   9 entity core_top is
  10
  11         port(
  12                 --System input pins
  13                         sys_clk : in std_logic;
  14                         sys_res : in std_logic;
  15                         result : out gp_register_t;
  16                         jump_result : out instruction_addr_t;
  17                         reg_wr_data : out gp_register_t
  18
  19                 );
  20
  21 end core_top;
  22
  23 architecture behav of core_top is
  24
  25                 signal jump_result_pin : instruction_addr_t;
  26                 signal prediction_result_pin : instruction_addr_t;
  27                 signal branch_prediction_bit_pin : std_logic;
  28                 signal alu_jump_bit_pin : std_logic;
  29                 signal instruction_pin : instruction_word_t;
  30                 signal prog_cnt_pin : instruction_addr_t;
  31
  32                 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
  33                 signal reg_wr_data_pin : gp_register_t;
  34                 signal reg_we_pin : std_logic;
  35                 signal to_next_stage : dec_op;
  36
  37 --              signal reg1_rd_data_pin : gp_register_t;
  38 --              signal reg2_rd_data_pin : gp_register_t;
  39
  40                  signal result_pin : gp_register_t;--reg
  41                  signal result_addr_pin : gp_addr_t;--reg
  42                  signal addr_pin : word_t; --memaddr
  43                  signal data_pin : gp_register_t; --mem data --ureg
  44                  signal alu_jump_pin : std_logic;--reg
  45                  signal brpr_pin  : std_logic;  --reg
  46                  signal wr_en_pin : std_logic;--regop --reg
  47                  signal dmem_pin  : std_logic;--memop
  48                  signal dmem_wr_en_pin : std_logic;
  49                  signal hword_pin  : std_logic;
  50                  signal byte_s_pin : std_logic;
  51
  52                                  signal gpm_in_pin : extmod_rec;
  53                                  signal gpm_out_pin : gp_register_t;
  54                  signal nop_pin : std_logic;
  55
  56
  57 begin
  58
  59         fetch_st : fetch_stage
  60                 generic map (
  61
  62                         '0',
  63                         '1'
  64                 )
  65
  66                 port map (
  67                 --System inputs
  68                         clk => sys_clk, --: in std_logic;
  69                         reset => sys_res, --: in std_logic;
  70
  71                 --Data inputs
  72                         jump_result => jump_result_pin, --: in instruction_addr_t;
  73                         prediction_result => prediction_result_pin, --: in instruction_addr_t;
  74                         branch_prediction_bit => branch_prediction_bit_pin,  --: in std_logic;
  75                         alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
  76
  77                 --Data outputs
  78                         instruction => instruction_pin, --: out instruction_word_t
  79                         prog_cnt => prog_cnt_pin
  80                 );
  81
  82         decode_st : decode_stage
  83                 generic map (
  84                         -- active reset value
  85                         '0',
  86                         -- active logic value
  87                         '1'
  88
  89                         )
  90                 port map (
  91                 --System inputs
  92                         clk => sys_clk, --: in std_logic;
  93                         reset => sys_res, -- : in std_logic;
  94
  95                 --Data inputs
  96                         instruction => instruction_pin, --: in instruction_word_t;
  97                         prog_cnt => prog_cnt_pin,
  98                         reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
  99                         reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
 100                         reg_we => reg_we_pin, --: in std_logic;
 101                         nop => nop_pin,
 102
 103                 --Data outputs
 104                         branch_prediction_res => prediction_result_pin, --: instruction_word_t;
 105                         branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
 106                         to_next_stage => to_next_stage
 107                 );
 108
 109           exec_st : execute_stage
 110                 generic map('0')
 111                 port map(sys_clk, sys_res,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
 112                 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
 113
 114           writeback_st : writeback_stage
 115                 generic map('0', '1')
 116                 port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
 117                 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
 118                 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin);
 119
 120
 121
 122
 123
 124 --init : process(all)
 125
 126 --begin
 127 --      jump_result_pin <= (others => '0');
 128 --      alu_jump_bit_pin <= '0';
 129 --      reg_w_addr_pin <= (others => '0');
 130 --      reg_wr_data_pin <= (others => '0');
 131 --      reg_we_pin <= '0';
 132
 133 --end process;
 134
 135         result <= result_pin;
 136         nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin);
 137
 138         jump_result <= jump_result_pin;
 139
 140         reg_wr_data <= reg_wr_data_pin;
 141 end behav;