2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
5 use work.common_pkg.all;
7 -------------------------------------------------------------------------------
9 -------------------------------------------------------------------------------
15 -------------------------------------------------------------------------------
17 -------------------------------------------------------------------------------
18 architecture behavior of pipeline_tb is
20 constant cc : time := 30 ns; -- test clock period
22 signal sys_clk_pin : std_logic;
23 signal sys_res_n_pin : std_logic;
26 signal dummy : std_logic;
28 signal jump_result_pin : instruction_addr_t;
29 signal prediction_result_pin : instruction_addr_t;
30 signal branch_prediction_bit_pin : std_logic;
31 signal alu_jump_bit_pin : std_logic;
32 signal instruction_pin : instruction_word_t;
34 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
35 signal reg_wr_data_pin : gp_register_t;
36 signal reg_we_pin : std_logic;
37 signal to_next_stage_pin : dec_op;
39 signal result_pin : gp_register_t;--reg
40 signal result_addr_pin : gp_addr_t;--reg
41 signal addr_pin : word_t; --memaddr
42 signal data_pin : gp_register_t; --mem data --ureg
43 signal alu_jump_pin : std_logic;--reg
44 signal brpr_pin : std_logic; --reg
45 signal wr_en_pin : std_logic;--regop --reg
46 signal dmem_pin : std_logic;--memop
47 signal dmem_wr_en_pin : std_logic;
48 signal hword_pin : std_logic;
49 signal byte_s_pin : std_logic;
53 -- instruction_ram : r_w_ram
55 -- PHYS_INSTR_ADDR_WIDTH,
61 -- instr_w_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
62 -- instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
68 fetch_st : fetch_stage
77 clk => sys_clk_pin, --: in std_logic;
78 reset => sys_res_n_pin, --: in std_logic;
81 jump_result => jump_result_pin, --: in instruction_addr_t;
82 prediction_result => prediction_result_pin, --: in instruction_addr_t;
83 branch_prediction_bit => branch_prediction_bit_pin, --: in std_logic;
84 alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
87 instruction => instruction_pin --: out instruction_word_t
90 decode_st : decode_stage
100 clk => sys_clk_pin, --: in std_logic;
101 reset => sys_res_n_pin, -- : in std_logic;
104 instruction => instruction_pin, --: in instruction_word_t;
105 reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
106 reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
107 reg_we => reg_we_pin, --: in std_logic;
110 branch_prediction_res => prediction_result_pin, --: instruction_word_t;
111 branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
112 to_next_stage => to_next_stage_pin
115 exec_st : execute_stage
117 port map(sys_clk_pin, sys_res_n_pin,to_next_stage_pin, result_pin, result_addr_pin,addr_pin,
118 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin);
120 writeback_st : writeback_stage
121 generic map('0', '1')
122 port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
123 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
124 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin);
128 -------------------------------------------------------------------------------
129 -- generate simulation clock
130 -------------------------------------------------------------------------------
139 -------------------------------------------------------------------------------
141 -------------------------------------------------------------------------------
144 -- wait for n clock cycles
145 procedure icwait(cycles : natural) is
147 for i in 1 to cycles loop
148 wait until sys_clk_pin = '1' and sys_clk_pin'event;
153 -----------------------------------------------------------------------------
155 -----------------------------------------------------------------------------
156 sys_res_n_pin <= '0';
157 -- reg_w_addr_pin <= (others => '0');
158 -- reg_wr_data_pin <= (others => '0');
159 -- reg_we_pin <= '0';
163 sys_res_n_pin <= '1';
164 wait until sys_res_n_pin = '1';
169 ---------------------------------------------------------------------------
171 ---------------------------------------------------------------------------
173 report "Test finished"
181 -------------------------------------------------------------------------------
183 -------------------------------------------------------------------------------
184 configuration pipeline_conf_beh of pipeline_tb is
186 for fetch_st : fetch_stage use entity work.fetch_stage(behav);
188 for decode_st : decode_stage use entity work.decode_stage(behav);
190 for exec_st : execute_stage use entity work.execute_stage(behav);
192 for writeback_st : writeback_stage use entity work.writeback_stage(behav);
196 end pipeline_conf_beh;