db/
incremental_db
work/
+dt.asm.rpt
+dt.done
+dt.dpf
+dt.fit.rpt
+dt.fit.summary
+dt.flow.rpt
+dt.map.rpt
+dt.map.summary
+dt.pin
+dt.pof
+dt.rbf
+dt.sof
+dt.tan.rpt
+dt.tan.summary
+output_file.pof
+output_file.rbf
+++ /dev/null
-Assembler report for dt
-Sun Dec 19 20:36:48 2010
-Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Assembler Summary
- 3. Assembler Settings
- 4. Assembler Generated Files
- 5. Assembler Device Options: dt.sof
- 6. Assembler Device Options: dt.pof
- 7. Assembler Device Options: dt.rbf
- 8. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2010 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Altera Program License
-Subscription Agreement, Altera MegaCore Function License
-Agreement, or other applicable license agreement, including,
-without limitation, that your use is for the sole purpose of
-programming logic devices manufactured by Altera and sold by
-Altera or its authorized distributors. Please refer to the
-applicable agreement for further details.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary ;
-+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Sun Dec 19 20:36:48 2010 ;
-; Revision Name ; dt ;
-; Top-level Entity Name ; core_top ;
-; Family ; Cyclone ;
-; Device ; EP1C12Q240C8 ;
-+-----------------------+---------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------+
-; Assembler Settings ;
-+-----------------------------------------------------------------------------+----------+---------------+
-; Option ; Setting ; Default Value ;
-+-----------------------------------------------------------------------------+----------+---------------+
-; Generate compressed bitstreams ; Off ; On ;
-; Generate Raw Binary File (.rbf) For Target Device ; On ; Off ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Compression mode ; Off ; Off ;
-; Clock source for configuration device ; Internal ; Internal ;
-; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
-; Divide clock frequency by ; 1 ; 1 ;
-; Auto user code ; Off ; Off ;
-; Use configuration device ; On ; On ;
-; Configuration device ; Auto ; Auto ;
-; Configuration device auto user code ; Off ; Off ;
-; Auto-increment JTAG user code for multiple configuration devices ; On ; On ;
-; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
-; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
-; Hexadecimal Output File start address ; 0 ; 0 ;
-; Hexadecimal Output File count direction ; Up ; Up ;
-; Release clears before tri-states ; Off ; Off ;
-; Auto-restart configuration after error ; On ; On ;
-; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
-; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
-; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
-; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
-+-----------------------------------------------------------------------------+----------+---------------+
-
-
-+---------------------------+
-; Assembler Generated Files ;
-+---------------------------+
-; File Name ;
-+---------------------------+
-; dt.sof ;
-; dt.pof ;
-; dt.rbf ;
-+---------------------------+
-
-
-+----------------------------------+
-; Assembler Device Options: dt.sof ;
-+----------------+-----------------+
-; Option ; Setting ;
-+----------------+-----------------+
-; Device ; EP1C12Q240C8 ;
-; JTAG usercode ; 0xFFFFFFFF ;
-; Checksum ; 0x002A3659 ;
-+----------------+-----------------+
-
-
-+----------------------------------+
-; Assembler Device Options: dt.pof ;
-+--------------------+-------------+
-; Option ; Setting ;
-+--------------------+-------------+
-; Device ; EPCS4 ;
-; JTAG usercode ; 0x00000000 ;
-; Checksum ; 0x03B3DAC6 ;
-; Compression Ratio ; 1 ;
-+--------------------+-------------+
-
-
-+----------------------------------+
-; Assembler Device Options: dt.rbf ;
-+---------------------+------------+
-; Option ; Setting ;
-+---------------------+------------+
-; Raw Binary File ; ;
-; Compression Ratio ; 1 ;
-+---------------------+------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus II Assembler
- Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
- Info: Processing started: Sun Dec 19 20:36:47 2010
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off dt -c dt
-Info: Assembler is generating device programming files
-Info: Quartus II Assembler was successful. 0 errors, 0 warnings
- Info: Peak virtual memory: 230 megabytes
- Info: Processing ended: Sun Dec 19 20:36:48 2010
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:01
-
-
+++ /dev/null
-Sun Dec 19 20:36:51 2010
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-
-<pin_planner>
- <pin_info>
- </pin_info>
- <buses>
- </buses>
- <group_file_association>
- </group_file_association>
- <pin_planner_file_specifies>
- </pin_planner_file_specifies>
-</pin_planner>
+++ /dev/null
-Fitter report for dt
-Sun Dec 19 20:36:44 2010
-Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Fitter Summary
- 3. Fitter Settings
- 4. Parallel Compilation
- 5. Incremental Compilation Preservation Summary
- 6. Incremental Compilation Partition Settings
- 7. Incremental Compilation Placement Preservation
- 8. Pin-Out File
- 9. Fitter Resource Usage Summary
- 10. Fitter Partition Statistics
- 11. Input Pins
- 12. Output Pins
- 13. I/O Bank Usage
- 14. All Package Pins
- 15. Output Pin Default Load For Reported TCO
- 16. Fitter Resource Utilization by Entity
- 17. Delay Chain Summary
- 18. Pad To Core Delay Chain Fanout
- 19. Control Signals
- 20. Global & Other Fast Signals
- 21. Non-Global High Fan-Out Signals
- 22. Fitter RAM Summary
- 23. Interconnect Usage Summary
- 24. LAB Logic Elements
- 25. LAB-wide Signals
- 26. LAB Signals Sourced
- 27. LAB Signals Sourced Out
- 28. LAB Distinct Inputs
- 29. Fitter Device Options
- 30. Estimated Delay Added for Hold Timing Summary
- 31. Estimated Delay Added for Hold Timing Details
- 32. Fitter Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2010 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Altera Program License
-Subscription Agreement, Altera MegaCore Function License
-Agreement, or other applicable license agreement, including,
-without limitation, that your use is for the sole purpose of
-programming logic devices manufactured by Altera and sold by
-Altera or its authorized distributors. Please refer to the
-applicable agreement for further details.
-
-
-
-+-----------------------------------------------------------------------+
-; Fitter Summary ;
-+-----------------------+-----------------------------------------------+
-; Fitter Status ; Successful - Sun Dec 19 20:36:44 2010 ;
-; Quartus II Version ; 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition ;
-; Revision Name ; dt ;
-; Top-level Entity Name ; core_top ;
-; Family ; Cyclone ;
-; Device ; EP1C12Q240C8 ;
-; Timing Models ; Final ;
-; Total logic elements ; 1,646 / 12,060 ( 14 % ) ;
-; Total pins ; 32 / 173 ( 18 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 66,560 / 239,616 ( 28 % ) ;
-; Total PLLs ; 0 / 2 ( 0 % ) ;
-+-----------------------+-----------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings ;
-+----------------------------------------------------------------------------+--------------------------------+--------------------------------+
-; Option ; Setting ; Default Value ;
-+----------------------------------------------------------------------------+--------------------------------+--------------------------------+
-; Device ; EP1C12Q240C8 ; ;
-; Fit Attempts to Skip ; 0 ; 0.0 ;
-; Device I/O Standard ; 3.3-V LVCMOS ; ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Use TimeQuest Timing Analyzer ; Off ; Off ;
-; Router Timing Optimization Level ; Normal ; Normal ;
-; Placement Effort Multiplier ; 1.0 ; 1.0 ;
-; Router Effort Multiplier ; 1.0 ; 1.0 ;
-; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
-; Optimize Multi-Corner Timing ; Off ; Off ;
-; Optimize Timing ; Normal compilation ; Normal compilation ;
-; Optimize Timing for ECOs ; Off ; Off ;
-; Regenerate full fit report during ECO compiles ; Off ; Off ;
-; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
-; Limit to One Fitting Attempt ; Off ; Off ;
-; Final Placement Optimizations ; Automatically ; Automatically ;
-; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
-; Fitter Initial Placement Seed ; 1 ; 1 ;
-; Slow Slew Rate ; Off ; Off ;
-; PCI I/O ; Off ; Off ;
-; Weak Pull-Up Resistor ; Off ; Off ;
-; Enable Bus-Hold Circuitry ; Off ; Off ;
-; Auto Global Memory Control Signals ; Off ; Off ;
-; Auto Packed Registers ; Auto ; Auto ;
-; Auto Delay Chains ; On ; On ;
-; Auto Merge PLLs ; On ; On ;
-; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
-; Perform Register Duplication for Performance ; Off ; Off ;
-; Perform Register Retiming for Performance ; Off ; Off ;
-; Perform Asynchronous Signal Pipelining ; Off ; Off ;
-; Fitter Effort ; Auto Fit ; Auto Fit ;
-; Physical Synthesis Effort Level ; Normal ; Normal ;
-; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
-; Auto Register Duplication ; Auto ; Auto ;
-; Auto Global Clock ; On ; On ;
-; Auto Global Register Control Signals ; On ; On ;
-; Stop After Congestion Map Generation ; Off ; Off ;
-; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
-+----------------------------------------------------------------------------+--------------------------------+--------------------------------+
-
-
-Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
-+-------------------------------------+
-; Parallel Compilation ;
-+----------------------------+--------+
-; Processors ; Number ;
-+----------------------------+--------+
-; Number detected on machine ; 2 ;
-; Maximum allowed ; 1 ;
-+----------------------------+--------+
-
-
-+----------------------------------------------+
-; Incremental Compilation Preservation Summary ;
-+---------------------+------------------------+
-; Type ; Value ;
-+---------------------+------------------------+
-; Placement (by node) ; ;
-; -- Requested ; 0 / 1777 ( 0.00 % ) ;
-; -- Achieved ; 0 / 1777 ( 0.00 % ) ;
-; ; ;
-; Routing (by net) ; ;
-; -- Requested ; 0 / 0 ( 0.00 % ) ;
-; -- Achieved ; 0 / 0 ( 0.00 % ) ;
-+---------------------+------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Partition Settings ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Placement Preservation ;
-+--------------------------------+---------+-------------------+-------------------------+-------------------+
-; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
-+--------------------------------+---------+-------------------+-------------------------+-------------------+
-; Top ; 1775 ; 0 ; N/A ; Source File ;
-; hard_block:auto_generated_inst ; 2 ; 0 ; N/A ; Source File ;
-+--------------------------------+---------+-------------------+-------------------------+-------------------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in /home/stefan/processor/calu/dt/dt.pin.
-
-
-+-----------------------------------------------------------------------------------------+
-; Fitter Resource Usage Summary ;
-+---------------------------------------------+-------------------------------------------+
-; Resource ; Usage ;
-+---------------------------------------------+-------------------------------------------+
-; Total logic elements ; 1,646 / 12,060 ( 14 % ) ;
-; -- Combinational with no register ; 1126 ;
-; -- Register only ; 26 ;
-; -- Combinational with a register ; 494 ;
-; ; ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 827 ;
-; -- 3 input functions ; 474 ;
-; -- 2 input functions ; 292 ;
-; -- 1 input functions ; 27 ;
-; -- 0 input functions ; 0 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 1470 ;
-; -- arithmetic mode ; 176 ;
-; -- qfbk mode ; 179 ;
-; -- register cascade mode ; 0 ;
-; -- synchronous clear/load mode ; 246 ;
-; -- asynchronous clear/load mode ; 492 ;
-; ; ;
-; Total registers ; 520 / 12,567 ( 4 % ) ;
-; Total LABs ; 174 / 1,206 ( 14 % ) ;
-; Logic elements in carry chains ; 184 ;
-; User inserted logic elements ; 0 ;
-; Virtual pins ; 0 ;
-; I/O pins ; 32 / 173 ( 18 % ) ;
-; -- Clock pins ; 1 / 2 ( 50 % ) ;
-; Global signals ; 2 ;
-; M4Ks ; 18 / 52 ( 35 % ) ;
-; Total memory bits ; 66,560 / 239,616 ( 28 % ) ;
-; Total RAM block bits ; 82,944 / 239,616 ( 35 % ) ;
-; PLLs ; 0 / 2 ( 0 % ) ;
-; Global clocks ; 2 / 8 ( 25 % ) ;
-; JTAGs ; 0 / 1 ( 0 % ) ;
-; ASMI Blocks ; 0 / 1 ( 0 % ) ;
-; CRC blocks ; 0 / 1 ( 0 % ) ;
-; Average interconnect usage (total/H/V) ; 12% / 12% / 11% ;
-; Peak interconnect usage (total/H/V) ; 42% / 44% / 40% ;
-; Maximum fan-out node ; sys_clk ;
-; Maximum fan-out ; 538 ;
-; Highest non-global fan-out signal ; execute_stage:exec_st|right_operand[0]~19 ;
-; Highest non-global fan-out ; 104 ;
-; Total fan-out ; 7140 ;
-; Average fan-out ; 4.20 ;
-+---------------------------------------------+-------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Fitter Partition Statistics ;
-+---------------------------------------------+--------------------+--------------------------------+
-; Statistic ; Top ; hard_block:auto_generated_inst ;
-+---------------------------------------------+--------------------+--------------------------------+
-; Difficulty Clustering Region ; Low ; Low ;
-; ; ; ;
-; Total logic elements ; 1646 ; 0 ;
-; -- Combinational with no register ; 1126 ; 0 ;
-; -- Register only ; 26 ; 0 ;
-; -- Combinational with a register ; 494 ; 0 ;
-; ; ; ;
-; Logic element usage by number of LUT inputs ; ; ;
-; -- 4 input functions ; 0 ; 0 ;
-; -- 3 input functions ; 0 ; 0 ;
-; -- 2 input functions ; 0 ; 0 ;
-; -- 1 input functions ; 0 ; 0 ;
-; -- 0 input functions ; 0 ; 0 ;
-; ; ; ;
-; Logic elements by mode ; ; ;
-; -- normal mode ; 0 ; 0 ;
-; -- arithmetic mode ; 0 ; 0 ;
-; -- qfbk mode ; 0 ; 0 ;
-; -- register cascade mode ; 0 ; 0 ;
-; -- synchronous clear/load mode ; 0 ; 0 ;
-; -- asynchronous clear/load mode ; 0 ; 0 ;
-; ; ; ;
-; Total registers ; 520 / 6030 ( 8 % ) ; 0 / 6030 ( 0 % ) ;
-; Virtual pins ; 0 ; 0 ;
-; I/O pins ; 32 ; 0 ;
-; DSP block 9-bit elements ; 0 ; 0 ;
-; Total memory bits ; 66560 ; 0 ;
-; Total RAM block bits ; 82944 ; 0 ;
-; M4K ; 18 / 52 ( 34 % ) ; 0 / 52 ( 0 % ) ;
-; ; ; ;
-; Connections ; ; ;
-; -- Input Connections ; 0 ; 0 ;
-; -- Registered Input Connections ; 0 ; 0 ;
-; -- Output Connections ; 0 ; 0 ;
-; -- Registered Output Connections ; 0 ; 0 ;
-; ; ; ;
-; Internal Connections ; ; ;
-; -- Total Connections ; 7455 ; 0 ;
-; -- Registered Connections ; 1762 ; 0 ;
-; ; ; ;
-; External Connections ; ; ;
-; -- Top ; 0 ; 0 ;
-; -- hard_block:auto_generated_inst ; 0 ; 0 ;
-; ; ; ;
-; Partition Interface ; ; ;
-; -- Input Ports ; 3 ; 0 ;
-; -- Output Ports ; 29 ; 0 ;
-; -- Bidir Ports ; 0 ; 0 ;
-; ; ; ;
-; Registered Ports ; ; ;
-; -- Registered Input Ports ; 0 ; 0 ;
-; -- Registered Output Ports ; 0 ; 0 ;
-; ; ; ;
-; Port Connectivity ; ; ;
-; -- Input Ports driven by GND ; 0 ; 0 ;
-; -- Output Ports driven by GND ; 0 ; 0 ;
-; -- Input Ports driven by VCC ; 0 ; 0 ;
-; -- Output Ports driven by VCC ; 0 ; 0 ;
-; -- Input Ports with no Source ; 0 ; 0 ;
-; -- Output Ports with no Source ; 0 ; 0 ;
-; -- Input Ports with no Fanout ; 0 ; 0 ;
-; -- Output Ports with no Fanout ; 0 ; 0 ;
-+---------------------------------------------+--------------------+--------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins ;
-+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
-+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
-; bus_rx ; 17 ; 1 ; 0 ; 21 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; Off ; Fitter ;
-; sys_clk ; 152 ; 3 ; 53 ; 15 ; 2 ; 538 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; Off ; User ;
-; sys_res ; 42 ; 1 ; 0 ; 6 ; 0 ; 504 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; Off ; User ;
-+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins ;
-+----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+----------------------+---------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
-+----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+----------------------+---------------------+
-; bus_tx ; 166 ; 3 ; 53 ; 22 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 10 pF ; - ; - ;
-; sseg0[0] ; 83 ; 4 ; 14 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
-; sseg0[1] ; 86 ; 4 ; 16 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
-; sseg0[2] ; 144 ; 3 ; 53 ; 12 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
-; sseg0[3] ; 39 ; 1 ; 0 ; 11 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
-; sseg0[4] ; 213 ; 2 ; 18 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
-; sseg0[5] ; 88 ; 4 ; 18 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
-; sseg0[6] ; 214 ; 2 ; 16 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
-; sseg1[0] ; 18 ; 1 ; 0 ; 21 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
-; sseg1[1] ; 93 ; 4 ; 26 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
-; sseg1[2] ; 94 ; 4 ; 28 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
-; sseg1[3] ; 162 ; 3 ; 53 ; 21 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
-; sseg1[4] ; 207 ; 2 ; 28 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
-; sseg1[5] ; 206 ; 2 ; 28 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
-; sseg1[6] ; 95 ; 4 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
-; sseg2[0] ; 21 ; 1 ; 0 ; 20 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
-; sseg2[1] ; 201 ; 2 ; 32 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
-; sseg2[2] ; 161 ; 3 ; 53 ; 20 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
-; sseg2[3] ; 202 ; 2 ; 32 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
-; sseg2[4] ; 20 ; 1 ; 0 ; 20 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
-; sseg2[5] ; 200 ; 2 ; 32 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
-; sseg2[6] ; 160 ; 3 ; 53 ; 20 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
-; sseg3[0] ; 87 ; 4 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
-; sseg3[1] ; 84 ; 4 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
-; sseg3[2] ; 38 ; 1 ; 0 ; 11 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
-; sseg3[3] ; 23 ; 1 ; 0 ; 16 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
-; sseg3[4] ; 85 ; 4 ; 16 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
-; sseg3[5] ; 215 ; 2 ; 16 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
-; sseg3[6] ; 216 ; 2 ; 16 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
-+----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+----------------------+---------------------+
-
-
-+------------------------------------------------------------+
-; I/O Bank Usage ;
-+----------+------------------+---------------+--------------+
-; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
-+----------+------------------+---------------+--------------+
-; 1 ; 10 / 44 ( 23 % ) ; 3.3V ; -- ;
-; 2 ; 9 / 42 ( 21 % ) ; 3.3V ; -- ;
-; 3 ; 6 / 45 ( 13 % ) ; 3.3V ; -- ;
-; 4 ; 9 / 42 ( 21 % ) ; 3.3V ; -- ;
-+----------+------------------+---------------+--------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins ;
-+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; 1 ; 0 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 2 ; 1 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 3 ; 2 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 4 ; 3 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 5 ; 4 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 6 ; 5 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 7 ; 6 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 8 ; 7 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 11 ; 8 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 12 ; 9 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 13 ; 10 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 14 ; 11 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 15 ; 12 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 16 ; 13 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 17 ; 14 ; 1 ; bus_rx ; input ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; Off ;
-; 18 ; 15 ; 1 ; sseg1[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; Off ;
-; 19 ; 16 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 20 ; 17 ; 1 ; sseg2[4] ; output ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; Off ;
-; 21 ; 18 ; 1 ; sseg2[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; Off ;
-; 22 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 23 ; 28 ; 1 ; sseg3[3] ; output ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; Off ;
-; 24 ; 29 ; 1 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; On ;
-; 25 ; 30 ; 1 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ;
-; 26 ; 31 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
-; 27 ; ; ; VCCA_PLL1 ; power ; ; 1.5V ; -- ; ; -- ; -- ;
-; 28 ; 32 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; 29 ; 33 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; 30 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
-; 31 ; ; ; GNDG_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
-; 32 ; 34 ; 1 ; ^nCEO ; ; ; ; -- ; ; -- ; -- ;
-; 33 ; 35 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
-; 34 ; 36 ; 1 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
-; 35 ; 37 ; 1 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
-; 36 ; 38 ; 1 ; ^DCLK ; bidir ; ; ; -- ; ; -- ; -- ;
-; 37 ; 39 ; 1 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; On ;
-; 38 ; 40 ; 1 ; sseg3[2] ; output ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; Off ;
-; 39 ; 41 ; 1 ; sseg0[3] ; output ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; Off ;
-; 40 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 41 ; 52 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 42 ; 53 ; 1 ; sys_res ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
-; 43 ; 54 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 44 ; 55 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 45 ; 56 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 46 ; 57 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 47 ; 58 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 48 ; 59 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 49 ; 60 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 50 ; 61 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 51 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 52 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 53 ; 62 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 54 ; 63 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 55 ; 64 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 56 ; 65 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 57 ; 66 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 58 ; 67 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 59 ; 68 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 60 ; 69 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 61 ; 70 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 62 ; 71 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 63 ; 72 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 64 ; 73 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 65 ; 74 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 66 ; 75 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 67 ; 76 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 68 ; 77 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 69 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 70 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 71 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 72 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
-; 73 ; 78 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 74 ; 79 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 75 ; 80 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 76 ; 81 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 77 ; 82 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 78 ; 83 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 79 ; 84 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 80 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 81 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
-; 82 ; 86 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 83 ; 87 ; 4 ; sseg0[0] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
-; 84 ; 88 ; 4 ; sseg3[1] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
-; 85 ; 89 ; 4 ; sseg3[4] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
-; 86 ; 90 ; 4 ; sseg0[1] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
-; 87 ; 91 ; 4 ; sseg3[0] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
-; 88 ; 92 ; 4 ; sseg0[5] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
-; 89 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 90 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
-; 91 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 92 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 93 ; 100 ; 4 ; sseg1[1] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
-; 94 ; 103 ; 4 ; sseg1[2] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
-; 95 ; 104 ; 4 ; sseg1[6] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
-; 96 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 97 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
-; 98 ; 106 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 99 ; 107 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 100 ; 108 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 101 ; 109 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 102 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 103 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
-; 104 ; 118 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 105 ; 119 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 106 ; 120 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 107 ; 121 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 108 ; 122 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 109 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 110 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
-; 111 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 112 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 113 ; 123 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 114 ; 124 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 115 ; 125 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 116 ; 126 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 117 ; 127 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 118 ; 128 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 119 ; 129 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 120 ; 130 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 121 ; 131 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 122 ; 132 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 123 ; 133 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 124 ; 134 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 125 ; 135 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 126 ; 136 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 127 ; 137 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 128 ; 138 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 129 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 130 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 131 ; 139 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 132 ; 140 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 133 ; 141 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 134 ; 142 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 135 ; 143 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 136 ; 144 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 137 ; 145 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 138 ; 146 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 139 ; 147 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 140 ; 148 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 141 ; 149 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 142 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 143 ; 160 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 144 ; 161 ; 3 ; sseg0[2] ; output ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; Off ;
-; 145 ; 162 ; 3 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
-; 146 ; 163 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
-; 147 ; 164 ; 3 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
-; 148 ; 165 ; 3 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
-; 149 ; 166 ; 3 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
-; 150 ; ; ; GNDG_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
-; 151 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
-; 152 ; 167 ; 3 ; sys_clk ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
-; 153 ; 168 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; 154 ; ; ; VCCA_PLL2 ; power ; ; 1.5V ; -- ; ; -- ; -- ;
-; 155 ; 169 ; 3 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
-; 156 ; 170 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 157 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 158 ; 180 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 159 ; 181 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 160 ; 182 ; 3 ; sseg2[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; Off ;
-; 161 ; 183 ; 3 ; sseg2[2] ; output ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; Off ;
-; 162 ; 184 ; 3 ; sseg1[3] ; output ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; Off ;
-; 163 ; 185 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 164 ; 186 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 165 ; 187 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 166 ; 188 ; 3 ; bus_tx ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
-; 167 ; 189 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 168 ; 190 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 169 ; 191 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 170 ; 192 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 171 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 172 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 173 ; 193 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 174 ; 194 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 175 ; 195 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 176 ; 196 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 177 ; 197 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 178 ; 198 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 179 ; 199 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 180 ; 200 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 181 ; 201 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 182 ; 202 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 183 ; 203 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 184 ; 204 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 185 ; 205 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 186 ; 206 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 187 ; 207 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 188 ; 208 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 189 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 190 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 191 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
-; 192 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 193 ; 209 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 194 ; 210 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 195 ; 211 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 196 ; 212 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 197 ; 213 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 198 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
-; 199 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 200 ; 222 ; 2 ; sseg2[5] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
-; 201 ; 223 ; 2 ; sseg2[1] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
-; 202 ; 224 ; 2 ; sseg2[3] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
-; 203 ; 225 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 204 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
-; 205 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 206 ; 227 ; 2 ; sseg1[5] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
-; 207 ; 228 ; 2 ; sseg1[4] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
-; 208 ; 231 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 209 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 210 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 211 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
-; 212 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 213 ; 239 ; 2 ; sseg0[4] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
-; 214 ; 240 ; 2 ; sseg0[6] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
-; 215 ; 241 ; 2 ; sseg3[5] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
-; 216 ; 242 ; 2 ; sseg3[6] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
-; 217 ; 243 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 218 ; 244 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 219 ; 245 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 220 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
-; 221 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 222 ; 247 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 223 ; 248 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 224 ; 249 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 225 ; 250 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 226 ; 251 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 227 ; 252 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 228 ; 253 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 229 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
-; 230 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 231 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 232 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 233 ; 254 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 234 ; 255 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 235 ; 256 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 236 ; 257 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 237 ; 258 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 238 ; 259 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 239 ; 260 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 240 ; 261 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+------------------------------------------------------------------+
-; Output Pin Default Load For Reported TCO ;
-+---------------------+-------+------------------------------------+
-; I/O Standard ; Load ; Termination Resistance ;
-+---------------------+-------+------------------------------------+
-; 3.3-V LVTTL ; 10 pF ; Not Available ;
-; 3.3-V LVCMOS ; 10 pF ; Not Available ;
-; 2.5 V ; 10 pF ; Not Available ;
-; 1.8 V ; 10 pF ; Not Available ;
-; 1.5 V ; 10 pF ; Not Available ;
-; SSTL-3 Class I ; 30 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
-; SSTL-3 Class II ; 30 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
-; SSTL-2 Class I ; 30 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
-; SSTL-2 Class II ; 30 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
-; Differential SSTL-2 ; 10 pF ; (See SSTL-2) ;
-; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ;
-; LVDS ; 4 pF ; 100 Ohm (Differential) ;
-; RSDS ; 10 pF ; 100 Ohm (Differential) ;
-+---------------------+-------+------------------------------------+
-Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity ;
-+----------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------------------------+--------------+
-; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
-+----------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------------------------+--------------+
-; |core_top ; 1646 (0) ; 520 ; 66560 ; 18 ; 32 ; 0 ; 1126 (0) ; 26 (0) ; 494 (0) ; 184 (0) ; 179 (0) ; |core_top ; ;
-; |decode_stage:decode_st| ; 212 (150) ; 106 ; 1024 ; 2 ; 0 ; 0 ; 106 (44) ; 0 (0) ; 106 (106) ; 11 (11) ; 3 (3) ; |core_top|decode_stage:decode_st ; ;
-; |decoder:decoder_inst| ; 62 (62) ; 0 ; 0 ; 0 ; 0 ; 0 ; 62 (62) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|decoder:decoder_inst ; ;
-; |r2_w_ram:register_ram| ; 0 (0) ; 0 ; 1024 ; 2 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram ; ;
-; |altsyncram:ram_rtl_1| ; 0 (0) ; 0 ; 512 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1 ; ;
-; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 512 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated ; ;
-; |altsyncram:ram_rtl_2| ; 0 (0) ; 0 ; 512 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2 ; ;
-; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 512 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2|altsyncram_emk1:auto_generated ; ;
-; |execute_stage:exec_st| ; 836 (137) ; 71 ; 0 ; 0 ; 0 ; 0 ; 765 (98) ; 1 (1) ; 70 (38) ; 108 (0) ; 68 (38) ; |core_top|execute_stage:exec_st ; ;
-; |alu:alu_inst| ; 637 (324) ; 0 ; 0 ; 0 ; 0 ; 0 ; 637 (324) ; 0 (0) ; 0 (0) ; 78 (44) ; 30 (27) ; |core_top|execute_stage:exec_st|alu:alu_inst ; ;
-; |exec_op:add_inst| ; 67 (67) ; 0 ; 0 ; 0 ; 0 ; 0 ; 67 (67) ; 0 (0) ; 0 (0) ; 34 (34) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:add_inst ; ;
-; |exec_op:shift_inst| ; 246 (246) ; 0 ; 0 ; 0 ; 0 ; 0 ; 246 (246) ; 0 (0) ; 0 (0) ; 0 (0) ; 3 (3) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst ; ;
-; |extension_gpm:gpmp_inst| ; 62 (62) ; 32 ; 0 ; 0 ; 0 ; 0 ; 30 (30) ; 0 (0) ; 32 (32) ; 30 (30) ; 0 (0) ; |core_top|execute_stage:exec_st|extension_gpm:gpmp_inst ; ;
-; |fetch_stage:fetch_st| ; 44 (23) ; 29 ; 0 ; 0 ; 0 ; 0 ; 15 (12) ; 0 (0) ; 29 (11) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st ; ;
-; |rom:instruction_ram| ; 21 (21) ; 18 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 18 (18) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st|rom:instruction_ram ; ;
-; |writeback_stage:writeback_st| ; 554 (141) ; 314 ; 65536 ; 16 ; 0 ; 0 ; 240 (77) ; 25 (0) ; 289 (64) ; 65 (0) ; 108 (106) ; |core_top|writeback_stage:writeback_st ; ;
-; |extension_7seg:sseg| ; 47 (47) ; 47 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 17 (17) ; 30 (30) ; 0 (0) ; 1 (1) ; |core_top|writeback_stage:writeback_st|extension_7seg:sseg ; ;
-; |extension_uart:uart| ; 366 (144) ; 203 ; 0 ; 0 ; 0 ; 0 ; 163 (38) ; 8 (0) ; 195 (106) ; 65 (0) ; 1 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart ; ;
-; |rs232_rx:rs232_rx_inst| ; 158 (158) ; 73 ; 0 ; 0 ; 0 ; 0 ; 85 (85) ; 8 (8) ; 65 (65) ; 48 (48) ; 1 (1) ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst ; ;
-; |rs232_tx:rs232_tx_inst| ; 64 (64) ; 24 ; 0 ; 0 ; 0 ; 0 ; 40 (40) ; 0 (0) ; 24 (24) ; 17 (17) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst ; ;
-; |r_w_ram:data_ram| ; 0 (0) ; 0 ; 65536 ; 16 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|r_w_ram:data_ram ; ;
-; |altsyncram:ram_rtl_0| ; 0 (0) ; 0 ; 65536 ; 16 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0 ; ;
-; |altsyncram_grk1:auto_generated| ; 0 (0) ; 0 ; 65536 ; 16 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated ; ;
-+----------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------------------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+-----------------------------------------------------------------------------------+
-; Delay Chain Summary ;
-+----------+----------+---------------+---------------+-----------------------+-----+
-; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;
-+----------+----------+---------------+---------------+-----------------------+-----+
-; bus_tx ; Output ; -- ; -- ; -- ; -- ;
-; sseg0[6] ; Output ; -- ; -- ; -- ; -- ;
-; sseg0[5] ; Output ; -- ; -- ; -- ; -- ;
-; sseg0[4] ; Output ; -- ; -- ; -- ; -- ;
-; sseg0[3] ; Output ; -- ; -- ; -- ; -- ;
-; sseg0[2] ; Output ; -- ; -- ; -- ; -- ;
-; sseg0[1] ; Output ; -- ; -- ; -- ; -- ;
-; sseg0[0] ; Output ; -- ; -- ; -- ; -- ;
-; sseg1[6] ; Output ; -- ; -- ; -- ; -- ;
-; sseg1[5] ; Output ; -- ; -- ; -- ; -- ;
-; sseg1[4] ; Output ; -- ; -- ; -- ; -- ;
-; sseg1[3] ; Output ; -- ; -- ; -- ; -- ;
-; sseg1[2] ; Output ; -- ; -- ; -- ; -- ;
-; sseg1[1] ; Output ; -- ; -- ; -- ; -- ;
-; sseg1[0] ; Output ; -- ; -- ; -- ; -- ;
-; sseg2[6] ; Output ; -- ; -- ; -- ; -- ;
-; sseg2[5] ; Output ; -- ; -- ; -- ; -- ;
-; sseg2[4] ; Output ; -- ; -- ; -- ; -- ;
-; sseg2[3] ; Output ; -- ; -- ; -- ; -- ;
-; sseg2[2] ; Output ; -- ; -- ; -- ; -- ;
-; sseg2[1] ; Output ; -- ; -- ; -- ; -- ;
-; sseg2[0] ; Output ; -- ; -- ; -- ; -- ;
-; sseg3[6] ; Output ; -- ; -- ; -- ; -- ;
-; sseg3[5] ; Output ; -- ; -- ; -- ; -- ;
-; sseg3[4] ; Output ; -- ; -- ; -- ; -- ;
-; sseg3[3] ; Output ; -- ; -- ; -- ; -- ;
-; sseg3[2] ; Output ; -- ; -- ; -- ; -- ;
-; sseg3[1] ; Output ; -- ; -- ; -- ; -- ;
-; sseg3[0] ; Output ; -- ; -- ; -- ; -- ;
-; sys_clk ; Input ; OFF ; OFF ; -- ; -- ;
-; sys_res ; Input ; OFF ; ON ; -- ; -- ;
-; bus_rx ; Input ; ON ; ON ; -- ; -- ;
-+----------+----------+---------------+---------------+-----------------------+-----+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------+
-; Pad To Core Delay Chain Fanout ;
-+---------------------------------------------------------------------------------------------------+-------------------+---------+
-; Source Pin / Fanout ; Pad To Core Index ; Setting ;
-+---------------------------------------------------------------------------------------------------+-------------------+---------+
-; sys_clk ; ; ;
-; sys_res ; ; ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[0] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[2] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[3] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[6] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[5] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[4] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[3] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[2] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[0] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[6] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[5] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[4] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[3] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[2] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[0] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[6] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[5] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[4] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[3] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[2] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[0] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[6] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[5] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[4] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[3] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[2] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[0] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[0] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[2] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[3] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[4] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[5] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[6] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[7] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[8] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[9] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[10] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[11] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[12] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[13] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[14] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[15] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[0] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[2] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[3] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[4] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[5] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[6] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[7] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[8] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[9] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[10] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[11] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[12] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[13] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[14] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[15] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[16] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[17] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[18] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[19] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[20] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[21] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[22] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[23] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[24] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[25] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[26] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[27] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[28] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[29] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[30] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[31] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[17] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[18] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[19] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[20] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[22] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[28] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[29] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[30] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[11] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|state ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[0] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[3] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[2] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[4] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[5] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[5] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[4] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[7] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[7] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[6] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[8] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[9] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[8] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[11] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[10] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[13] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[12] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[15] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[14] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[16] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[0] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[2] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[3] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.sel ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.byte_en[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[4] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[5] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[6] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[7] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[8] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[9] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[10] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[11] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[12] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[13] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[14] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[15] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.dmem_en ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[31] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[30] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[29] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[28] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[27] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[26] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[25] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[24] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[23] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[22] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[21] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[20] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[19] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[18] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[17] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[16] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[15] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[14] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|idle_sig ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.condition[0] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.condition[3] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.alu_jump ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.brpr ; 0 ; OFF ;
-; - execute_stage:exec_st|alu:alu_inst|\calc:cond_met~1 ; 1 ; ON ;
-; - decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.res_addr[2] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.wr_en ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[6] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg2 ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[6] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_detail[3] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[5] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[5] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[7] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[4] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[4] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[2] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[2] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[1] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[1] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[3] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[3] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[0] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[0] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[8] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[8] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[9] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[9] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[10] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[10] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[11] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[12] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[12] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[13] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[13] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[14] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[14] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[15] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[15] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_group.AND_OP ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg1 ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_group.JMP_OP ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_group.OR_OP ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_group.XOR_OP ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[19] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[18] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[20] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[17] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[17] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[21] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[23] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[24] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[22] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_detail[2] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.carry ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_detail[1] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[16] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[16] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_group.ADDSUB_OP ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[27] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[29] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[28] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[30] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[31] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[25] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[26] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[21] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[31] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_detail[4] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.daddr[0] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.daddr[2] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.daddr[3] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.daddr[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[6] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.displacement[4] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.displacement[31] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.displacement[9] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.displacement[7] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.displacement[6] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.displacement[5] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[5] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[7] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[4] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[2] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[3] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[0] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr_nxt[0]~1 ; 1 ; ON ;
-; - writeback_stage:writeback_st|extension_uart:uart|tx_rdy_int ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.POST_STOP ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.displacement[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_BIT ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_START ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[6]~0 ; 1 ; ON ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_STOP ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.IDLE ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[5]~2 ; 1 ; ON ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[7]~4 ; 1 ; ON ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[4]~6 ; 1 ; ON ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[2]~8 ; 1 ; ON ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[1]~10 ; 1 ; ON ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[3]~12 ; 1 ; ON ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[0]~14 ; 1 ; ON ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|bus_rx_int ; 1 ; ON ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|sync[1] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.saddr2[2] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.saddr2[0] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[4] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[6] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[3] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[5] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[2] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[4] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.saddr2[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[6] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[3] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[0] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.saddr1[0] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[5] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[2] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.saddr1[2] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[7] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[19] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[18] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[16] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[17] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[20] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[14] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[7] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[19] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[18] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[29] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[13] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[9] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[28] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[8] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[31] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[20] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[12] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[21] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[23] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[22] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[27] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[29] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[26] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[14] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[10] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[28] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[25] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[11] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[19] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[18] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[31] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[30] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[24] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[13] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[16] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[9] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[8] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[21] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[17] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[15] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[20] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[23] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[22] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[27] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[12] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[26] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[25] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[29] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[13] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[30] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[24] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[10] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[28] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[11] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[4] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[11] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[31] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[7] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[21] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[15] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[23] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[22] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[27] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[26] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[25] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[30] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[24] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[12] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[8] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[0] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[3] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[6] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.dmem_write_en ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[2] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[2] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[3] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[10] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[9] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[14] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[13] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[9] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.imm_set ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[4] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[6] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[3] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[0] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[12] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[5] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[2] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[6] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[5] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[10] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[11] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[15] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[7] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[14] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[19] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[18] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[13] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[16] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[9] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[8] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[17] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[20] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[4] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[12] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[6] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[3] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[0] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[5] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[2] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[29] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[1] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[28] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[10] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.data[12] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.data[13] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.data[14] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.data[15] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.data[19] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.data[18] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.data[20] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.data[17] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.data[21] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.data[23] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.data[24] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.data[22] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.data[16] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.data[27] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.data[29] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.data[28] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.data[30] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.data[31] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.data[25] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.data[26] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[31] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.data[8] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.data[9] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.data[10] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.data[11] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[11] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[21] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[15] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[23] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[22] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[27] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[26] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[25] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[30] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[24] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[7] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[10] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[9] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[8] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[7] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[6] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[5] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[4] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.data[6] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.data[4] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[2] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[3] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.data[5] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.data[7] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.data[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.data[2] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.data[0] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[9] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[1] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[8] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.data[3] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[10] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[0] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.wr_en ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|new_rx_data ; 1 ; ON ;
-; - decode_stage:decode_st|dec_op_inst.saddr1[3] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.saddr2[3] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.saddr1[1] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.brpr ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][11] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|sync[2] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_detail[5] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.res_addr[0] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.res_addr[1] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.res_addr[3] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][29] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][28] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][27] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][26] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][25] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][24] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][23] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][22] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][21] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][20] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][19] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][18] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][17] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][16] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][15] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][14] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][13] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][12] ; 0 ; OFF ;
-; bus_rx ; ; ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|sync[1] ; 1 ; ON ;
-+---------------------------------------------------------------------------------------------------+-------------------+---------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Control Signals ;
-+----------------------------------------------------------------------------------------------+---------------+---------+-----------------------------------------+--------+----------------------+------------------+
-; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
-+----------------------------------------------------------------------------------------------+---------------+---------+-----------------------------------------+--------+----------------------+------------------+
-; decode_stage:decode_st|decoder:decoder_inst|instr_s~10 ; LC_X36_Y12_N6 ; 10 ; Sync. load ; no ; -- ; -- ;
-; decode_stage:decode_st|rtw_rec_nxt.immediate[16]~28 ; LC_X36_Y12_N1 ; 9 ; Sync. clear ; no ; -- ; -- ;
-; execute_stage:exec_st|alu:alu_inst|calc~0 ; LC_X25_Y16_N7 ; 2 ; Clock enable ; no ; -- ; -- ;
-; execute_stage:exec_st|alu:alu_inst|pwr_en ; LC_X32_Y18_N0 ; 30 ; Clock enable ; no ; -- ; -- ;
-; fetch_stage:fetch_st|rom:instruction_ram|data_out[22] ; LC_X21_Y16_N1 ; 31 ; Sync. clear ; no ; -- ; -- ;
-; sys_clk ; PIN_152 ; 538 ; Clock ; yes ; Global Clock ; GCLK7 ;
-; sys_res ; PIN_42 ; 504 ; Async. clear, Async. load, Clock enable ; yes ; Global Clock ; GCLK3 ;
-; writeback_stage:writeback_st|dmem_we~0 ; LC_X22_Y14_N4 ; 16 ; Write enable ; no ; -- ; -- ;
-; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[6]~0 ; LC_X21_Y11_N3 ; 28 ; Clock enable ; no ; -- ; -- ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[4]~33 ; LC_X22_Y18_N2 ; 16 ; Sync. clear ; no ; -- ; -- ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|new_rx_data ; LC_X22_Y18_N9 ; 9 ; Clock enable ; no ; -- ; -- ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[7]~0 ; LC_X22_Y18_N9 ; 9 ; Clock enable ; no ; -- ; -- ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_BIT ; LC_X21_Y19_N3 ; 51 ; Sync. load ; no ; -- ; -- ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int~0 ; LC_X29_Y8_N2 ; 6 ; Clock enable ; no ; -- ; -- ;
-; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0]~0 ; LC_X35_Y13_N0 ; 31 ; Clock enable ; no ; -- ; -- ;
-; writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[15]~0 ; LC_X30_Y13_N6 ; 32 ; Clock enable ; no ; -- ; -- ;
-; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0]~1 ; LC_X35_Y13_N9 ; 32 ; Clock enable ; no ; -- ; -- ;
-; writeback_stage:writeback_st|reg_we~11 ; LC_X29_Y17_N6 ; 7 ; Write enable ; no ; -- ; -- ;
-+----------------------------------------------------------------------------------------------+---------------+---------+-----------------------------------------+--------+----------------------+------------------+
-
-
-+------------------------------------------------------------------------+
-; Global & Other Fast Signals ;
-+---------+----------+---------+----------------------+------------------+
-; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
-+---------+----------+---------+----------------------+------------------+
-; sys_clk ; PIN_152 ; 538 ; Global Clock ; GCLK7 ;
-; sys_res ; PIN_42 ; 504 ; Global Clock ; GCLK3 ;
-+---------+----------+---------+----------------------+------------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Non-Global High Fan-Out Signals ;
-+-----------------------------------------------------------------------------------------+---------+
-; Name ; Fan-Out ;
-+-----------------------------------------------------------------------------------------+---------+
-; execute_stage:exec_st|right_operand[0]~19 ; 104 ;
-; execute_stage:exec_st|right_operand[1]~15 ; 98 ;
-; writeback_stage:writeback_st|wb_reg.dmem_en ; 91 ;
-; execute_stage:exec_st|alu:alu_inst|Selector98~0 ; 89 ;
-; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; 78 ;
-; execute_stage:exec_st|right_operand[2]~13 ; 63 ;
-; execute_stage:exec_st|alu:alu_inst|Selector63~0 ; 60 ;
-; execute_stage:exec_st|left_operand[19]~3 ; 59 ;
-; decode_stage:decode_st|dec_op_inst.op_detail[3] ; 53 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_BIT ; 51 ;
-; writeback_stage:writeback_st|regfile_val[24]~50 ; 48 ;
-; execute_stage:exec_st|right_operand[3]~17 ; 48 ;
-; execute_stage:exec_st|right_operand[5]~3 ; 48 ;
-; execute_stage:exec_st|right_operand[5]~2 ; 48 ;
-; writeback_stage:writeback_st|wb_reg.address[3] ; 45 ;
-; fetch_stage:fetch_st|rom:instruction_ram|data_out[23] ; 41 ;
-; decode_stage:decode_st|dec_op_inst.op_detail[1] ; 41 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_STOP ; 35 ;
-; decode_stage:decode_st|dec_op_inst.op_group.OR_OP ; 34 ;
-; decode_stage:decode_st|dec_op_inst.op_group.XOR_OP ; 33 ;
-; decode_stage:decode_st|dec_op_inst.op_group.AND_OP ; 33 ;
-; writeback_stage:writeback_st|data_addr[12]~10 ; 32 ;
-; writeback_stage:writeback_st|data_addr[11]~9 ; 32 ;
-; writeback_stage:writeback_st|data_addr[10]~8 ; 32 ;
-; writeback_stage:writeback_st|data_addr[9]~7 ; 32 ;
-; writeback_stage:writeback_st|data_addr[8]~6 ; 32 ;
-; writeback_stage:writeback_st|data_addr[7]~5 ; 32 ;
-; writeback_stage:writeback_st|data_addr[6]~4 ; 32 ;
-; writeback_stage:writeback_st|data_addr[5]~3 ; 32 ;
-; writeback_stage:writeback_st|data_addr[4]~2 ; 32 ;
-; writeback_stage:writeback_st|data_addr[3]~1 ; 32 ;
-; writeback_stage:writeback_st|data_addr[2]~0 ; 32 ;
-; execute_stage:exec_st|alu:alu_inst|calc~1 ; 32 ;
-; execute_stage:exec_st|alu:alu_inst|Selector16~2 ; 32 ;
-; execute_stage:exec_st|alu:alu_inst|Selector16~1 ; 32 ;
-; decode_stage:decode_st|rtw_rec.rtw_reg1 ; 32 ;
-; writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[15]~0 ; 32 ;
-; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0]~1 ; 32 ;
-; fetch_stage:fetch_st|rom:instruction_ram|data_out[22] ; 31 ;
-; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0]~0 ; 31 ;
-; execute_stage:exec_st|alu:alu_inst|pwr_en ; 30 ;
-; execute_stage:exec_st|alu:alu_inst|pinc~0 ; 29 ;
-; fetch_stage:fetch_st|rom:instruction_ram|data_out[27] ; 28 ;
-; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[6]~0 ; 28 ;
-; decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP ; 27 ;
-; writeback_stage:writeback_st|extension_uart:uart|gread~0 ; 27 ;
-; writeback_stage:writeback_st|regfile_val[24]~51 ; 24 ;
-; decode_stage:decode_st|decoder:decoder_inst|instr_spl.bp~0 ; 23 ;
-; decode_stage:decode_st|dec_op_inst.displacement[31] ; 23 ;
-; fetch_stage:fetch_st|rom:instruction_ram|data_out[26] ; 23 ;
-+-----------------------------------------------------------------------------------------+---------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter RAM Summary ;
-+--------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M4Ks ; MIF ; Location ;
-+--------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 16 ; 32 ; 16 ; 32 ; yes ; no ; yes ; no ; 512 ; 16 ; 32 ; 16 ; 32 ; 512 ; 1 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; M4K_X33_Y17 ;
-; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 16 ; 32 ; 16 ; 32 ; yes ; no ; yes ; no ; 512 ; 16 ; 32 ; 16 ; 32 ; 512 ; 1 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; M4K_X33_Y18 ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 2048 ; 32 ; 2048 ; 32 ; yes ; no ; yes ; no ; 65536 ; 2048 ; 32 ; 2048 ; 32 ; 65536 ; 16 ; db/dt.ram0_r_w_ram_1e9198d1.hdl.mif ; M4K_X19_Y19, M4K_X33_Y13, M4K_X33_Y14, M4K_X33_Y16, M4K_X19_Y13, M4K_X19_Y16, M4K_X19_Y18, M4K_X19_Y11, M4K_X19_Y15, M4K_X19_Y14, M4K_X19_Y10, M4K_X33_Y11, M4K_X33_Y12, M4K_X33_Y15, M4K_X19_Y17, M4K_X19_Y12 ;
-+--------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.
-
-
-+------------------------------------------------------+
-; Interconnect Usage Summary ;
-+----------------------------+-------------------------+
-; Interconnect Resource Type ; Usage ;
-+----------------------------+-------------------------+
-; C4s ; 3,149 / 30,600 ( 10 % ) ;
-; Direct links ; 169 / 43,552 ( < 1 % ) ;
-; Global clocks ; 2 / 8 ( 25 % ) ;
-; LAB clocks ; 64 / 312 ( 21 % ) ;
-; LUT chains ; 152 / 10,854 ( 1 % ) ;
-; Local interconnects ; 3,313 / 43,552 ( 8 % ) ;
-; M4K buffers ; 96 / 1,872 ( 5 % ) ;
-; R4s ; 3,533 / 28,560 ( 12 % ) ;
-+----------------------------+-------------------------+
-
-
-+----------------------------------------------------------------------------+
-; LAB Logic Elements ;
-+--------------------------------------------+-------------------------------+
-; Number of Logic Elements (Average = 9.46) ; Number of LABs (Total = 174) ;
-+--------------------------------------------+-------------------------------+
-; 1 ; 4 ;
-; 2 ; 0 ;
-; 3 ; 2 ;
-; 4 ; 2 ;
-; 5 ; 1 ;
-; 6 ; 0 ;
-; 7 ; 2 ;
-; 8 ; 7 ;
-; 9 ; 7 ;
-; 10 ; 149 ;
-+--------------------------------------------+-------------------------------+
-
-
-+--------------------------------------------------------------------+
-; LAB-wide Signals ;
-+------------------------------------+-------------------------------+
-; LAB-wide Signals (Average = 1.83) ; Number of LABs (Total = 174) ;
-+------------------------------------+-------------------------------+
-; 1 Async. clear ; 126 ;
-; 1 Async. load ; 1 ;
-; 1 Clock ; 130 ;
-; 1 Clock enable ; 39 ;
-; 1 Sync. clear ; 4 ;
-; 1 Sync. load ; 5 ;
-; 2 Clock enables ; 14 ;
-+------------------------------------+-------------------------------+
-
-
-+------------------------------------------------------------------------------+
-; LAB Signals Sourced ;
-+----------------------------------------------+-------------------------------+
-; Number of Signals Sourced (Average = 10.30) ; Number of LABs (Total = 174) ;
-+----------------------------------------------+-------------------------------+
-; 0 ; 0 ;
-; 1 ; 4 ;
-; 2 ; 0 ;
-; 3 ; 2 ;
-; 4 ; 2 ;
-; 5 ; 1 ;
-; 6 ; 0 ;
-; 7 ; 2 ;
-; 8 ; 5 ;
-; 9 ; 7 ;
-; 10 ; 87 ;
-; 11 ; 30 ;
-; 12 ; 16 ;
-; 13 ; 6 ;
-; 14 ; 5 ;
-; 15 ; 3 ;
-; 16 ; 1 ;
-; 17 ; 3 ;
-+----------------------------------------------+-------------------------------+
-
-
-+---------------------------------------------------------------------------------+
-; LAB Signals Sourced Out ;
-+-------------------------------------------------+-------------------------------+
-; Number of Signals Sourced Out (Average = 7.25) ; Number of LABs (Total = 174) ;
-+-------------------------------------------------+-------------------------------+
-; 0 ; 0 ;
-; 1 ; 4 ;
-; 2 ; 1 ;
-; 3 ; 5 ;
-; 4 ; 9 ;
-; 5 ; 18 ;
-; 6 ; 26 ;
-; 7 ; 33 ;
-; 8 ; 30 ;
-; 9 ; 19 ;
-; 10 ; 21 ;
-; 11 ; 3 ;
-; 12 ; 1 ;
-; 13 ; 0 ;
-; 14 ; 1 ;
-; 15 ; 1 ;
-; 16 ; 2 ;
-+-------------------------------------------------+-------------------------------+
-
-
-+------------------------------------------------------------------------------+
-; LAB Distinct Inputs ;
-+----------------------------------------------+-------------------------------+
-; Number of Distinct Inputs (Average = 16.75) ; Number of LABs (Total = 174) ;
-+----------------------------------------------+-------------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 0 ;
-; 3 ; 3 ;
-; 4 ; 1 ;
-; 5 ; 2 ;
-; 6 ; 2 ;
-; 7 ; 6 ;
-; 8 ; 2 ;
-; 9 ; 6 ;
-; 10 ; 6 ;
-; 11 ; 6 ;
-; 12 ; 4 ;
-; 13 ; 4 ;
-; 14 ; 13 ;
-; 15 ; 10 ;
-; 16 ; 5 ;
-; 17 ; 4 ;
-; 18 ; 9 ;
-; 19 ; 12 ;
-; 20 ; 16 ;
-; 21 ; 35 ;
-; 22 ; 28 ;
-+----------------------------------------------+-------------------------------+
-
-
-+--------------------------------------------------------------------+
-; Fitter Device Options ;
-+----------------------------------------------+---------------------+
-; Option ; Setting ;
-+----------------------------------------------+---------------------+
-; Enable user-supplied start-up clock (CLKUSR) ; Off ;
-; Enable device-wide reset (DEV_CLRn) ; Off ;
-; Enable device-wide output enable (DEV_OE) ; Off ;
-; Enable INIT_DONE output ; Off ;
-; Configuration scheme ; Active Serial ;
-; Error detection CRC ; Off ;
-; ASDO,nCSO ; As input tri-stated ;
-; Reserve all unused pins ; As input tri-stated ;
-; Base pin-out file on sameframe device ; Off ;
-+----------------------------------------------+---------------------+
-
-
-+------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing Summary ;
-+-----------------+----------------------+-------------------+
-; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
-+-----------------+----------------------+-------------------+
-
-
-+------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing Details ;
-+-----------------+----------------------+-------------------+
-; Source Register ; Destination Register ; Delay Added in ns ;
-+-----------------+----------------------+-------------------+
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Info: *******************************************************************
-Info: Running Quartus II Fitter
- Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
- Info: Processing started: Sun Dec 19 20:36:27 2010
-Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off dt -c dt
-Info: Selected device EP1C12Q240C8 for design "dt"
-Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning: Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
-Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
- Info: Device EP1C6Q240C8 is compatible
-Info: Fitter converted 2 user pins into dedicated programming pins
- Info: Pin ~nCSO~ is reserved at location 24
- Info: Pin ~ASDO~ is reserved at location 37
-Critical Warning: No exact pin location assignment(s) for 29 pins of 32 total pins
- Info: Pin sseg0[6] not assigned to an exact location on the device
- Info: Pin sseg0[5] not assigned to an exact location on the device
- Info: Pin sseg0[4] not assigned to an exact location on the device
- Info: Pin sseg0[3] not assigned to an exact location on the device
- Info: Pin sseg0[2] not assigned to an exact location on the device
- Info: Pin sseg0[1] not assigned to an exact location on the device
- Info: Pin sseg0[0] not assigned to an exact location on the device
- Info: Pin sseg1[6] not assigned to an exact location on the device
- Info: Pin sseg1[5] not assigned to an exact location on the device
- Info: Pin sseg1[4] not assigned to an exact location on the device
- Info: Pin sseg1[3] not assigned to an exact location on the device
- Info: Pin sseg1[2] not assigned to an exact location on the device
- Info: Pin sseg1[1] not assigned to an exact location on the device
- Info: Pin sseg1[0] not assigned to an exact location on the device
- Info: Pin sseg2[6] not assigned to an exact location on the device
- Info: Pin sseg2[5] not assigned to an exact location on the device
- Info: Pin sseg2[4] not assigned to an exact location on the device
- Info: Pin sseg2[3] not assigned to an exact location on the device
- Info: Pin sseg2[2] not assigned to an exact location on the device
- Info: Pin sseg2[1] not assigned to an exact location on the device
- Info: Pin sseg2[0] not assigned to an exact location on the device
- Info: Pin sseg3[6] not assigned to an exact location on the device
- Info: Pin sseg3[5] not assigned to an exact location on the device
- Info: Pin sseg3[4] not assigned to an exact location on the device
- Info: Pin sseg3[3] not assigned to an exact location on the device
- Info: Pin sseg3[2] not assigned to an exact location on the device
- Info: Pin sseg3[1] not assigned to an exact location on the device
- Info: Pin sseg3[0] not assigned to an exact location on the device
- Info: Pin bus_rx not assigned to an exact location on the device
-Info: Timing-driven compilation is using the Classic Timing Analyzer
-Warning: Classic Timing Analyzer will not be available in a future release of the Quartus II software. Use the TimeQuest Timing Analyzer to run timing analysis on your design. Convert all the project settings and the timing constraints to TimeQuest Timing Analyzer equivalents.
-Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
-Extra Info: Performing register packing on registers with non-logic cell location assignments
-Extra Info: Completed register packing on registers with non-logic cell location assignments
-Info: Completed User Assigned Global Signals Promotion Operation
-Info: DQS I/O pins require 0 global routing resources
-Info: Automatically promoted signal "sys_clk" to use Global clock in PIN 152
-Info: Automatically promoted some destinations of signal "sys_res" to use Global clock
- Info: Destination "execute_stage:exec_st|alu:alu_inst|\calc:cond_met~1" may be non-global or may not use global clock
- Info: Destination "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|new_rx_data" may be non-global or may not use global clock
- Info: Destination "fetch_stage:fetch_st|instr_r_addr_nxt[0]~1" may be non-global or may not use global clock
- Info: Destination "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[6]~0" may be non-global or may not use global clock
- Info: Destination "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[5]~2" may be non-global or may not use global clock
- Info: Destination "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[7]~4" may be non-global or may not use global clock
- Info: Destination "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[4]~6" may be non-global or may not use global clock
- Info: Destination "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[2]~8" may be non-global or may not use global clock
- Info: Destination "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[1]~10" may be non-global or may not use global clock
- Info: Destination "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[3]~12" may be non-global or may not use global clock
- Info: Limited to 10 non-global destinations
-Info: Pin "sys_res" drives global clock, but is not placed in a dedicated clock pin position
-Info: Completed Auto Global Promotion Operation
-Info: Starting register packing
-Extra Info: Started Fast Input/Output/OE register processing
-Extra Info: Finished Fast Input/Output/OE register processing
-Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
-Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density
-Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
-Info: Finished register packing
-Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
- Info: Number of I/O pins in group: 29 (unused VREF, 3.3V VCCIO, 1 input, 28 output, 0 bidirectional)
- Info: I/O standards used: 3.3-V LVCMOS.
-Info: I/O bank details before I/O pin placement
- Info: Statistics of I/O banks
- Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 3 total pin(s) used -- 41 pins available
- Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 42 pins available
- Info: I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 2 total pin(s) used -- 43 pins available
- Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 42 pins available
-Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
-Info: Fitter preparation operations ending: elapsed time is 00:00:02
-Info: Fitter placement preparation operations beginning
-Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
-Info: Fitter placement operations beginning
-Info: Fitter placement was successful
-Info: Fitter placement operations ending: elapsed time is 00:00:02
-Info: Estimated most critical path is register to register delay of 23.818 ns
- Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X35_Y17; Fanout = 2; REG Node = 'writeback_stage:writeback_st|wb_reg.address[16]'
- Info: 2: + IC(0.860 ns) + CELL(0.114 ns) = 0.974 ns; Loc. = LAB_X36_Y17; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~3'
- Info: 3: + IC(1.490 ns) + CELL(0.114 ns) = 2.578 ns; Loc. = LAB_X29_Y17; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~4'
- Info: 4: + IC(0.063 ns) + CELL(0.590 ns) = 3.231 ns; Loc. = LAB_X29_Y17; Fanout = 4; COMB Node = 'writeback_stage:writeback_st|Equal0~8'
- Info: 5: + IC(0.211 ns) + CELL(0.442 ns) = 3.884 ns; Loc. = LAB_X29_Y17; Fanout = 27; COMB Node = 'writeback_stage:writeback_st|extension_uart:uart|gread~0'
- Info: 6: + IC(1.564 ns) + CELL(0.590 ns) = 6.038 ns; Loc. = LAB_X27_Y12; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|regfile_val[17]~96'
- Info: 7: + IC(1.633 ns) + CELL(0.114 ns) = 7.785 ns; Loc. = LAB_X22_Y15; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|regfile_val[17]~97'
- Info: 8: + IC(1.653 ns) + CELL(0.114 ns) = 9.552 ns; Loc. = LAB_X27_Y12; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|regfile_val[17]~98'
- Info: 9: + IC(0.361 ns) + CELL(0.292 ns) = 10.205 ns; Loc. = LAB_X27_Y12; Fanout = 6; COMB Node = 'writeback_stage:writeback_st|regfile_val[17]~99'
- Info: 10: + IC(1.177 ns) + CELL(0.114 ns) = 11.496 ns; Loc. = LAB_X29_Y12; Fanout = 1; COMB Node = 'execute_stage:exec_st|right_operand[17]~64'
- Info: 11: + IC(0.361 ns) + CELL(0.292 ns) = 12.149 ns; Loc. = LAB_X29_Y12; Fanout = 5; COMB Node = 'execute_stage:exec_st|right_operand[17]~65'
- Info: 12: + IC(1.889 ns) + CELL(0.114 ns) = 14.152 ns; Loc. = LAB_X36_Y11; Fanout = 3; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add0~176'
- Info: 13: + IC(1.431 ns) + CELL(0.575 ns) = 16.158 ns; Loc. = LAB_X31_Y13; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add0~78COUT1_259'
- Info: 14: + IC(0.000 ns) + CELL(0.080 ns) = 16.238 ns; Loc. = LAB_X31_Y13; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add0~73COUT1_261'
- Info: 15: + IC(0.000 ns) + CELL(0.608 ns) = 16.846 ns; Loc. = LAB_X31_Y13; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add0~66'
- Info: 16: + IC(1.416 ns) + CELL(0.590 ns) = 18.852 ns; Loc. = LAB_X23_Y12; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector12~2'
- Info: 17: + IC(0.063 ns) + CELL(0.590 ns) = 19.505 ns; Loc. = LAB_X23_Y12; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector12~5'
- Info: 18: + IC(0.752 ns) + CELL(0.590 ns) = 20.847 ns; Loc. = LAB_X23_Y11; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Equal0~1'
- Info: 19: + IC(1.563 ns) + CELL(0.590 ns) = 23.000 ns; Loc. = LAB_X28_Y18; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Equal0~2'
- Info: 20: + IC(0.211 ns) + CELL(0.607 ns) = 23.818 ns; Loc. = LAB_X28_Y18; Fanout = 1; REG Node = 'execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero'
- Info: Total cell delay = 7.120 ns ( 29.89 % )
- Info: Total interconnect delay = 16.698 ns ( 70.11 % )
-Info: Fitter routing operations beginning
-Info: Router estimated average interconnect usage is 9% of the available device resources
- Info: Router estimated peak interconnect usage is 35% of the available device resources in the region that extends from location X21_Y14 to location X31_Y27
-Info: Fitter routing operations ending: elapsed time is 00:00:05
-Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
- Info: Optimizations that may affect the design's routability were skipped
- Info: Optimizations that may affect the design's timing were skipped
-Info: Completed Fixed Delay Chain Operation
-Info: Started post-fitting delay annotation
-Info: Delay annotation completed successfully
-Info: Completed Auto Delay Chain Operation
-Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
-Info: Quartus II Fitter was successful. 0 errors, 3 warnings
- Info: Peak virtual memory: 272 megabytes
- Info: Processing ended: Sun Dec 19 20:36:45 2010
- Info: Elapsed time: 00:00:18
- Info: Total CPU time (on all processors): 00:00:16
-
-
+++ /dev/null
-Fitter Status : Successful - Sun Dec 19 20:36:44 2010
-Quartus II Version : 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition
-Revision Name : dt
-Top-level Entity Name : core_top
-Family : Cyclone
-Device : EP1C12Q240C8
-Timing Models : Final
-Total logic elements : 1,646 / 12,060 ( 14 % )
-Total pins : 32 / 173 ( 18 % )
-Total virtual pins : 0
-Total memory bits : 66,560 / 239,616 ( 28 % )
-Total PLLs : 0 / 2 ( 0 % )
+++ /dev/null
-Flow report for dt
-Sun Dec 19 20:36:51 2010
-Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Flow Summary
- 3. Flow Settings
- 4. Flow Non-Default Global Settings
- 5. Flow Elapsed Time
- 6. Flow OS Summary
- 7. Flow Log
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2010 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Altera Program License
-Subscription Agreement, Altera MegaCore Function License
-Agreement, or other applicable license agreement, including,
-without limitation, that your use is for the sole purpose of
-programming logic devices manufactured by Altera and sold by
-Altera or its authorized distributors. Please refer to the
-applicable agreement for further details.
-
-
-
-+-------------------------------------------------------------------------+
-; Flow Summary ;
-+-------------------------+-----------------------------------------------+
-; Flow Status ; Successful - Sun Dec 19 20:36:51 2010 ;
-; Quartus II Version ; 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition ;
-; Revision Name ; dt ;
-; Top-level Entity Name ; core_top ;
-; Family ; Cyclone ;
-; Device ; EP1C12Q240C8 ;
-; Timing Models ; Final ;
-; Met timing requirements ; Yes ;
-; Total logic elements ; 1,646 / 12,060 ( 14 % ) ;
-; Total pins ; 32 / 173 ( 18 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 66,560 / 239,616 ( 28 % ) ;
-; Total PLLs ; 0 / 2 ( 0 % ) ;
-+-------------------------+-----------------------------------------------+
-
-
-+-----------------------------------------+
-; Flow Settings ;
-+-------------------+---------------------+
-; Option ; Setting ;
-+-------------------+---------------------+
-; Start date & time ; 12/19/2010 20:36:12 ;
-; Main task ; Compilation ;
-; Revision Name ; dt ;
-+-------------------+---------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings ;
-+-------------------------------------+--------------------------------+---------------+-------------+------------+
-; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
-+-------------------------------------+--------------------------------+---------------+-------------+------------+
-; COMPILER_SIGNATURE_ID ; 99901343620.129278737205529 ; -- ; -- ; -- ;
-; MISC_FILE ; /homes/burban/dt/dt.dpf ; -- ; -- ; -- ;
-; MISC_FILE ; /homes/c0726283/calu/dt/dt.dpf ; -- ; -- ; -- ;
-; PARTITION_COLOR ; 16764057 ; -- ; core_top ; Top ;
-; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; core_top ; Top ;
-; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; core_top ; Top ;
-; TOP_LEVEL_ENTITY ; core_top ; dt ; -- ; -- ;
-+-------------------------------------+--------------------------------+---------------+-------------+------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time ;
-+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:13 ; 1.0 ; -- ; 00:00:12 ;
-; Fitter ; 00:00:17 ; 1.0 ; -- ; 00:00:15 ;
-; Assembler ; 00:00:01 ; 1.0 ; -- ; 00:00:01 ;
-; Classic Timing Analyzer ; 00:00:01 ; 1.0 ; -- ; 00:00:01 ;
-; Total ; 00:00:32 ; -- ; -- ; 00:00:29 ;
-+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------+
-; Flow OS Summary ;
-+-------------------------+------------------+----------------+------------+----------------+
-; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
-+-------------------------+------------------+----------------+------------+----------------+
-; Analysis & Synthesis ; ubuntu ; Ubuntu 10.04.1 ; 10 ; x86_64 ;
-; Fitter ; ubuntu ; Ubuntu 10.04.1 ; 10 ; x86_64 ;
-; Assembler ; ubuntu ; Ubuntu 10.04.1 ; 10 ; x86_64 ;
-; Classic Timing Analyzer ; ubuntu ; Ubuntu 10.04.1 ; 10 ; x86_64 ;
-+-------------------------+------------------+----------------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off dt -c dt
-quartus_fit --read_settings_files=off --write_settings_files=off dt -c dt
-quartus_asm --read_settings_files=off --write_settings_files=off dt -c dt
-quartus_tan --read_settings_files=off --write_settings_files=off dt -c dt --timing_analysis_only
-
-
-
+++ /dev/null
-Analysis & Synthesis report for dt
-Sun Dec 19 20:36:26 2010
-Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Analysis & Synthesis Summary
- 3. Analysis & Synthesis Settings
- 4. Parallel Compilation
- 5. Analysis & Synthesis Source Files Read
- 6. Analysis & Synthesis Resource Usage Summary
- 7. Analysis & Synthesis Resource Utilization by Entity
- 8. Analysis & Synthesis RAM Summary
- 9. State Machine - |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state
- 10. State Machine - |core_top|decode_stage:decode_st|dec_op_inst.op_group
- 11. Registers Removed During Synthesis
- 12. Removed Registers Triggering Further Register Optimizations
- 13. General Register Statistics
- 14. Inverted Register Statistics
- 15. Registers Packed Into Inferred Megafunctions
- 16. Multiplexer Restructuring Statistics (Restructuring Performed)
- 17. Source assignments for writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated
- 18. Source assignments for decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated
- 19. Source assignments for decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2|altsyncram_emk1:auto_generated
- 20. Parameter Settings for User Entity Instance: fetch_stage:fetch_st
- 21. Parameter Settings for User Entity Instance: fetch_stage:fetch_st|rom:instruction_ram
- 22. Parameter Settings for User Entity Instance: decode_stage:decode_st
- 23. Parameter Settings for User Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram
- 24. Parameter Settings for User Entity Instance: execute_stage:exec_st
- 25. Parameter Settings for User Entity Instance: execute_stage:exec_st|extension_gpm:gpmp_inst
- 26. Parameter Settings for User Entity Instance: writeback_stage:writeback_st
- 27. Parameter Settings for User Entity Instance: writeback_stage:writeback_st|r_w_ram:data_ram
- 28. Parameter Settings for User Entity Instance: writeback_stage:writeback_st|extension_uart:uart
- 29. Parameter Settings for User Entity Instance: writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst
- 30. Parameter Settings for User Entity Instance: writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst
- 31. Parameter Settings for User Entity Instance: writeback_stage:writeback_st|extension_7seg:sseg
- 32. Parameter Settings for Inferred Entity Instance: writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0
- 33. Parameter Settings for Inferred Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1
- 34. Parameter Settings for Inferred Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2
- 35. altsyncram Parameter Settings by Entity Instance
- 36. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst"
- 37. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:xor_inst"
- 38. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:or_inst"
- 39. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:and_inst"
- 40. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:add_inst"
- 41. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst"
- 42. Port Connectivity Checks: "execute_stage:exec_st"
- 43. Port Connectivity Checks: "decode_stage:decode_st|decoder:decoder_inst"
- 44. Analysis & Synthesis Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2010 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Altera Program License
-Subscription Agreement, Altera MegaCore Function License
-Agreement, or other applicable license agreement, including,
-without limitation, that your use is for the sole purpose of
-programming logic devices manufactured by Altera and sold by
-Altera or its authorized distributors. Please refer to the
-applicable agreement for further details.
-
-
-
-+-----------------------------------------------------------------------------+
-; Analysis & Synthesis Summary ;
-+-----------------------------+-----------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Sun Dec 19 20:36:26 2010 ;
-; Quartus II Version ; 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition ;
-; Revision Name ; dt ;
-; Top-level Entity Name ; core_top ;
-; Family ; Cyclone ;
-; Total logic elements ; 1,879 ;
-; Total pins ; 32 ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 66,560 ;
-; Total PLLs ; 0 ;
-+-----------------------------+-----------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings ;
-+----------------------------------------------------------------------------+--------------------+--------------------+
-; Option ; Setting ; Default Value ;
-+----------------------------------------------------------------------------+--------------------+--------------------+
-; Device ; EP1C12Q240C8 ; ;
-; Top-level entity name ; core_top ; dt ;
-; Family name ; Cyclone ; Stratix II ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Restructure Multiplexers ; Auto ; Auto ;
-; Create Debugging Nodes for IP Cores ; Off ; Off ;
-; Preserve fewer node names ; On ; On ;
-; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
-; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
-; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
-; State Machine Processing ; Auto ; Auto ;
-; Safe State Machine ; Off ; Off ;
-; Extract Verilog State Machines ; On ; On ;
-; Extract VHDL State Machines ; On ; On ;
-; Ignore Verilog initial constructs ; Off ; Off ;
-; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
-; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
-; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
-; Parallel Synthesis ; On ; On ;
-; NOT Gate Push-Back ; On ; On ;
-; Power-Up Don't Care ; On ; On ;
-; Remove Redundant Logic Cells ; Off ; Off ;
-; Remove Duplicate Registers ; On ; On ;
-; Ignore CARRY Buffers ; Off ; Off ;
-; Ignore CASCADE Buffers ; Off ; Off ;
-; Ignore GLOBAL Buffers ; Off ; Off ;
-; Ignore ROW GLOBAL Buffers ; Off ; Off ;
-; Ignore LCELL Buffers ; Off ; Off ;
-; Ignore SOFT Buffers ; On ; On ;
-; Limit AHDL Integers to 32 Bits ; Off ; Off ;
-; Optimization Technique ; Balanced ; Balanced ;
-; Carry Chain Length ; 70 ; 70 ;
-; Auto Carry Chains ; On ; On ;
-; Auto Open-Drain Pins ; On ; On ;
-; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
-; Auto ROM Replacement ; On ; On ;
-; Auto RAM Replacement ; On ; On ;
-; Auto Shift Register Replacement ; Auto ; Auto ;
-; Auto Clock Enable Replacement ; On ; On ;
-; Strict RAM Replacement ; Off ; Off ;
-; Allow Synchronous Control Signals ; On ; On ;
-; Force Use of Synchronous Clear Signals ; Off ; Off ;
-; Auto RAM Block Balancing ; On ; On ;
-; Auto RAM to Logic Cell Conversion ; Off ; Off ;
-; Auto Resource Sharing ; Off ; Off ;
-; Allow Any RAM Size For Recognition ; Off ; Off ;
-; Allow Any ROM Size For Recognition ; Off ; Off ;
-; Allow Any Shift Register Size For Recognition ; Off ; Off ;
-; Use LogicLock Constraints during Resource Balancing ; On ; On ;
-; Ignore translate_off and synthesis_off directives ; Off ; Off ;
-; Report Parameter Settings ; On ; On ;
-; Report Source Assignments ; On ; On ;
-; Report Connectivity Checks ; On ; On ;
-; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
-; Synchronization Register Chain Length ; 2 ; 2 ;
-; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
-; HDL message level ; Level2 ; Level2 ;
-; Suppress Register Optimization Related Messages ; Off ; Off ;
-; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
-; Clock MUX Protection ; On ; On ;
-; Block Design Naming ; Auto ; Auto ;
-; Synthesis Effort ; Auto ; Auto ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
-; Analysis & Synthesis Message Level ; Medium ; Medium ;
-; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
-; Resource Aware Inference For Block RAM ; On ; On ;
-; Synthesis Seed ; 1 ; 1 ;
-+----------------------------------------------------------------------------+--------------------+--------------------+
-
-
-Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
-+-------------------------------------+
-; Parallel Compilation ;
-+----------------------------+--------+
-; Processors ; Number ;
-+----------------------------+--------+
-; Number detected on machine ; 2 ;
-; Maximum allowed ; 1 ;
-+----------------------------+--------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read ;
-+--------------------------------------+-----------------+-------------------------------------------------------+---------------------------------------------------------------------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
-+--------------------------------------+-----------------+-------------------------------------------------------+---------------------------------------------------------------------+
-; ../cpu/src/rom.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/rom.vhd ;
-; ../cpu/src/rom_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/rom_b.vhd ;
-; ../cpu/src/extension_7seg_pkg.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/extension_7seg_pkg.vhd ;
-; ../cpu/src/extension_7seg_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/extension_7seg_b.vhd ;
-; ../cpu/src/extension_7seg.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/extension_7seg.vhd ;
-; ../cpu/src/rs232_rx_arc.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/rs232_rx_arc.vhd ;
-; ../cpu/src/rs232_rx.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/rs232_rx.vhd ;
-; ../cpu/src/writeback_stage_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/writeback_stage_b.vhd ;
-; ../cpu/src/writeback_stage.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/writeback_stage.vhd ;
-; ../cpu/src/rs232_tx_arc.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/rs232_tx_arc.vhd ;
-; ../cpu/src/rs232_tx.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/rs232_tx.vhd ;
-; ../cpu/src/r_w_ram_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/r_w_ram_b.vhd ;
-; ../cpu/src/r_w_ram.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/r_w_ram.vhd ;
-; ../cpu/src/r2_w_ram_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/r2_w_ram_b.vhd ;
-; ../cpu/src/r2_w_ram.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/r2_w_ram.vhd ;
-; ../cpu/src/mem_pkg.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/mem_pkg.vhd ;
-; ../cpu/src/fetch_stage_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/fetch_stage_b.vhd ;
-; ../cpu/src/fetch_stage.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/fetch_stage.vhd ;
-; ../cpu/src/extension_uart_pkg.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/extension_uart_pkg.vhd ;
-; ../cpu/src/extension_uart_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/extension_uart_b.vhd ;
-; ../cpu/src/extension_uart.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/extension_uart.vhd ;
-; ../cpu/src/extension_pkg.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/extension_pkg.vhd ;
-; ../cpu/src/extension_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/extension_b.vhd ;
-; ../cpu/src/extension.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/extension.vhd ;
-; ../cpu/src/execute_stage_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/execute_stage_b.vhd ;
-; ../cpu/src/execute_stage.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/execute_stage.vhd ;
-; ../cpu/src/exec_op.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/exec_op.vhd ;
-; ../cpu/src/decoder_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/decoder_b.vhd ;
-; ../cpu/src/decoder.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/decoder.vhd ;
-; ../cpu/src/decode_stage_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/decode_stage_b.vhd ;
-; ../cpu/src/decode_stage.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/decode_stage.vhd ;
-; ../cpu/src/core_top.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/core_top.vhd ;
-; ../cpu/src/core_pkg.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/core_pkg.vhd ;
-; ../cpu/src/common_pkg.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/common_pkg.vhd ;
-; ../cpu/src/alu_pkg.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/alu_pkg.vhd ;
-; ../cpu/src/alu_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/alu_b.vhd ;
-; ../cpu/src/alu.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/alu.vhd ;
-; ../cpu/src/exec_op/xor_op_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/exec_op/xor_op_b.vhd ;
-; ../cpu/src/exec_op/shift_op_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/exec_op/shift_op_b.vhd ;
-; ../cpu/src/exec_op/or_op_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/exec_op/or_op_b.vhd ;
-; ../cpu/src/exec_op/and_op_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/exec_op/and_op_b.vhd ;
-; ../cpu/src/exec_op/add_op_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/exec_op/add_op_b.vhd ;
-; altsyncram.tdf ; yes ; Megafunction ; /opt/altera/10.0sp1/quartus/libraries/megafunctions/altsyncram.tdf ;
-; db/altsyncram_grk1.tdf ; yes ; Auto-Generated Megafunction ; /home/stefan/processor/calu/dt/db/altsyncram_grk1.tdf ;
-; db/dt.ram0_r_w_ram_1e9198d1.hdl.mif ; yes ; Auto-Generated Auto-Found Memory Initialization File ; /home/stefan/processor/calu/dt/db/dt.ram0_r_w_ram_1e9198d1.hdl.mif ;
-; db/altsyncram_emk1.tdf ; yes ; Auto-Generated Megafunction ; /home/stefan/processor/calu/dt/db/altsyncram_emk1.tdf ;
-; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; yes ; Auto-Generated Auto-Found Memory Initialization File ; /home/stefan/processor/calu/dt/db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ;
-+--------------------------------------+-----------------+-------------------------------------------------------+---------------------------------------------------------------------+
-
-
-+-------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary ;
-+---------------------------------------------+---------+
-; Resource ; Usage ;
-+---------------------------------------------+---------+
-; Total logic elements ; 1879 ;
-; -- Combinational with no register ; 1359 ;
-; -- Register only ; 259 ;
-; -- Combinational with a register ; 261 ;
-; ; ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 827 ;
-; -- 3 input functions ; 474 ;
-; -- 2 input functions ; 292 ;
-; -- 1 input functions ; 27 ;
-; -- 0 input functions ; 0 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 1703 ;
-; -- arithmetic mode ; 176 ;
-; -- qfbk mode ; 0 ;
-; -- register cascade mode ; 0 ;
-; -- synchronous clear/load mode ; 57 ;
-; -- asynchronous clear/load mode ; 492 ;
-; ; ;
-; Total registers ; 520 ;
-; Total logic cells in carry chains ; 184 ;
-; I/O pins ; 32 ;
-; Total memory bits ; 66560 ;
-; Maximum fan-out node ; sys_clk ;
-; Maximum fan-out ; 616 ;
-; Total fan-out ; 8075 ;
-; Average fan-out ; 4.02 ;
-+---------------------------------------------+---------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity ;
-+----------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------------------------+--------------+
-; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
-+----------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------------------------+--------------+
-; |core_top ; 1879 (0) ; 520 ; 66560 ; 32 ; 0 ; 1359 (0) ; 259 (0) ; 261 (0) ; 184 (0) ; 0 (0) ; |core_top ; ;
-; |decode_stage:decode_st| ; 220 (153) ; 106 ; 1024 ; 0 ; 0 ; 114 (47) ; 54 (54) ; 52 (52) ; 11 (11) ; 0 (0) ; |core_top|decode_stage:decode_st ; ;
-; |decoder:decoder_inst| ; 67 (67) ; 0 ; 0 ; 0 ; 0 ; 67 (67) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|decoder:decoder_inst ; ;
-; |r2_w_ram:register_ram| ; 0 (0) ; 0 ; 1024 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram ; ;
-; |altsyncram:ram_rtl_1| ; 0 (0) ; 0 ; 512 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1 ; ;
-; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 512 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated ; ;
-; |altsyncram:ram_rtl_2| ; 0 (0) ; 0 ; 512 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2 ; ;
-; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 512 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2|altsyncram_emk1:auto_generated ; ;
-; |execute_stage:exec_st| ; 940 (175) ; 71 ; 0 ; 0 ; 0 ; 869 (136) ; 23 (4) ; 48 (35) ; 108 (0) ; 0 (0) ; |core_top|execute_stage:exec_st ; ;
-; |alu:alu_inst| ; 703 (387) ; 0 ; 0 ; 0 ; 0 ; 703 (387) ; 0 (0) ; 0 (0) ; 78 (44) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst ; ;
-; |exec_op:add_inst| ; 67 (67) ; 0 ; 0 ; 0 ; 0 ; 67 (67) ; 0 (0) ; 0 (0) ; 34 (34) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:add_inst ; ;
-; |exec_op:shift_inst| ; 249 (249) ; 0 ; 0 ; 0 ; 0 ; 249 (249) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst ; ;
-; |extension_gpm:gpmp_inst| ; 62 (62) ; 32 ; 0 ; 0 ; 0 ; 30 (30) ; 19 (19) ; 13 (13) ; 30 (30) ; 0 (0) ; |core_top|execute_stage:exec_st|extension_gpm:gpmp_inst ; ;
-; |fetch_stage:fetch_st| ; 55 (34) ; 29 ; 0 ; 0 ; 0 ; 26 (23) ; 11 (11) ; 18 (0) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st ; ;
-; |rom:instruction_ram| ; 21 (21) ; 18 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 18 (18) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st|rom:instruction_ram ; ;
-; |writeback_stage:writeback_st| ; 664 (247) ; 314 ; 65536 ; 0 ; 0 ; 350 (183) ; 171 (45) ; 143 (19) ; 65 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st ; ;
-; |extension_7seg:sseg| ; 48 (48) ; 47 ; 0 ; 0 ; 0 ; 1 (1) ; 18 (18) ; 29 (29) ; 0 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_7seg:sseg ; ;
-; |extension_uart:uart| ; 369 (145) ; 203 ; 0 ; 0 ; 0 ; 166 (39) ; 108 (98) ; 95 (8) ; 65 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart ; ;
-; |rs232_rx:rs232_rx_inst| ; 160 (160) ; 73 ; 0 ; 0 ; 0 ; 87 (87) ; 10 (10) ; 63 (63) ; 48 (48) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst ; ;
-; |rs232_tx:rs232_tx_inst| ; 64 (64) ; 24 ; 0 ; 0 ; 0 ; 40 (40) ; 0 (0) ; 24 (24) ; 17 (17) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst ; ;
-; |r_w_ram:data_ram| ; 0 (0) ; 0 ; 65536 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|r_w_ram:data_ram ; ;
-; |altsyncram:ram_rtl_0| ; 0 (0) ; 0 ; 65536 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0 ; ;
-; |altsyncram_grk1:auto_generated| ; 0 (0) ; 0 ; 65536 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated ; ;
-+----------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------------------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis RAM Summary ;
-+--------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+--------------------------------------+
-; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
-+--------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+--------------------------------------+
-; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 16 ; 32 ; 16 ; 32 ; 512 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ;
-; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 16 ; 32 ; 16 ; 32 ; 512 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 2048 ; 32 ; 2048 ; 32 ; 65536 ; db/dt.ram0_r_w_ram_1e9198d1.hdl.mif ;
-+--------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+--------------------------------------+
-
-
-Encoding Type: One-Hot
-+---------------------------------------------------------------------------------------------------------+
-; State Machine - |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state ;
-+------------------+-----------------+-----------------+----------------+------------------+--------------+
-; Name ; state.POST_STOP ; state.READ_STOP ; state.READ_BIT ; state.READ_START ; state.IDLE ;
-+------------------+-----------------+-----------------+----------------+------------------+--------------+
-; state.IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; state.READ_START ; 0 ; 0 ; 0 ; 1 ; 1 ;
-; state.READ_BIT ; 0 ; 0 ; 1 ; 0 ; 1 ;
-; state.READ_STOP ; 0 ; 1 ; 0 ; 0 ; 1 ;
-; state.POST_STOP ; 1 ; 0 ; 0 ; 0 ; 1 ;
-+------------------+-----------------+-----------------+----------------+------------------+--------------+
-
-
-Encoding Type: One-Hot
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; State Machine - |core_top|decode_stage:decode_st|dec_op_inst.op_group ;
-+--------------------------------+--------------------------------+-----------------------------+------------------------------+-------------------------------+-----------------------------+----------------------------+-----------------------------+--------------------------------+
-; Name ; dec_op_inst.op_group.JMP_ST_OP ; dec_op_inst.op_group.JMP_OP ; dec_op_inst.op_group.LDST_OP ; dec_op_inst.op_group.SHIFT_OP ; dec_op_inst.op_group.XOR_OP ; dec_op_inst.op_group.OR_OP ; dec_op_inst.op_group.AND_OP ; dec_op_inst.op_group.ADDSUB_OP ;
-+--------------------------------+--------------------------------+-----------------------------+------------------------------+-------------------------------+-----------------------------+----------------------------+-----------------------------+--------------------------------+
-; dec_op_inst.op_group.ADDSUB_OP ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; dec_op_inst.op_group.AND_OP ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ;
-; dec_op_inst.op_group.OR_OP ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;
-; dec_op_inst.op_group.XOR_OP ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ;
-; dec_op_inst.op_group.SHIFT_OP ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ;
-; dec_op_inst.op_group.LDST_OP ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;
-; dec_op_inst.op_group.JMP_OP ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
-; dec_op_inst.op_group.JMP_ST_OP ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
-+--------------------------------+--------------------------------+-----------------------------+------------------------------+-------------------------------+-----------------------------+----------------------------+-----------------------------+--------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Registers Removed During Synthesis ;
-+------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+
-; Register name ; Reason for Removal ;
-+------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+
-; decode_stage:decode_st|dec_op_inst.prog_cnt[11..31] ; Stuck at GND due to stuck port data_in ;
-; fetch_stage:fetch_st|rom:instruction_ram|data_out[2,8] ; Stuck at GND due to stuck port data_in ;
-; writeback_stage:writeback_st|wb_reg.hword ; Stuck at GND due to stuck port data_in ;
-; writeback_stage:writeback_st|wb_reg.byte_s ; Stuck at GND due to stuck port data_in ;
-; writeback_stage:writeback_st|wb_reg.address[0..1] ; Lost fanout ;
-; decode_stage:decode_st|dec_op_inst.displacement[2,8] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][29] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][28] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][27] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][26] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][25] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][24] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][23] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][22] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][21] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][20] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][19] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][18] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][17] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][16] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][15] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][14] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][13] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][12] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][11] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][10] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][9] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][8] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][7] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][6] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][5] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][4] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][3] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][2] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][1] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][0] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][29] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][28] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][27] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][26] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][25] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][24] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][23] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][22] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][21] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][20] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][19] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][18] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][17] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][16] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][15] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][14] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][13] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][12] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][11] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][10] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][9] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][8] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][7] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][6] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][5] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][4] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][3] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][2] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][1] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][0] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][29] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][28] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][27] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][26] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][25] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][24] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][23] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][22] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][21] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][20] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][19] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][18] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][17] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][16] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][15] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][14] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][13] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][12] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][11] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][10] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][9] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][8] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][7] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][6] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][5] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][4] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][3] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][2] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][1] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][0] ; Lost fanout ;
-; writeback_stage:writeback_st|wb_reg.byte_en[0..3] ; Merged with writeback_stage:writeback_st|wb_reg.dmem_en ;
-; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.byte_en[0] ; Merged with writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.byte_en[1] ;
-; writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[8..30] ; Merged with writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[31] ;
-; decode_stage:decode_st|dec_op_inst.op_detail[0] ; Merged with decode_stage:decode_st|rtw_rec.imm_set ;
-; fetch_stage:fetch_st|rom:instruction_ram|data_out[9,28..30] ; Merged with fetch_stage:fetch_st|rom:instruction_ram|data_out[31] ;
-; fetch_stage:fetch_st|rom:instruction_ram|data_out[0,10..14,18] ; Merged with fetch_stage:fetch_st|rom:instruction_ram|data_out[22] ;
-; fetch_stage:fetch_st|rom:instruction_ram|data_out[3] ; Merged with fetch_stage:fetch_st|rom:instruction_ram|data_out[4] ;
-; decode_stage:decode_st|rtw_rec.immediate[23..27] ; Merged with decode_stage:decode_st|rtw_rec.immediate[31] ;
-; decode_stage:decode_st|rtw_rec.immediate[16] ; Merged with decode_stage:decode_st|rtw_rec.immediate[17] ;
-; decode_stage:decode_st|rtw_rec.immediate[7] ; Merged with decode_stage:decode_st|rtw_rec.immediate[11] ;
-; decode_stage:decode_st|dec_op_inst.condition[1..2] ; Merged with decode_stage:decode_st|dec_op_inst.condition[3] ;
-; decode_stage:decode_st|dec_op_inst.displacement[15..30] ; Merged with decode_stage:decode_st|dec_op_inst.displacement[31] ;
-; decode_stage:decode_st|dec_op_inst.displacement[0,10..13] ; Merged with decode_stage:decode_st|dec_op_inst.displacement[14] ;
-; decode_stage:decode_st|dec_op_inst.displacement[3] ; Merged with decode_stage:decode_st|dec_op_inst.displacement[4] ;
-; writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[31] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.oflo ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.sign ; Lost fanout ;
-; decode_stage:decode_st|dec_op_inst.displacement[14] ; Merged with decode_stage:decode_st|dec_op_inst.displacement[31] ;
-; fetch_stage:fetch_st|instr_r_addr[11..31] ; Lost fanout ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[17..31] ; Lost fanout ;
-; Total Number of Removed Registers = 231 ; ;
-+------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Removed Registers Triggering Further Register Optimizations ;
-+---------------------------------------------------------------+---------------------------+----------------------------------------------------------------+
-; Register name ; Reason for Removal ; Registers Removed due to This Register ;
-+---------------------------------------------------------------+---------------------------+----------------------------------------------------------------+
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][29] ; Lost Fanouts ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.oflo, ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.sign ;
-; fetch_stage:fetch_st|rom:instruction_ram|data_out[8] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[8] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|rom:instruction_ram|data_out[2] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[2] ;
-; ; due to stuck port data_in ; ;
-+---------------------------------------------------------------+---------------------------+----------------------------------------------------------------+
-
-
-+------------------------------------------------------+
-; General Register Statistics ;
-+----------------------------------------------+-------+
-; Statistic ; Value ;
-+----------------------------------------------+-------+
-; Total registers ; 520 ;
-; Number of registers using Synchronous Clear ; 25 ;
-; Number of registers using Synchronous Load ; 40 ;
-; Number of registers using Asynchronous Clear ; 487 ;
-; Number of registers using Asynchronous Load ; 5 ;
-; Number of registers using Clock Enable ; 177 ;
-; Number of registers using Preset ; 0 ;
-+----------------------------------------------+-------+
-
-
-+-----------------------------------------------------------------------------------------------+
-; Inverted Register Statistics ;
-+-------------------------------------------------------------------------------------+---------+
-; Inverted Register ; Fan out ;
-+-------------------------------------------------------------------------------------+---------+
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; 1 ;
-; writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[1] ; 4 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[1] ; 2 ;
-; writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[4] ; 4 ;
-; writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[5] ; 4 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[5] ; 2 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[4] ; 2 ;
-; writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[7] ; 4 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[7] ; 2 ;
-; writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[8] ; 4 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[8] ; 2 ;
-; decode_stage:decode_st|dec_op_inst.condition[0] ; 1 ;
-; decode_stage:decode_st|dec_op_inst.condition[3] ; 1 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; 4 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|sync[2] ; 13 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|sync[1] ; 1 ;
-; Total number of inverted registers = 26 ; ;
-+-------------------------------------------------------------------------------------+---------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------+
-; Registers Packed Into Inferred Megafunctions ;
-+------------------------------------------------------------+------------------------------------------------------+------+
-; Register Name ; Megafunction ; Type ;
-+------------------------------------------------------------+------------------------------------------------------+------+
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[0] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[1] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[2] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[3] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[4] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[5] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[6] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[7] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[8] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[9] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[10] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[11] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[12] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[13] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[14] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[15] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[16] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[17] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[18] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[19] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[20] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[22] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[24] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[25] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[26] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[27] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[28] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[29] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[30] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[31] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[0] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[1] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[2] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[3] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[4] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[5] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[6] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[7] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[8] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[9] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[10] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[11] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[12] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[13] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[14] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[15] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[16] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[17] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[18] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[19] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[20] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[21] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[22] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[23] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[24] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[25] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[26] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[27] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[28] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[29] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[30] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[31] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[0] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[1] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[2] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[3] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[4] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[5] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[6] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[7] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[8] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[9] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[10] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[11] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[12] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[13] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[14] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[15] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[16] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[17] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[18] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[19] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[20] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[21] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[22] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[23] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[24] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[25] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[26] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[27] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[28] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[29] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[30] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[31] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-+------------------------------------------------------------+------------------------------------------------------+------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Multiplexer Restructuring Statistics (Restructuring Performed) ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------+
-; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------+
-; 3:1 ; 27 bits ; 54 LEs ; 27 LEs ; 27 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[17] ;
-; 3:1 ; 6 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |core_top|decode_stage:decode_st|dec_op_inst.displacement[7] ;
-; 4:1 ; 18 bits ; 36 LEs ; 36 LEs ; 0 LEs ; Yes ; |core_top|writeback_stage:writeback_st|wb_reg.address[19] ;
-; 5:1 ; 21 bits ; 63 LEs ; 42 LEs ; 21 LEs ; Yes ; |core_top|fetch_stage:fetch_st|instr_r_addr[30] ;
-; 18:1 ; 3 bits ; 36 LEs ; 3 LEs ; 33 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[1] ;
-; 5:1 ; 16 bits ; 48 LEs ; 16 LEs ; 32 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[4] ;
-; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[4] ;
-; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; No ; |core_top|execute_stage:exec_st|condition[0] ;
-; 3:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; No ; |core_top|decode_stage:decode_st|decoder:decoder_inst|instr_spl.reg_src2_addr[1] ;
-; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; No ; |core_top|decode_stage:decode_st|decoder:decoder_inst|\split_instr:instr_s.op_group.JMP_ST_OP ;
-; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |core_top|decode_stage:decode_st|decoder:decoder_inst|instr_spl.immediate[8] ;
-; 3:1 ; 32 bits ; 64 LEs ; 64 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|left_operand[19] ;
-; 4:1 ; 32 bits ; 64 LEs ; 64 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|right_operand[5] ;
-; 4:1 ; 12 bits ; 24 LEs ; 24 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|alu:alu_inst|Selector63 ;
-; 5:1 ; 11 bits ; 33 LEs ; 22 LEs ; 11 LEs ; No ; |core_top|fetch_stage:fetch_st|instr_r_addr_nxt[0] ;
-; 4:1 ; 11 bits ; 22 LEs ; 11 LEs ; 11 LEs ; No ; |core_top|execute_stage:exec_st|alu:alu_inst|Selector98 ;
-; 32:1 ; 3 bits ; 63 LEs ; 6 LEs ; 57 LEs ; No ; |core_top|decode_stage:decode_st|decoder:decoder_inst|instr_spl.reg_src1_addr[0] ;
-; 6:1 ; 9 bits ; 36 LEs ; 27 LEs ; 9 LEs ; No ; |core_top|decode_stage:decode_st|decoder:decoder_inst|instr_s ;
-; 7:1 ; 3 bits ; 12 LEs ; 6 LEs ; 6 LEs ; No ; |core_top|decode_stage:decode_st|decoder:decoder_inst|instr_spl.immediate[12] ;
-; 10:1 ; 24 bits ; 144 LEs ; 96 LEs ; 48 LEs ; No ; |core_top|writeback_stage:writeback_st|regfile_val[24] ;
-; 8:1 ; 2 bits ; 10 LEs ; 4 LEs ; 6 LEs ; No ; |core_top|decode_stage:decode_st|decoder:decoder_inst|instr_spl.immediate[3] ;
-; 11:1 ; 8 bits ; 56 LEs ; 48 LEs ; 8 LEs ; No ; |core_top|writeback_stage:writeback_st|regfile_val[0] ;
-; 10:1 ; 18 bits ; 108 LEs ; 108 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|alu:alu_inst|Selector16 ;
-; 11:1 ; 4 bits ; 28 LEs ; 24 LEs ; 4 LEs ; No ; |core_top|execute_stage:exec_st|alu:alu_inst|Selector3 ;
-; 11:1 ; 4 bits ; 28 LEs ; 24 LEs ; 4 LEs ; No ; |core_top|execute_stage:exec_st|alu:alu_inst|Selector28 ;
-; 12:1 ; 2 bits ; 16 LEs ; 14 LEs ; 2 LEs ; No ; |core_top|execute_stage:exec_st|alu:alu_inst|Selector1 ;
-; 12:1 ; 2 bits ; 16 LEs ; 14 LEs ; 2 LEs ; No ; |core_top|execute_stage:exec_st|alu:alu_inst|Selector29 ;
-; 14:1 ; 3 bits ; 27 LEs ; 21 LEs ; 6 LEs ; No ; |core_top|decode_stage:decode_st|decoder:decoder_inst|instr_s ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated ;
-+---------------------------------+--------------------+------+------------------------------------------------------------+
-; Assignment ; Value ; From ; To ;
-+---------------------------------+--------------------+------+------------------------------------------------------------+
-; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
-+---------------------------------+--------------------+------+------------------------------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated ;
-+---------------------------------+--------------------+------+-----------------------------------------------------------+
-; Assignment ; Value ; From ; To ;
-+---------------------------------+--------------------+------+-----------------------------------------------------------+
-; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
-+---------------------------------+--------------------+------+-----------------------------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2|altsyncram_emk1:auto_generated ;
-+---------------------------------+--------------------+------+-----------------------------------------------------------+
-; Assignment ; Value ; From ; To ;
-+---------------------------------+--------------------+------+-----------------------------------------------------------+
-; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
-+---------------------------------+--------------------+------+-----------------------------------------------------------+
-
-
-+-------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: fetch_stage:fetch_st ;
-+----------------+-------+------------------------------------------+
-; Parameter Name ; Value ; Type ;
-+----------------+-------+------------------------------------------+
-; reset_value ; '0' ; Enumerated ;
-; logic_act ; '1' ; Enumerated ;
-+----------------+-------+------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: fetch_stage:fetch_st|rom:instruction_ram ;
-+----------------+-------+--------------------------------------------------------------+
-; Parameter Name ; Value ; Type ;
-+----------------+-------+--------------------------------------------------------------+
-; addr_width ; 11 ; Signed Integer ;
-; data_width ; 32 ; Signed Integer ;
-+----------------+-------+--------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: decode_stage:decode_st ;
-+----------------+-------+--------------------------------------------+
-; Parameter Name ; Value ; Type ;
-+----------------+-------+--------------------------------------------+
-; reset_value ; '0' ; Enumerated ;
-; logic_act ; '1' ; Enumerated ;
-+----------------+-------+--------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram ;
-+----------------+-------+------------------------------------------------------------------+
-; Parameter Name ; Value ; Type ;
-+----------------+-------+------------------------------------------------------------------+
-; addr_width ; 4 ; Signed Integer ;
-; data_width ; 32 ; Signed Integer ;
-+----------------+-------+------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+--------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: execute_stage:exec_st ;
-+----------------+-------+-------------------------------------------+
-; Parameter Name ; Value ; Type ;
-+----------------+-------+-------------------------------------------+
-; reset_value ; '0' ; Enumerated ;
-+----------------+-------+-------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+--------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: execute_stage:exec_st|extension_gpm:gpmp_inst ;
-+----------------+-------+-------------------------------------------------------------------+
-; Parameter Name ; Value ; Type ;
-+----------------+-------+-------------------------------------------------------------------+
-; reset_value ; '0' ; Enumerated ;
-+----------------+-------+-------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: writeback_stage:writeback_st ;
-+----------------+-------+--------------------------------------------------+
-; Parameter Name ; Value ; Type ;
-+----------------+-------+--------------------------------------------------+
-; reset_value ; '0' ; Enumerated ;
-; logic_act ; '1' ; Enumerated ;
-+----------------+-------+--------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+--------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: writeback_stage:writeback_st|r_w_ram:data_ram ;
-+----------------+-------+-------------------------------------------------------------------+
-; Parameter Name ; Value ; Type ;
-+----------------+-------+-------------------------------------------------------------------+
-; addr_width ; 11 ; Signed Integer ;
-; data_width ; 32 ; Signed Integer ;
-+----------------+-------+-------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-----------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: writeback_stage:writeback_st|extension_uart:uart ;
-+----------------+-------+----------------------------------------------------------------------+
-; Parameter Name ; Value ; Type ;
-+----------------+-------+----------------------------------------------------------------------+
-; reset_value ; '0' ; Enumerated ;
-+----------------+-------+----------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+----------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst ;
-+----------------+-------+---------------------------------------------------------------------------------------------+
-; Parameter Name ; Value ; Type ;
-+----------------+-------+---------------------------------------------------------------------------------------------+
-; reset_value ; '0' ; Enumerated ;
-+----------------+-------+---------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+----------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst ;
-+----------------+-------+---------------------------------------------------------------------------------------------+
-; Parameter Name ; Value ; Type ;
-+----------------+-------+---------------------------------------------------------------------------------------------+
-; reset_value ; '0' ; Enumerated ;
-; sync_stages ; 2 ; Signed Integer ;
-+----------------+-------+---------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-----------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: writeback_stage:writeback_st|extension_7seg:sseg ;
-+----------------+-------+----------------------------------------------------------------------+
-; Parameter Name ; Value ; Type ;
-+----------------+-------+----------------------------------------------------------------------+
-; reset_value ; '0' ; Enumerated ;
-+----------------+-------+----------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for Inferred Entity Instance: writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0 ;
-+------------------------------------+-------------------------------------+------------------------------------------+
-; Parameter Name ; Value ; Type ;
-+------------------------------------+-------------------------------------+------------------------------------------+
-; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
-; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
-; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
-; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
-; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
-; WIDTH_BYTEENA ; 1 ; Untyped ;
-; OPERATION_MODE ; DUAL_PORT ; Untyped ;
-; WIDTH_A ; 32 ; Untyped ;
-; WIDTHAD_A ; 11 ; Untyped ;
-; NUMWORDS_A ; 2048 ; Untyped ;
-; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
-; ADDRESS_ACLR_A ; NONE ; Untyped ;
-; OUTDATA_ACLR_A ; NONE ; Untyped ;
-; WRCONTROL_ACLR_A ; NONE ; Untyped ;
-; INDATA_ACLR_A ; NONE ; Untyped ;
-; BYTEENA_ACLR_A ; NONE ; Untyped ;
-; WIDTH_B ; 32 ; Untyped ;
-; WIDTHAD_B ; 11 ; Untyped ;
-; NUMWORDS_B ; 2048 ; Untyped ;
-; INDATA_REG_B ; CLOCK1 ; Untyped ;
-; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
-; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
-; ADDRESS_REG_B ; CLOCK0 ; Untyped ;
-; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
-; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
-; INDATA_ACLR_B ; NONE ; Untyped ;
-; WRCONTROL_ACLR_B ; NONE ; Untyped ;
-; ADDRESS_ACLR_B ; NONE ; Untyped ;
-; OUTDATA_ACLR_B ; NONE ; Untyped ;
-; RDCONTROL_ACLR_B ; NONE ; Untyped ;
-; BYTEENA_ACLR_B ; NONE ; Untyped ;
-; WIDTH_BYTEENA_A ; 1 ; Untyped ;
-; WIDTH_BYTEENA_B ; 1 ; Untyped ;
-; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
-; BYTE_SIZE ; 8 ; Untyped ;
-; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ; Untyped ;
-; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
-; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
-; INIT_FILE ; db/dt.ram0_r_w_ram_1e9198d1.hdl.mif ; Untyped ;
-; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
-; MAXIMUM_DEPTH ; 0 ; Untyped ;
-; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
-; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
-; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
-; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
-; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
-; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
-; ENABLE_ECC ; FALSE ; Untyped ;
-; DEVICE_FAMILY ; Cyclone ; Untyped ;
-; CBXI_PARAMETER ; altsyncram_grk1 ; Untyped ;
-+------------------------------------+-------------------------------------+------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+--------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for Inferred Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1 ;
-+------------------------------------+--------------------------------------+----------------------------------------+
-; Parameter Name ; Value ; Type ;
-+------------------------------------+--------------------------------------+----------------------------------------+
-; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
-; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
-; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
-; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
-; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
-; WIDTH_BYTEENA ; 1 ; Untyped ;
-; OPERATION_MODE ; DUAL_PORT ; Untyped ;
-; WIDTH_A ; 32 ; Untyped ;
-; WIDTHAD_A ; 4 ; Untyped ;
-; NUMWORDS_A ; 16 ; Untyped ;
-; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
-; ADDRESS_ACLR_A ; NONE ; Untyped ;
-; OUTDATA_ACLR_A ; NONE ; Untyped ;
-; WRCONTROL_ACLR_A ; NONE ; Untyped ;
-; INDATA_ACLR_A ; NONE ; Untyped ;
-; BYTEENA_ACLR_A ; NONE ; Untyped ;
-; WIDTH_B ; 32 ; Untyped ;
-; WIDTHAD_B ; 4 ; Untyped ;
-; NUMWORDS_B ; 16 ; Untyped ;
-; INDATA_REG_B ; CLOCK1 ; Untyped ;
-; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
-; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
-; ADDRESS_REG_B ; CLOCK0 ; Untyped ;
-; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
-; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
-; INDATA_ACLR_B ; NONE ; Untyped ;
-; WRCONTROL_ACLR_B ; NONE ; Untyped ;
-; ADDRESS_ACLR_B ; NONE ; Untyped ;
-; OUTDATA_ACLR_B ; NONE ; Untyped ;
-; RDCONTROL_ACLR_B ; NONE ; Untyped ;
-; BYTEENA_ACLR_B ; NONE ; Untyped ;
-; WIDTH_BYTEENA_A ; 1 ; Untyped ;
-; WIDTH_BYTEENA_B ; 1 ; Untyped ;
-; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
-; BYTE_SIZE ; 8 ; Untyped ;
-; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ; Untyped ;
-; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
-; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
-; INIT_FILE ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; Untyped ;
-; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
-; MAXIMUM_DEPTH ; 0 ; Untyped ;
-; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
-; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
-; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
-; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
-; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
-; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
-; ENABLE_ECC ; FALSE ; Untyped ;
-; DEVICE_FAMILY ; Cyclone ; Untyped ;
-; CBXI_PARAMETER ; altsyncram_emk1 ; Untyped ;
-+------------------------------------+--------------------------------------+----------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+--------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for Inferred Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2 ;
-+------------------------------------+--------------------------------------+----------------------------------------+
-; Parameter Name ; Value ; Type ;
-+------------------------------------+--------------------------------------+----------------------------------------+
-; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
-; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
-; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
-; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
-; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
-; WIDTH_BYTEENA ; 1 ; Untyped ;
-; OPERATION_MODE ; DUAL_PORT ; Untyped ;
-; WIDTH_A ; 32 ; Untyped ;
-; WIDTHAD_A ; 4 ; Untyped ;
-; NUMWORDS_A ; 16 ; Untyped ;
-; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
-; ADDRESS_ACLR_A ; NONE ; Untyped ;
-; OUTDATA_ACLR_A ; NONE ; Untyped ;
-; WRCONTROL_ACLR_A ; NONE ; Untyped ;
-; INDATA_ACLR_A ; NONE ; Untyped ;
-; BYTEENA_ACLR_A ; NONE ; Untyped ;
-; WIDTH_B ; 32 ; Untyped ;
-; WIDTHAD_B ; 4 ; Untyped ;
-; NUMWORDS_B ; 16 ; Untyped ;
-; INDATA_REG_B ; CLOCK1 ; Untyped ;
-; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
-; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
-; ADDRESS_REG_B ; CLOCK0 ; Untyped ;
-; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
-; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
-; INDATA_ACLR_B ; NONE ; Untyped ;
-; WRCONTROL_ACLR_B ; NONE ; Untyped ;
-; ADDRESS_ACLR_B ; NONE ; Untyped ;
-; OUTDATA_ACLR_B ; NONE ; Untyped ;
-; RDCONTROL_ACLR_B ; NONE ; Untyped ;
-; BYTEENA_ACLR_B ; NONE ; Untyped ;
-; WIDTH_BYTEENA_A ; 1 ; Untyped ;
-; WIDTH_BYTEENA_B ; 1 ; Untyped ;
-; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
-; BYTE_SIZE ; 8 ; Untyped ;
-; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ; Untyped ;
-; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
-; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
-; INIT_FILE ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; Untyped ;
-; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
-; MAXIMUM_DEPTH ; 0 ; Untyped ;
-; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
-; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
-; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
-; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
-; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
-; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
-; ENABLE_ECC ; FALSE ; Untyped ;
-; DEVICE_FAMILY ; Cyclone ; Untyped ;
-; CBXI_PARAMETER ; altsyncram_emk1 ; Untyped ;
-+------------------------------------+--------------------------------------+----------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+----------------------------------------------------------------------------------------------------------------+
-; altsyncram Parameter Settings by Entity Instance ;
-+-------------------------------------------+--------------------------------------------------------------------+
-; Name ; Value ;
-+-------------------------------------------+--------------------------------------------------------------------+
-; Number of entity instances ; 3 ;
-; Entity Instance ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0 ;
-; -- OPERATION_MODE ; DUAL_PORT ;
-; -- WIDTH_A ; 32 ;
-; -- NUMWORDS_A ; 2048 ;
-; -- OUTDATA_REG_A ; UNREGISTERED ;
-; -- WIDTH_B ; 32 ;
-; -- NUMWORDS_B ; 2048 ;
-; -- ADDRESS_REG_B ; CLOCK0 ;
-; -- OUTDATA_REG_B ; UNREGISTERED ;
-; -- RAM_BLOCK_TYPE ; AUTO ;
-; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ;
-; Entity Instance ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1 ;
-; -- OPERATION_MODE ; DUAL_PORT ;
-; -- WIDTH_A ; 32 ;
-; -- NUMWORDS_A ; 16 ;
-; -- OUTDATA_REG_A ; UNREGISTERED ;
-; -- WIDTH_B ; 32 ;
-; -- NUMWORDS_B ; 16 ;
-; -- ADDRESS_REG_B ; CLOCK0 ;
-; -- OUTDATA_REG_B ; UNREGISTERED ;
-; -- RAM_BLOCK_TYPE ; AUTO ;
-; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ;
-; Entity Instance ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2 ;
-; -- OPERATION_MODE ; DUAL_PORT ;
-; -- WIDTH_A ; 32 ;
-; -- NUMWORDS_A ; 16 ;
-; -- OUTDATA_REG_A ; UNREGISTERED ;
-; -- WIDTH_B ; 32 ;
-; -- NUMWORDS_B ; 16 ;
-; -- ADDRESS_REG_B ; CLOCK0 ;
-; -- OUTDATA_REG_B ; UNREGISTERED ;
-; -- RAM_BLOCK_TYPE ; AUTO ;
-; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ;
-+-------------------------------------------+--------------------------------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst" ;
-+------------------------+--------+----------+-------------------------------------------------------------------------------------+
-; Port ; Type ; Severity ; Details ;
-+------------------------+--------+----------+-------------------------------------------------------------------------------------+
-; alu_result.status.zero ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; alu_result.status.sign ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; alu_result.alu_jump ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; alu_result.brpr ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; alu_result.reg_op ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; alu_result.mem_op ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; alu_result.mem_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-+------------------------+--------+----------+-------------------------------------------------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:xor_inst" ;
-+------------------------+--------+----------+-------------------------------------------------------------------------------------+
-; Port ; Type ; Severity ; Details ;
-+------------------------+--------+----------+-------------------------------------------------------------------------------------+
-; alu_result.status.zero ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; alu_result.status.sign ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; alu_result.alu_jump ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; alu_result.brpr ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; alu_result.reg_op ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; alu_result.mem_op ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; alu_result.mem_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-+------------------------+--------+----------+-------------------------------------------------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:or_inst" ;
-+------------------------+--------+----------+-------------------------------------------------------------------------------------+
-; Port ; Type ; Severity ; Details ;
-+------------------------+--------+----------+-------------------------------------------------------------------------------------+
-; alu_result.status.zero ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; alu_result.status.sign ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; alu_result.alu_jump ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; alu_result.brpr ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; alu_result.reg_op ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; alu_result.mem_op ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; alu_result.mem_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-+------------------------+--------+----------+-------------------------------------------------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:and_inst" ;
-+------------------------+--------+----------+-------------------------------------------------------------------------------------+
-; Port ; Type ; Severity ; Details ;
-+------------------------+--------+----------+-------------------------------------------------------------------------------------+
-; alu_result.status.zero ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; alu_result.status.sign ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; alu_result.alu_jump ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; alu_result.brpr ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; alu_result.reg_op ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; alu_result.mem_op ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; alu_result.mem_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-+------------------------+--------+----------+-------------------------------------------------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:add_inst" ;
-+------------------------+--------+----------+-------------------------------------------------------------------------------------+
-; Port ; Type ; Severity ; Details ;
-+------------------------+--------+----------+-------------------------------------------------------------------------------------+
-; alu_result.status.zero ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; alu_result.status.sign ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; alu_result.alu_jump ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; alu_result.brpr ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; alu_result.reg_op ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; alu_result.mem_op ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; alu_result.mem_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-+------------------------+--------+----------+-------------------------------------------------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst" ;
-+--------------------+--------+----------+-------------------------------------------------------------------------------------+
-; Port ; Type ; Severity ; Details ;
-+--------------------+--------+----------+-------------------------------------------------------------------------------------+
-; alu_state.reg_op ; Input ; Info ; Stuck at GND ;
-; alu_state.mem_op ; Input ; Info ; Stuck at GND ;
-; alu_state.mem_en ; Input ; Info ; Stuck at GND ;
-; alu_state.hw_op ; Input ; Info ; Stuck at GND ;
-; alu_state.byte_op ; Input ; Info ; Stuck at GND ;
-; alu_state.sign_xt ; Input ; Info ; Stuck at GND ;
-; alu_result.sign_xt ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-+--------------------+--------+----------+-------------------------------------------------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "execute_stage:exec_st" ;
-+--------------+--------+----------+-------------------------------------------------------------------------------------+
-; Port ; Type ; Severity ; Details ;
-+--------------+--------+----------+-------------------------------------------------------------------------------------+
-; ext_data_out ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-+--------------+--------+----------+-------------------------------------------------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "decode_stage:decode_st|decoder:decoder_inst" ;
-+--------------------+--------+----------+-------------------------------------------------------------------------------------+
-; Port ; Type ; Severity ; Details ;
-+--------------------+--------+----------+-------------------------------------------------------------------------------------+
-; instr_spl.jmptype ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; instr_spl.high_low ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; instr_spl.fill ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; instr_spl.signext ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-+--------------------+--------+----------+-------------------------------------------------------------------------------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus II Analysis & Synthesis
- Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
- Info: Processing started: Sun Dec 19 20:36:12 2010
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dt -c dt
-Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/rom.vhd
- Info: Found entity 1: rom
-Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/rom_b.vhd
- Info: Found design unit 1: rom-behaviour
-Info: Found 2 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/extension_7seg_pkg.vhd
- Info: Found design unit 1: extension_7seg_pkg
- Info: Found design unit 2: extension_7seg_pkg-body
-Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/extension_7seg_b.vhd
- Info: Found design unit 1: extension_7seg-behav
-Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/extension_7seg.vhd
- Info: Found entity 1: extension_7seg
-Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/rs232_rx_arc.vhd
- Info: Found design unit 1: rs232_rx-beh
-Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/rs232_rx.vhd
- Info: Found entity 1: rs232_rx
-Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/writeback_stage_b.vhd
- Info: Found design unit 1: writeback_stage-behav
-Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/writeback_stage.vhd
- Info: Found entity 1: writeback_stage
-Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/rw_r_ram_b.vhd
- Info: Found design unit 1: rw_r_ram-behaviour
-Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/rw_r_ram.vhd
- Info: Found entity 1: rw_r_ram
-Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/rs232_tx_arc.vhd
- Info: Found design unit 1: rs232_tx-beh
-Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/rs232_tx.vhd
- Info: Found entity 1: rs232_tx
-Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/r_w_ram_b.vhd
- Info: Found design unit 1: r_w_ram-behaviour
-Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/r_w_ram.vhd
- Info: Found entity 1: r_w_ram
-Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/r2_w_ram_b.vhd
- Info: Found design unit 1: r2_w_ram-behaviour
-Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/r2_w_ram.vhd
- Info: Found entity 1: r2_w_ram
-Info: Found 3 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/pipeline_tb.vhd
- Info: Found design unit 1: pipeline_tb-behavior
- Info: Found design unit 2: pipeline_conf_beh
- Info: Found entity 1: pipeline_tb
-Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/mem_pkg.vhd
- Info: Found design unit 1: mem_pkg
-Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/fetch_stage_b.vhd
- Info: Found design unit 1: fetch_stage-behav
-Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/fetch_stage.vhd
- Info: Found entity 1: fetch_stage
-Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/extension_uart_pkg.vhd
- Info: Found design unit 1: extension_uart_pkg
-Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/extension_uart_b.vhd
- Info: Found design unit 1: extension_uart-behav
-Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/extension_uart.vhd
- Info: Found entity 1: extension_uart
-Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/extension_pkg.vhd
- Info: Found design unit 1: extension_pkg
-Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/extension_b.vhd
- Info: Found design unit 1: extension_gpm-behav
-Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/extension.vhd
- Info: Found entity 1: extension_gpm
-Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/execute_stage_b.vhd
- Info: Found design unit 1: execute_stage-behav
-Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/execute_stage.vhd
- Info: Found entity 1: execute_stage
-Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/exec_op.vhd
- Info: Found entity 1: exec_op
-Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/decoder_b.vhd
- Info: Found design unit 1: decoder-behav_d
-Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/decoder.vhd
- Info: Found entity 1: decoder
-Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/decode_stage_b.vhd
- Info: Found design unit 1: decode_stage-behav
-Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/decode_stage.vhd
- Info: Found entity 1: decode_stage
-Info: Found 2 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/core_top.vhd
- Info: Found design unit 1: core_top-behav
- Info: Found entity 1: core_top
-Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/core_pkg.vhd
- Info: Found design unit 1: core_pkg
-Info: Found 2 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/common_pkg.vhd
- Info: Found design unit 1: common_pkg
- Info: Found design unit 2: common_pkg-body
-Info: Found 2 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/alu_pkg.vhd
- Info: Found design unit 1: alu_pkg
- Info: Found design unit 2: alu_pkg-body
-Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/alu_b.vhd
- Info: Found design unit 1: alu-behaviour
-Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/alu.vhd
- Info: Found entity 1: alu
-Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/exec_op/xor_op_b.vhd
- Info: Found design unit 1: exec_op-xor_op
-Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/exec_op/shift_op_b.vhd
- Info: Found design unit 1: exec_op-shift_op
-Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/exec_op/or_op_b.vhd
- Info: Found design unit 1: exec_op-or_op
-Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/exec_op/and_op_b.vhd
- Info: Found design unit 1: exec_op-and_op
-Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/exec_op/add_op_b.vhd
- Info: Found design unit 1: exec_op-add_op
-Info: Elaborating entity "core_top" for the top level hierarchy
-Warning (10036): Verilog HDL or VHDL warning at core_top.vhd(31): object "jump_result" assigned a value but never read
-Warning (10541): VHDL Signal Declaration warning at core_top.vhd(59): used implicit default value for signal "gpm_in_pin" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
-Warning (10036): Verilog HDL or VHDL warning at core_top.vhd(60): object "gpm_out_pin" assigned a value but never read
-Warning (10036): Verilog HDL or VHDL warning at core_top.vhd(63): object "vers" assigned a value but never read
-Info: Elaborating entity "fetch_stage" for hierarchy "fetch_stage:fetch_st"
-Warning (10541): VHDL Signal Declaration warning at fetch_stage_b.vhd(11): used implicit default value for signal "instr_w_addr" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
-Warning (10541): VHDL Signal Declaration warning at fetch_stage_b.vhd(14): used implicit default value for signal "instr_we" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
-Warning (10541): VHDL Signal Declaration warning at fetch_stage_b.vhd(15): used implicit default value for signal "instr_wr_data" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
-Info: Elaborating entity "rom" for hierarchy "fetch_stage:fetch_st|rom:instruction_ram"
-Info: Elaborating entity "decode_stage" for hierarchy "decode_stage:decode_st"
-Info: Elaborating entity "r2_w_ram" for hierarchy "decode_stage:decode_st|r2_w_ram:register_ram"
-Info: Elaborating entity "decoder" for hierarchy "decode_stage:decode_st|decoder:decoder_inst"
-Info: Elaborating entity "execute_stage" for hierarchy "execute_stage:exec_st"
-Warning (10541): VHDL Signal Declaration warning at execute_stage_b.vhd(19): used implicit default value for signal "ext_gpmp" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
-Info: Elaborating entity "alu" for hierarchy "execute_stage:exec_st|alu:alu_inst"
-Info: Elaborating entity "exec_op" using architecture "A:add_op" for hierarchy "execute_stage:exec_st|alu:alu_inst|exec_op:add_inst"
-Info: Elaborating entity "exec_op" using architecture "A:and_op" for hierarchy "execute_stage:exec_st|alu:alu_inst|exec_op:and_inst"
-Info: Elaborating entity "exec_op" using architecture "A:or_op" for hierarchy "execute_stage:exec_st|alu:alu_inst|exec_op:or_inst"
-Info: Elaborating entity "exec_op" using architecture "A:xor_op" for hierarchy "execute_stage:exec_st|alu:alu_inst|exec_op:xor_inst"
-Info: Elaborating entity "exec_op" using architecture "A:shift_op" for hierarchy "execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst"
-Info: Elaborating entity "extension_gpm" for hierarchy "execute_stage:exec_st|extension_gpm:gpmp_inst"
-Info: Elaborating entity "writeback_stage" for hierarchy "writeback_stage:writeback_st"
-Warning (10036): Verilog HDL or VHDL warning at writeback_stage_b.vhd(20): object "ext_timer" assigned a value but never read
-Warning (10036): Verilog HDL or VHDL warning at writeback_stage_b.vhd(20): object "ext_gpmp" assigned a value but never read
-Warning (10036): Verilog HDL or VHDL warning at writeback_stage_b.vhd(25): object "calc_mem_res" assigned a value but never read
-Info: Elaborating entity "r_w_ram" for hierarchy "writeback_stage:writeback_st|r_w_ram:data_ram"
-Info: Elaborating entity "extension_uart" for hierarchy "writeback_stage:writeback_st|extension_uart:uart"
-Info: Elaborating entity "rs232_tx" for hierarchy "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst"
-Info: Elaborating entity "rs232_rx" for hierarchy "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst"
-Info: Elaborating entity "extension_7seg" for hierarchy "writeback_stage:writeback_st|extension_7seg:sseg"
-Info: Inferred 3 megafunctions from design logic
- Info: Inferred altsyncram megafunction from the following design logic: "writeback_stage:writeback_st|r_w_ram:data_ram|ram~44"
- Info: Parameter OPERATION_MODE set to DUAL_PORT
- Info: Parameter WIDTH_A set to 32
- Info: Parameter WIDTHAD_A set to 11
- Info: Parameter NUMWORDS_A set to 2048
- Info: Parameter WIDTH_B set to 32
- Info: Parameter WIDTHAD_B set to 11
- Info: Parameter NUMWORDS_B set to 2048
- Info: Parameter ADDRESS_ACLR_A set to NONE
- Info: Parameter OUTDATA_REG_B set to UNREGISTERED
- Info: Parameter ADDRESS_ACLR_B set to NONE
- Info: Parameter OUTDATA_ACLR_B set to NONE
- Info: Parameter ADDRESS_REG_B set to CLOCK0
- Info: Parameter INDATA_ACLR_A set to NONE
- Info: Parameter WRCONTROL_ACLR_A set to NONE
- Info: Parameter INIT_FILE set to db/dt.ram0_r_w_ram_1e9198d1.hdl.mif
- Info: Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
- Info: Inferred altsyncram megafunction from the following design logic: "decode_stage:decode_st|r2_w_ram:register_ram|ram~37"
- Info: Parameter OPERATION_MODE set to DUAL_PORT
- Info: Parameter WIDTH_A set to 32
- Info: Parameter WIDTHAD_A set to 4
- Info: Parameter NUMWORDS_A set to 16
- Info: Parameter WIDTH_B set to 32
- Info: Parameter WIDTHAD_B set to 4
- Info: Parameter NUMWORDS_B set to 16
- Info: Parameter ADDRESS_ACLR_A set to NONE
- Info: Parameter OUTDATA_REG_B set to UNREGISTERED
- Info: Parameter ADDRESS_ACLR_B set to NONE
- Info: Parameter OUTDATA_ACLR_B set to NONE
- Info: Parameter ADDRESS_REG_B set to CLOCK0
- Info: Parameter INDATA_ACLR_A set to NONE
- Info: Parameter WRCONTROL_ACLR_A set to NONE
- Info: Parameter INIT_FILE set to db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif
- Info: Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
- Info: Inferred altsyncram megafunction from the following design logic: "decode_stage:decode_st|r2_w_ram:register_ram|ram~38"
- Info: Parameter OPERATION_MODE set to DUAL_PORT
- Info: Parameter WIDTH_A set to 32
- Info: Parameter WIDTHAD_A set to 4
- Info: Parameter NUMWORDS_A set to 16
- Info: Parameter WIDTH_B set to 32
- Info: Parameter WIDTHAD_B set to 4
- Info: Parameter NUMWORDS_B set to 16
- Info: Parameter ADDRESS_ACLR_A set to NONE
- Info: Parameter OUTDATA_REG_B set to UNREGISTERED
- Info: Parameter ADDRESS_ACLR_B set to NONE
- Info: Parameter OUTDATA_ACLR_B set to NONE
- Info: Parameter ADDRESS_REG_B set to CLOCK0
- Info: Parameter INDATA_ACLR_A set to NONE
- Info: Parameter WRCONTROL_ACLR_A set to NONE
- Info: Parameter INIT_FILE set to db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif
- Info: Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
-Info: Elaborated megafunction instantiation "writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0"
-Info: Instantiated megafunction "writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0" with the following parameter:
- Info: Parameter "OPERATION_MODE" = "DUAL_PORT"
- Info: Parameter "WIDTH_A" = "32"
- Info: Parameter "WIDTHAD_A" = "11"
- Info: Parameter "NUMWORDS_A" = "2048"
- Info: Parameter "WIDTH_B" = "32"
- Info: Parameter "WIDTHAD_B" = "11"
- Info: Parameter "NUMWORDS_B" = "2048"
- Info: Parameter "ADDRESS_ACLR_A" = "NONE"
- Info: Parameter "OUTDATA_REG_B" = "UNREGISTERED"
- Info: Parameter "ADDRESS_ACLR_B" = "NONE"
- Info: Parameter "OUTDATA_ACLR_B" = "NONE"
- Info: Parameter "ADDRESS_REG_B" = "CLOCK0"
- Info: Parameter "INDATA_ACLR_A" = "NONE"
- Info: Parameter "WRCONTROL_ACLR_A" = "NONE"
- Info: Parameter "INIT_FILE" = "db/dt.ram0_r_w_ram_1e9198d1.hdl.mif"
- Info: Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA"
-Info: Found 1 design units, including 1 entities, in source file db/altsyncram_grk1.tdf
- Info: Found entity 1: altsyncram_grk1
-Info: Elaborated megafunction instantiation "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1"
-Info: Instantiated megafunction "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1" with the following parameter:
- Info: Parameter "OPERATION_MODE" = "DUAL_PORT"
- Info: Parameter "WIDTH_A" = "32"
- Info: Parameter "WIDTHAD_A" = "4"
- Info: Parameter "NUMWORDS_A" = "16"
- Info: Parameter "WIDTH_B" = "32"
- Info: Parameter "WIDTHAD_B" = "4"
- Info: Parameter "NUMWORDS_B" = "16"
- Info: Parameter "ADDRESS_ACLR_A" = "NONE"
- Info: Parameter "OUTDATA_REG_B" = "UNREGISTERED"
- Info: Parameter "ADDRESS_ACLR_B" = "NONE"
- Info: Parameter "OUTDATA_ACLR_B" = "NONE"
- Info: Parameter "ADDRESS_REG_B" = "CLOCK0"
- Info: Parameter "INDATA_ACLR_A" = "NONE"
- Info: Parameter "WRCONTROL_ACLR_A" = "NONE"
- Info: Parameter "INIT_FILE" = "db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif"
- Info: Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA"
-Info: Found 1 design units, including 1 entities, in source file db/altsyncram_emk1.tdf
- Info: Found entity 1: altsyncram_emk1
-Info: Registers with preset signals will power-up high
-Info: 130 registers lost all their fanouts during netlist optimizations. The first 130 are displayed below.
- Info: Register "writeback_stage:writeback_st|wb_reg.address[0]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|wb_reg.address[1]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][29]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][28]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][27]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][26]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][25]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][24]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][23]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][22]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][21]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][20]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][19]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][18]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][17]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][16]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][15]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][14]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][13]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][12]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][11]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][10]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][9]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][8]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][7]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][6]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][5]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][4]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][3]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][2]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][1]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][0]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][29]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][28]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][27]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][26]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][25]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][24]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][23]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][22]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][21]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][20]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][19]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][18]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][17]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][16]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][15]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][14]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][13]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][12]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][11]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][10]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][9]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][8]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][7]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][6]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][5]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][4]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][3]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][2]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][1]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][0]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][29]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][28]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][27]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][26]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][25]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][24]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][23]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][22]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][21]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][20]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][19]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][18]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][17]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][16]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][15]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][14]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][13]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][12]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][11]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][10]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][9]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][8]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][7]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][6]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][5]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][4]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][3]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][2]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][1]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][0]" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.oflo" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.sign" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[11]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[12]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[13]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[14]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[15]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[16]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[17]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[18]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[19]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[20]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[21]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[22]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[23]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[24]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[25]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[26]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[27]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[28]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[29]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[30]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[31]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[31]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[30]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[29]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[28]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[27]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[26]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[25]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[24]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[23]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[22]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[21]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[20]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[19]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[18]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[17]" lost all its fanouts during netlist optimizations.
-Info: Generating hard_block partition "hard_block:auto_generated_inst"
-Info: Implemented 2007 device resources after synthesis - the final resource count might be different
- Info: Implemented 3 input pins
- Info: Implemented 29 output pins
- Info: Implemented 1879 logic cells
- Info: Implemented 96 RAM segments
-Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings
- Info: Peak virtual memory: 270 megabytes
- Info: Processing ended: Sun Dec 19 20:36:26 2010
- Info: Elapsed time: 00:00:14
- Info: Total CPU time (on all processors): 00:00:13
-
-
+++ /dev/null
-Analysis & Synthesis Status : Successful - Sun Dec 19 20:36:26 2010
-Quartus II Version : 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition
-Revision Name : dt
-Top-level Entity Name : core_top
-Family : Cyclone
-Total logic elements : 1,879
-Total pins : 32
-Total virtual pins : 0
-Total memory bits : 66,560
-Total PLLs : 0
+++ /dev/null
- -- Copyright (C) 1991-2010 Altera Corporation
- -- Your use of Altera Corporation's design tools, logic functions
- -- and other software and tools, and its AMPP partner logic
- -- functions, and any output files from any of the foregoing
- -- (including device programming or simulation files), and any
- -- associated documentation or information are expressly subject
- -- to the terms and conditions of the Altera Program License
- -- Subscription Agreement, Altera MegaCore Function License
- -- Agreement, or other applicable license agreement, including,
- -- without limitation, that your use is for the sole purpose of
- -- programming logic devices manufactured by Altera and sold by
- -- Altera or its authorized distributors. Please refer to the
- -- applicable agreement for further details.
- --
- -- This is a Quartus II output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus II input file. This file cannot be used
- -- to make Quartus II pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus II help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC : No Connect. This pin has no internal connection to the device.
- -- DNU : Do Not Use. This pin MUST NOT be connected.
- -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.5V).
- -- VCCIO : Dedicated power pin, which MUST be connected to VCC
- -- of its bank.
- -- Bank 1: 3.3V
- -- Bank 2: 3.3V
- -- Bank 3: 3.3V
- -- Bank 4: 3.3V
- -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- -- It can also be used to report unused dedicated pins. The connection
- -- on the board for unused dedicated pins depends on whether this will
- -- be used in a future design. One example is device migration. When
- -- using device migration, refer to the device pin-tables. If it is a
- -- GND pin in the pin table or if it will not be used in a future design
- -- for another purpose the it MUST be connected to GND. If it is an unused
- -- dedicated pin, then it can be connected to a valid signal on the board
- -- (low, high, or toggling) if that signal is required for a different
- -- revision of the design.
- -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
- -- This pin should be connected to GND. It may also be connected to a
- -- valid signal on the board (low, high, or toggling) if that signal
- -- is required for a different revision of the design.
- -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
- -- or leave it unconnected.
- -- RESERVED : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
-CHIP "dt" ASSIGNED TO AN: EP1C12Q240C8
-
-Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
--------------------------------------------------------------------------------------------------------------
-RESERVED_INPUT : 1 : : : : 1 :
-RESERVED_INPUT : 2 : : : : 1 :
-RESERVED_INPUT : 3 : : : : 1 :
-RESERVED_INPUT : 4 : : : : 1 :
-RESERVED_INPUT : 5 : : : : 1 :
-RESERVED_INPUT : 6 : : : : 1 :
-RESERVED_INPUT : 7 : : : : 1 :
-RESERVED_INPUT : 8 : : : : 1 :
-VCCIO1 : 9 : power : : 3.3V : 1 :
-GND : 10 : gnd : : : :
-RESERVED_INPUT : 11 : : : : 1 :
-RESERVED_INPUT : 12 : : : : 1 :
-RESERVED_INPUT : 13 : : : : 1 :
-RESERVED_INPUT : 14 : : : : 1 :
-RESERVED_INPUT : 15 : : : : 1 :
-RESERVED_INPUT : 16 : : : : 1 :
-bus_rx : 17 : input : 3.3-V LVCMOS : : 1 : N
-sseg1[0] : 18 : output : 3.3-V LVCMOS : : 1 : N
-RESERVED_INPUT : 19 : : : : 1 :
-sseg2[4] : 20 : output : 3.3-V LVCMOS : : 1 : N
-sseg2[0] : 21 : output : 3.3-V LVCMOS : : 1 : N
-VCCIO1 : 22 : power : : 3.3V : 1 :
-sseg3[3] : 23 : output : 3.3-V LVCMOS : : 1 : N
-~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 24 : input : 3.3-V LVCMOS : : 1 : N
-DATA0 : 25 : input : : : 1 :
-nCONFIG : 26 : : : : 1 :
-VCCA_PLL1 : 27 : power : : 1.5V : :
-GND+ : 28 : : : : 1 :
-GND+ : 29 : : : : 1 :
-GNDA_PLL1 : 30 : gnd : : : :
-GNDG_PLL1 : 31 : gnd : : : :
-nCEO : 32 : : : : 1 :
-nCE : 33 : : : : 1 :
-MSEL0 : 34 : : : : 1 :
-MSEL1 : 35 : : : : 1 :
-DCLK : 36 : bidir : : : 1 :
-~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 37 : input : 3.3-V LVCMOS : : 1 : N
-sseg3[2] : 38 : output : 3.3-V LVCMOS : : 1 : N
-sseg0[3] : 39 : output : 3.3-V LVCMOS : : 1 : N
-GND : 40 : gnd : : : :
-RESERVED_INPUT : 41 : : : : 1 :
-sys_res : 42 : input : 3.3-V LVCMOS : : 1 : Y
-RESERVED_INPUT : 43 : : : : 1 :
-RESERVED_INPUT : 44 : : : : 1 :
-RESERVED_INPUT : 45 : : : : 1 :
-RESERVED_INPUT : 46 : : : : 1 :
-RESERVED_INPUT : 47 : : : : 1 :
-RESERVED_INPUT : 48 : : : : 1 :
-RESERVED_INPUT : 49 : : : : 1 :
-RESERVED_INPUT : 50 : : : : 1 :
-VCCIO1 : 51 : power : : 3.3V : 1 :
-GND : 52 : gnd : : : :
-RESERVED_INPUT : 53 : : : : 1 :
-RESERVED_INPUT : 54 : : : : 1 :
-RESERVED_INPUT : 55 : : : : 1 :
-RESERVED_INPUT : 56 : : : : 1 :
-RESERVED_INPUT : 57 : : : : 1 :
-RESERVED_INPUT : 58 : : : : 1 :
-RESERVED_INPUT : 59 : : : : 1 :
-RESERVED_INPUT : 60 : : : : 1 :
-RESERVED_INPUT : 61 : : : : 4 :
-RESERVED_INPUT : 62 : : : : 4 :
-RESERVED_INPUT : 63 : : : : 4 :
-RESERVED_INPUT : 64 : : : : 4 :
-RESERVED_INPUT : 65 : : : : 4 :
-RESERVED_INPUT : 66 : : : : 4 :
-RESERVED_INPUT : 67 : : : : 4 :
-RESERVED_INPUT : 68 : : : : 4 :
-GND : 69 : gnd : : : :
-VCCIO4 : 70 : power : : 3.3V : 4 :
-GND : 71 : gnd : : : :
-VCCINT : 72 : power : : 1.5V : :
-RESERVED_INPUT : 73 : : : : 4 :
-RESERVED_INPUT : 74 : : : : 4 :
-RESERVED_INPUT : 75 : : : : 4 :
-RESERVED_INPUT : 76 : : : : 4 :
-RESERVED_INPUT : 77 : : : : 4 :
-RESERVED_INPUT : 78 : : : : 4 :
-RESERVED_INPUT : 79 : : : : 4 :
-GND : 80 : gnd : : : :
-VCCINT : 81 : power : : 1.5V : :
-RESERVED_INPUT : 82 : : : : 4 :
-sseg0[0] : 83 : output : 3.3-V LVCMOS : : 4 : N
-sseg3[1] : 84 : output : 3.3-V LVCMOS : : 4 : N
-sseg3[4] : 85 : output : 3.3-V LVCMOS : : 4 : N
-sseg0[1] : 86 : output : 3.3-V LVCMOS : : 4 : N
-sseg3[0] : 87 : output : 3.3-V LVCMOS : : 4 : N
-sseg0[5] : 88 : output : 3.3-V LVCMOS : : 4 : N
-GND : 89 : gnd : : : :
-VCCINT : 90 : power : : 1.5V : :
-GND : 91 : gnd : : : :
-VCCIO4 : 92 : power : : 3.3V : 4 :
-sseg1[1] : 93 : output : 3.3-V LVCMOS : : 4 : N
-sseg1[2] : 94 : output : 3.3-V LVCMOS : : 4 : N
-sseg1[6] : 95 : output : 3.3-V LVCMOS : : 4 : N
-GND : 96 : gnd : : : :
-VCCINT : 97 : power : : 1.5V : :
-RESERVED_INPUT : 98 : : : : 4 :
-RESERVED_INPUT : 99 : : : : 4 :
-RESERVED_INPUT : 100 : : : : 4 :
-RESERVED_INPUT : 101 : : : : 4 :
-GND : 102 : gnd : : : :
-VCCINT : 103 : power : : 1.5V : :
-RESERVED_INPUT : 104 : : : : 4 :
-RESERVED_INPUT : 105 : : : : 4 :
-RESERVED_INPUT : 106 : : : : 4 :
-RESERVED_INPUT : 107 : : : : 4 :
-RESERVED_INPUT : 108 : : : : 4 :
-GND : 109 : gnd : : : :
-VCCINT : 110 : power : : 1.5V : :
-GND : 111 : gnd : : : :
-VCCIO4 : 112 : power : : 3.3V : 4 :
-RESERVED_INPUT : 113 : : : : 4 :
-RESERVED_INPUT : 114 : : : : 4 :
-RESERVED_INPUT : 115 : : : : 4 :
-RESERVED_INPUT : 116 : : : : 4 :
-RESERVED_INPUT : 117 : : : : 4 :
-RESERVED_INPUT : 118 : : : : 4 :
-RESERVED_INPUT : 119 : : : : 4 :
-RESERVED_INPUT : 120 : : : : 4 :
-RESERVED_INPUT : 121 : : : : 3 :
-RESERVED_INPUT : 122 : : : : 3 :
-RESERVED_INPUT : 123 : : : : 3 :
-RESERVED_INPUT : 124 : : : : 3 :
-RESERVED_INPUT : 125 : : : : 3 :
-RESERVED_INPUT : 126 : : : : 3 :
-RESERVED_INPUT : 127 : : : : 3 :
-RESERVED_INPUT : 128 : : : : 3 :
-GND : 129 : gnd : : : :
-VCCIO3 : 130 : power : : 3.3V : 3 :
-RESERVED_INPUT : 131 : : : : 3 :
-RESERVED_INPUT : 132 : : : : 3 :
-RESERVED_INPUT : 133 : : : : 3 :
-RESERVED_INPUT : 134 : : : : 3 :
-RESERVED_INPUT : 135 : : : : 3 :
-RESERVED_INPUT : 136 : : : : 3 :
-RESERVED_INPUT : 137 : : : : 3 :
-RESERVED_INPUT : 138 : : : : 3 :
-RESERVED_INPUT : 139 : : : : 3 :
-RESERVED_INPUT : 140 : : : : 3 :
-RESERVED_INPUT : 141 : : : : 3 :
-GND : 142 : gnd : : : :
-RESERVED_INPUT : 143 : : : : 3 :
-sseg0[2] : 144 : output : 3.3-V LVCMOS : : 3 : N
-CONF_DONE : 145 : : : : 3 :
-nSTATUS : 146 : : : : 3 :
-TCK : 147 : input : : : 3 :
-TMS : 148 : input : : : 3 :
-TDO : 149 : output : : : 3 :
-GNDG_PLL2 : 150 : gnd : : : :
-GNDA_PLL2 : 151 : gnd : : : :
-sys_clk : 152 : input : 3.3-V LVCMOS : : 3 : Y
-GND+ : 153 : : : : 3 :
-VCCA_PLL2 : 154 : power : : 1.5V : :
-TDI : 155 : input : : : 3 :
-RESERVED_INPUT : 156 : : : : 3 :
-VCCIO3 : 157 : power : : 3.3V : 3 :
-RESERVED_INPUT : 158 : : : : 3 :
-RESERVED_INPUT : 159 : : : : 3 :
-sseg2[6] : 160 : output : 3.3-V LVCMOS : : 3 : N
-sseg2[2] : 161 : output : 3.3-V LVCMOS : : 3 : N
-sseg1[3] : 162 : output : 3.3-V LVCMOS : : 3 : N
-RESERVED_INPUT : 163 : : : : 3 :
-RESERVED_INPUT : 164 : : : : 3 :
-RESERVED_INPUT : 165 : : : : 3 :
-bus_tx : 166 : output : 3.3-V LVCMOS : : 3 : Y
-RESERVED_INPUT : 167 : : : : 3 :
-RESERVED_INPUT : 168 : : : : 3 :
-RESERVED_INPUT : 169 : : : : 3 :
-RESERVED_INPUT : 170 : : : : 3 :
-GND : 171 : gnd : : : :
-VCCIO3 : 172 : power : : 3.3V : 3 :
-RESERVED_INPUT : 173 : : : : 3 :
-RESERVED_INPUT : 174 : : : : 3 :
-RESERVED_INPUT : 175 : : : : 3 :
-RESERVED_INPUT : 176 : : : : 3 :
-RESERVED_INPUT : 177 : : : : 3 :
-RESERVED_INPUT : 178 : : : : 3 :
-RESERVED_INPUT : 179 : : : : 3 :
-RESERVED_INPUT : 180 : : : : 3 :
-RESERVED_INPUT : 181 : : : : 2 :
-RESERVED_INPUT : 182 : : : : 2 :
-RESERVED_INPUT : 183 : : : : 2 :
-RESERVED_INPUT : 184 : : : : 2 :
-RESERVED_INPUT : 185 : : : : 2 :
-RESERVED_INPUT : 186 : : : : 2 :
-RESERVED_INPUT : 187 : : : : 2 :
-RESERVED_INPUT : 188 : : : : 2 :
-VCCIO2 : 189 : power : : 3.3V : 2 :
-GND : 190 : gnd : : : :
-VCCINT : 191 : power : : 1.5V : :
-GND : 192 : gnd : : : :
-RESERVED_INPUT : 193 : : : : 2 :
-RESERVED_INPUT : 194 : : : : 2 :
-RESERVED_INPUT : 195 : : : : 2 :
-RESERVED_INPUT : 196 : : : : 2 :
-RESERVED_INPUT : 197 : : : : 2 :
-VCCINT : 198 : power : : 1.5V : :
-GND : 199 : gnd : : : :
-sseg2[5] : 200 : output : 3.3-V LVCMOS : : 2 : N
-sseg2[1] : 201 : output : 3.3-V LVCMOS : : 2 : N
-sseg2[3] : 202 : output : 3.3-V LVCMOS : : 2 : N
-RESERVED_INPUT : 203 : : : : 2 :
-VCCINT : 204 : power : : 1.5V : :
-GND : 205 : gnd : : : :
-sseg1[5] : 206 : output : 3.3-V LVCMOS : : 2 : N
-sseg1[4] : 207 : output : 3.3-V LVCMOS : : 2 : N
-RESERVED_INPUT : 208 : : : : 2 :
-VCCIO2 : 209 : power : : 3.3V : 2 :
-GND : 210 : gnd : : : :
-VCCINT : 211 : power : : 1.5V : :
-GND : 212 : gnd : : : :
-sseg0[4] : 213 : output : 3.3-V LVCMOS : : 2 : N
-sseg0[6] : 214 : output : 3.3-V LVCMOS : : 2 : N
-sseg3[5] : 215 : output : 3.3-V LVCMOS : : 2 : N
-sseg3[6] : 216 : output : 3.3-V LVCMOS : : 2 : N
-RESERVED_INPUT : 217 : : : : 2 :
-RESERVED_INPUT : 218 : : : : 2 :
-RESERVED_INPUT : 219 : : : : 2 :
-VCCINT : 220 : power : : 1.5V : :
-GND : 221 : gnd : : : :
-RESERVED_INPUT : 222 : : : : 2 :
-RESERVED_INPUT : 223 : : : : 2 :
-RESERVED_INPUT : 224 : : : : 2 :
-RESERVED_INPUT : 225 : : : : 2 :
-RESERVED_INPUT : 226 : : : : 2 :
-RESERVED_INPUT : 227 : : : : 2 :
-RESERVED_INPUT : 228 : : : : 2 :
-VCCINT : 229 : power : : 1.5V : :
-GND : 230 : gnd : : : :
-VCCIO2 : 231 : power : : 3.3V : 2 :
-GND : 232 : gnd : : : :
-RESERVED_INPUT : 233 : : : : 2 :
-RESERVED_INPUT : 234 : : : : 2 :
-RESERVED_INPUT : 235 : : : : 2 :
-RESERVED_INPUT : 236 : : : : 2 :
-RESERVED_INPUT : 237 : : : : 2 :
-RESERVED_INPUT : 238 : : : : 2 :
-RESERVED_INPUT : 239 : : : : 2 :
-RESERVED_INPUT : 240 : : : : 2 :
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
-set_global_assignment -name MISC_FILE /homes/burban/dt/dt.dpf
+set_location_assignment PIN_42 -to sys_res
set_location_assignment PIN_166 -to bus_tx
set_location_assignment PIN_152 -to sys_clk
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
-set_global_assignment -name MISC_FILE /homes/c0726283/calu/dt/dt.dpf
-set_location_assignment PIN_42 -to sys_res
set_global_assignment -name VHDL_FILE ../cpu/src/rom.vhd
set_global_assignment -name VHDL_FILE ../cpu/src/rom_b.vhd
set_global_assignment -name VHDL_FILE ../cpu/src/extension_7seg_pkg.vhd
set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/or_op_b.vhd
set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/and_op_b.vhd
set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/add_op_b.vhd
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+++ /dev/null
-Classic Timing Analyzer report for dt
-Sun Dec 19 20:36:51 2010
-Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Classic Timing Analyzer Deprecation
- 3. Timing Analyzer Summary
- 4. Timing Analyzer Settings
- 5. Clock Settings Summary
- 6. Parallel Compilation
- 7. Clock Setup: 'sys_clk'
- 8. tsu
- 9. tco
- 10. th
- 11. Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2010 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Altera Program License
-Subscription Agreement, Altera MegaCore Function License
-Agreement, or other applicable license agreement, including,
-without limitation, that your use is for the sole purpose of
-programming logic devices manufactured by Altera and sold by
-Altera or its authorized distributors. Please refer to the
-applicable agreement for further details.
-
-
-
----------------------------------------
-; Classic Timing Analyzer Deprecation ;
----------------------------------------
-Classic Timing Analyzer will not be available in a future release of the Quartus II software. Use the TimeQuest Timing Analyzer to run timing analysis on your design. Convert all the project settings and the timing constraints to TimeQuest Timing Analyzer equivalents.
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Timing Analyzer Summary ;
-+------------------------------+-------+---------------+----------------------------------+------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+------------+----------+--------------+
-; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
-+------------------------------+-------+---------------+----------------------------------+------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+------------+----------+--------------+
-; Worst-case tsu ; N/A ; None ; 18.145 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; -- ; sys_clk ; 0 ;
-; Worst-case tco ; N/A ; None ; 10.677 ns ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; bus_tx ; sys_clk ; -- ; 0 ;
-; Worst-case th ; N/A ; None ; -5.628 ns ; bus_rx ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|sync[1] ; -- ; sys_clk ; 0 ;
-; Clock Setup: 'sys_clk' ; N/A ; None ; 36.95 MHz ( period = 27.067 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 0 ;
-; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
-+------------------------------+-------+---------------+----------------------------------+------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+------------+----------+--------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------+
-; Timing Analyzer Settings ;
-+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
-; Option ; Setting ; From ; To ; Entity Name ;
-+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
-; Device Name ; EP1C12Q240C8 ; ; ; ;
-; Timing Models ; Final ; ; ; ;
-; Default hold multicycle ; Same as Multicycle ; ; ; ;
-; Cut paths between unrelated clock domains ; On ; ; ; ;
-; Cut off read during write signal paths ; On ; ; ; ;
-; Cut off feedback from I/O pins ; On ; ; ; ;
-; Report Combined Fast/Slow Timing ; Off ; ; ; ;
-; Ignore Clock Settings ; Off ; ; ; ;
-; Analyze latches as synchronous elements ; On ; ; ; ;
-; Enable Recovery/Removal analysis ; Off ; ; ; ;
-; Enable Clock Latency ; Off ; ; ; ;
-; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
-; Number of source nodes to report per destination node ; 10 ; ; ; ;
-; Number of destination nodes to report ; 10 ; ; ; ;
-; Number of paths to report ; 200 ; ; ; ;
-; Report Minimum Timing Checks ; Off ; ; ; ;
-; Use Fast Timing Models ; Off ; ; ; ;
-; Report IO Paths Separately ; Off ; ; ; ;
-; Perform Multicorner Analysis ; Off ; ; ; ;
-; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
-; Reports worst-case timing paths for each clock domain and analysis ; On ; ; ; ;
-; Specifies the maximum number of worst-case timing paths to report for each clock domain and analysis ; 100 ; ; ; ;
-; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
-+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clock Settings Summary ;
-+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
-; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
-+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
-; sys_clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
-+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
-
-
-Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
-+-------------------------------------+
-; Parallel Compilation ;
-+----------------------------+--------+
-; Processors ; Number ;
-+----------------------------+--------+
-; Number detected on machine ; 2 ;
-; Maximum allowed ; 1 ;
-+----------------------------+--------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clock Setup: 'sys_clk' ;
-+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
-; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
-+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
-; N/A ; 36.95 MHz ( period = 27.067 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 26.747 ns ;
-; N/A ; 38.35 MHz ( period = 26.075 ns ) ; writeback_stage:writeback_st|wb_reg.address[3] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 25.790 ns ;
-; N/A ; 39.35 MHz ( period = 25.412 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 25.151 ns ;
-; N/A ; 39.69 MHz ( period = 25.193 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[15] ; sys_clk ; sys_clk ; None ; None ; 24.873 ns ;
-; N/A ; 39.79 MHz ( period = 25.134 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[9] ; sys_clk ; sys_clk ; None ; None ; 24.805 ns ;
-; N/A ; 39.86 MHz ( period = 25.086 ns ) ; writeback_stage:writeback_st|wb_reg.address[2] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.801 ns ;
-; N/A ; 39.87 MHz ( period = 25.079 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 24.759 ns ;
-; N/A ; 39.91 MHz ( period = 25.059 ns ) ; writeback_stage:writeback_st|wb_reg.address[21] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.798 ns ;
-; N/A ; 40.12 MHz ( period = 24.928 ns ) ; writeback_stage:writeback_st|wb_reg.address[12] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.667 ns ;
-; N/A ; 40.16 MHz ( period = 24.899 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~portb_address_reg0 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.205 ns ;
-; N/A ; 40.16 MHz ( period = 24.899 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~portb_address_reg1 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.205 ns ;
-; N/A ; 40.16 MHz ( period = 24.899 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~portb_address_reg2 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.205 ns ;
-; N/A ; 40.16 MHz ( period = 24.899 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~portb_address_reg3 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.205 ns ;
-; N/A ; 40.16 MHz ( period = 24.899 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~portb_address_reg4 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.205 ns ;
-; N/A ; 40.16 MHz ( period = 24.899 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~portb_address_reg5 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.205 ns ;
-; N/A ; 40.16 MHz ( period = 24.899 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~portb_address_reg6 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.205 ns ;
-; N/A ; 40.16 MHz ( period = 24.899 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~portb_address_reg7 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.205 ns ;
-; N/A ; 40.16 MHz ( period = 24.899 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~portb_address_reg8 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.205 ns ;
-; N/A ; 40.16 MHz ( period = 24.899 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~portb_address_reg9 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.205 ns ;
-; N/A ; 40.16 MHz ( period = 24.899 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~portb_address_reg10 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.205 ns ;
-; N/A ; 40.19 MHz ( period = 24.883 ns ) ; writeback_stage:writeback_st|wb_reg.address[17] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.622 ns ;
-; N/A ; 40.19 MHz ( period = 24.882 ns ) ; writeback_stage:writeback_st|wb_reg.address[20] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.621 ns ;
-; N/A ; 40.19 MHz ( period = 24.881 ns ) ; writeback_stage:writeback_st|wb_reg.address[28] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.620 ns ;
-; N/A ; 40.22 MHz ( period = 24.866 ns ) ; writeback_stage:writeback_st|wb_reg.address[18] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.605 ns ;
-; N/A ; 40.37 MHz ( period = 24.770 ns ) ; writeback_stage:writeback_st|wb_reg.address[22] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.509 ns ;
-; N/A ; 40.40 MHz ( period = 24.750 ns ) ; writeback_stage:writeback_st|wb_reg.address[16] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.489 ns ;
-; N/A ; 40.46 MHz ( period = 24.718 ns ) ; writeback_stage:writeback_st|wb_reg.address[29] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.457 ns ;
-; N/A ; 40.48 MHz ( period = 24.704 ns ) ; writeback_stage:writeback_st|wb_reg.address[26] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.443 ns ;
-; N/A ; 40.49 MHz ( period = 24.697 ns ) ; writeback_stage:writeback_st|wb_reg.address[15] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.436 ns ;
-; N/A ; 40.53 MHz ( period = 24.674 ns ) ; writeback_stage:writeback_st|wb_reg.address[19] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.413 ns ;
-; N/A ; 40.65 MHz ( period = 24.598 ns ) ; writeback_stage:writeback_st|wb_reg.address[30] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.337 ns ;
-; N/A ; 40.67 MHz ( period = 24.590 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.329 ns ;
-; N/A ; 40.77 MHz ( period = 24.528 ns ) ; writeback_stage:writeback_st|wb_reg.address[27] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.267 ns ;
-; N/A ; 40.80 MHz ( period = 24.509 ns ) ; writeback_stage:writeback_st|wb_reg.address[14] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.248 ns ;
-; N/A ; 40.82 MHz ( period = 24.497 ns ) ; writeback_stage:writeback_st|wb_reg.address[5] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.245 ns ;
-; N/A ; 40.95 MHz ( period = 24.422 ns ) ; writeback_stage:writeback_st|wb_reg.address[25] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.161 ns ;
-; N/A ; 40.96 MHz ( period = 24.417 ns ) ; writeback_stage:writeback_st|wb_reg.address[6] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.156 ns ;
-; N/A ; 40.96 MHz ( period = 24.413 ns ) ; writeback_stage:writeback_st|wb_reg.address[31] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.152 ns ;
-; N/A ; 41.26 MHz ( period = 24.235 ns ) ; writeback_stage:writeback_st|wb_reg.address[8] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.974 ns ;
-; N/A ; 41.29 MHz ( period = 24.220 ns ) ; writeback_stage:writeback_st|wb_reg.address[24] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.959 ns ;
-; N/A ; 41.32 MHz ( period = 24.201 ns ) ; writeback_stage:writeback_st|wb_reg.address[3] ; execute_stage:exec_st|reg.result[15] ; sys_clk ; sys_clk ; None ; None ; 23.916 ns ;
-; N/A ; 41.32 MHz ( period = 24.200 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a2~portb_address_reg0 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.515 ns ;
-; N/A ; 41.32 MHz ( period = 24.200 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a2~portb_address_reg1 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.515 ns ;
-; N/A ; 41.32 MHz ( period = 24.200 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.515 ns ;
-; N/A ; 41.32 MHz ( period = 24.200 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a2~portb_address_reg3 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.515 ns ;
-; N/A ; 41.32 MHz ( period = 24.200 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a2~portb_address_reg4 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.515 ns ;
-; N/A ; 41.32 MHz ( period = 24.200 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a2~portb_address_reg5 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.515 ns ;
-; N/A ; 41.32 MHz ( period = 24.200 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a2~portb_address_reg6 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.515 ns ;
-; N/A ; 41.32 MHz ( period = 24.200 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a2~portb_address_reg7 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.515 ns ;
-; N/A ; 41.32 MHz ( period = 24.200 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a2~portb_address_reg8 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.515 ns ;
-; N/A ; 41.32 MHz ( period = 24.200 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a2~portb_address_reg9 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.515 ns ;
-; N/A ; 41.32 MHz ( period = 24.200 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a2~portb_address_reg10 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.515 ns ;
-; N/A ; 41.42 MHz ( period = 24.142 ns ) ; writeback_stage:writeback_st|wb_reg.address[3] ; execute_stage:exec_st|reg.result[9] ; sys_clk ; sys_clk ; None ; None ; 23.848 ns ;
-; N/A ; 41.52 MHz ( period = 24.087 ns ) ; writeback_stage:writeback_st|wb_reg.address[3] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 23.802 ns ;
-; N/A ; 41.60 MHz ( period = 24.039 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[19] ; sys_clk ; sys_clk ; None ; None ; 23.743 ns ;
-; N/A ; 41.68 MHz ( period = 23.990 ns ) ; writeback_stage:writeback_st|wb_reg.address[4] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.729 ns ;
-; N/A ; 41.69 MHz ( period = 23.987 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2|altsyncram_emk1:auto_generated|ram_block1a6~portb_address_reg0 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.293 ns ;
-; N/A ; 41.69 MHz ( period = 23.987 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2|altsyncram_emk1:auto_generated|ram_block1a6~portb_address_reg1 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.293 ns ;
-; N/A ; 41.69 MHz ( period = 23.987 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2|altsyncram_emk1:auto_generated|ram_block1a6~portb_address_reg2 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.293 ns ;
-; N/A ; 41.69 MHz ( period = 23.987 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2|altsyncram_emk1:auto_generated|ram_block1a6~portb_address_reg3 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.293 ns ;
-; N/A ; 41.78 MHz ( period = 23.935 ns ) ; writeback_stage:writeback_st|wb_reg.address[13] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.674 ns ;
-; N/A ; 41.81 MHz ( period = 23.916 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 23.579 ns ;
-; N/A ; 41.85 MHz ( period = 23.896 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a24~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.514 ns ;
-; N/A ; 41.85 MHz ( period = 23.894 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[13] ; sys_clk ; sys_clk ; None ; None ; 23.633 ns ;
-; N/A ; 41.86 MHz ( period = 23.890 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a16~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.508 ns ;
-; N/A ; 41.90 MHz ( period = 23.867 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a29~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.552 ns ;
-; N/A ; 41.92 MHz ( period = 23.854 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.548 ns ;
-; N/A ; 41.93 MHz ( period = 23.847 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a24~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.461 ns ;
-; N/A ; 41.93 MHz ( period = 23.847 ns ) ; writeback_stage:writeback_st|wb_reg.address[10] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.586 ns ;
-; N/A ; 41.94 MHz ( period = 23.841 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a16~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.455 ns ;
-; N/A ; 41.95 MHz ( period = 23.839 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[10] ; sys_clk ; sys_clk ; None ; None ; 23.510 ns ;
-; N/A ; 41.99 MHz ( period = 23.818 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a29~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.499 ns ;
-; N/A ; 42.01 MHz ( period = 23.805 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.495 ns ;
-; N/A ; 42.02 MHz ( period = 23.801 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a9~portb_address_reg0 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.107 ns ;
-; N/A ; 42.02 MHz ( period = 23.801 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a9~portb_address_reg1 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.107 ns ;
-; N/A ; 42.02 MHz ( period = 23.801 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a9~portb_address_reg2 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.107 ns ;
-; N/A ; 42.02 MHz ( period = 23.801 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a9~portb_address_reg3 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.107 ns ;
-; N/A ; 42.06 MHz ( period = 23.773 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~porta_address_reg0 ; sys_clk ; sys_clk ; None ; None ; 23.467 ns ;
-; N/A ; 42.07 MHz ( period = 23.771 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[18] ; sys_clk ; sys_clk ; None ; None ; 23.475 ns ;
-; N/A ; 42.07 MHz ( period = 23.771 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a7~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.456 ns ;
-; N/A ; 42.10 MHz ( period = 23.755 ns ) ; writeback_stage:writeback_st|wb_reg.address[21] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 23.494 ns ;
-; N/A ; 42.11 MHz ( period = 23.748 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; execute_stage:exec_st|reg.result[15] ; sys_clk ; sys_clk ; None ; None ; 23.487 ns ;
-; N/A ; 42.15 MHz ( period = 23.722 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a7~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.403 ns ;
-; N/A ; 42.17 MHz ( period = 23.715 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a20~portb_address_reg0 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.997 ns ;
-; N/A ; 42.17 MHz ( period = 23.715 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a20~portb_address_reg1 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.997 ns ;
-; N/A ; 42.17 MHz ( period = 23.715 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a20~portb_address_reg2 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.997 ns ;
-; N/A ; 42.17 MHz ( period = 23.715 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a20~portb_address_reg3 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.997 ns ;
-; N/A ; 42.17 MHz ( period = 23.715 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a20~portb_address_reg4 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.997 ns ;
-; N/A ; 42.17 MHz ( period = 23.715 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a20~portb_address_reg5 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.997 ns ;
-; N/A ; 42.17 MHz ( period = 23.715 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a20~portb_address_reg6 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.997 ns ;
-; N/A ; 42.17 MHz ( period = 23.715 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a20~portb_address_reg7 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.997 ns ;
-; N/A ; 42.17 MHz ( period = 23.715 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a20~portb_address_reg8 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.997 ns ;
-; N/A ; 42.17 MHz ( period = 23.715 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a20~portb_address_reg9 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.997 ns ;
-; N/A ; 42.17 MHz ( period = 23.715 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a20~portb_address_reg10 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.997 ns ;
-; N/A ; 42.19 MHz ( period = 23.701 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[11] ; sys_clk ; sys_clk ; None ; None ; 23.372 ns ;
-; N/A ; 42.31 MHz ( period = 23.634 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 23.373 ns ;
-; N/A ; 42.33 MHz ( period = 23.624 ns ) ; writeback_stage:writeback_st|wb_reg.address[12] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 23.363 ns ;
-; N/A ; 42.36 MHz ( period = 23.609 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[27] ; sys_clk ; sys_clk ; None ; None ; 23.289 ns ;
-; N/A ; 42.41 MHz ( period = 23.579 ns ) ; writeback_stage:writeback_st|wb_reg.address[17] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 23.318 ns ;
-; N/A ; 42.41 MHz ( period = 23.578 ns ) ; writeback_stage:writeback_st|wb_reg.address[20] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 23.317 ns ;
-; N/A ; 42.41 MHz ( period = 23.577 ns ) ; writeback_stage:writeback_st|wb_reg.address[28] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 23.316 ns ;
-; N/A ; 42.47 MHz ( period = 23.545 ns ) ; writeback_stage:writeback_st|wb_reg.address[9] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.284 ns ;
-; N/A ; 42.54 MHz ( period = 23.508 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a6~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.261 ns ;
-; N/A ; 42.56 MHz ( period = 23.495 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a30~portb_address_reg0 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.742 ns ;
-; N/A ; 42.56 MHz ( period = 23.495 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a30~portb_address_reg1 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.742 ns ;
-; N/A ; 42.56 MHz ( period = 23.495 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a30~portb_address_reg2 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.742 ns ;
-; N/A ; 42.56 MHz ( period = 23.495 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a30~portb_address_reg3 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.742 ns ;
-; N/A ; 42.56 MHz ( period = 23.495 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a30~portb_address_reg4 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.742 ns ;
-; N/A ; 42.56 MHz ( period = 23.495 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a30~portb_address_reg5 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.742 ns ;
-; N/A ; 42.56 MHz ( period = 23.495 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a30~portb_address_reg6 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.742 ns ;
-; N/A ; 42.56 MHz ( period = 23.495 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a30~portb_address_reg7 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.742 ns ;
-; N/A ; 42.56 MHz ( period = 23.495 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a30~portb_address_reg8 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.742 ns ;
-; N/A ; 42.56 MHz ( period = 23.495 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a30~portb_address_reg9 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.742 ns ;
-; N/A ; 42.56 MHz ( period = 23.495 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a30~portb_address_reg10 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.742 ns ;
-; N/A ; 42.58 MHz ( period = 23.484 ns ) ; writeback_stage:writeback_st|wb_reg.address[18] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 23.223 ns ;
-; N/A ; 42.59 MHz ( period = 23.479 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; execute_stage:exec_st|reg.result[9] ; sys_clk ; sys_clk ; None ; None ; 23.209 ns ;
-; N/A ; 42.61 MHz ( period = 23.466 ns ) ; writeback_stage:writeback_st|wb_reg.address[22] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 23.205 ns ;
-; N/A ; 42.63 MHz ( period = 23.459 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a6~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.208 ns ;
-; N/A ; 42.64 MHz ( period = 23.451 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a19~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.169 ns ;
-; N/A ; 42.65 MHz ( period = 23.446 ns ) ; writeback_stage:writeback_st|wb_reg.address[16] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 23.185 ns ;
-; N/A ; 42.67 MHz ( period = 23.434 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[12] ; sys_clk ; sys_clk ; None ; None ; 23.114 ns ;
-; N/A ; 42.69 MHz ( period = 23.427 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~portb_address_reg0 ; sys_clk ; sys_clk ; None ; None ; 23.117 ns ;
-; N/A ; 42.70 MHz ( period = 23.419 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[16] ; sys_clk ; sys_clk ; None ; None ; 23.099 ns ;
-; N/A ; 42.70 MHz ( period = 23.419 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a30~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.172 ns ;
-; N/A ; 42.71 MHz ( period = 23.414 ns ) ; writeback_stage:writeback_st|wb_reg.address[29] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 23.153 ns ;
-; N/A ; 42.72 MHz ( period = 23.408 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a29~portb_address_reg0 ; sys_clk ; sys_clk ; None ; None ; 23.089 ns ;
-; N/A ; 42.73 MHz ( period = 23.402 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a19~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.116 ns ;
-; N/A ; 42.73 MHz ( period = 23.402 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a29~porta_address_reg0 ; sys_clk ; sys_clk ; None ; None ; 23.087 ns ;
-; N/A ; 42.73 MHz ( period = 23.401 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a2~porta_address_reg0 ; sys_clk ; sys_clk ; None ; None ; 23.086 ns ;
-; N/A ; 42.74 MHz ( period = 23.400 ns ) ; writeback_stage:writeback_st|wb_reg.address[26] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 23.139 ns ;
-; N/A ; 42.74 MHz ( period = 23.398 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a12~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.151 ns ;
-; N/A ; 42.74 MHz ( period = 23.395 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a10~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.148 ns ;
-; N/A ; 42.75 MHz ( period = 23.394 ns ) ; writeback_stage:writeback_st|wb_reg.address[21] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a24~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.012 ns ;
-; N/A ; 42.75 MHz ( period = 23.393 ns ) ; writeback_stage:writeback_st|wb_reg.address[15] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 23.132 ns ;
-; N/A ; 42.76 MHz ( period = 23.388 ns ) ; writeback_stage:writeback_st|wb_reg.address[21] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a16~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.006 ns ;
-; N/A ; 42.78 MHz ( period = 23.375 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a2~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.060 ns ;
-; N/A ; 42.79 MHz ( period = 23.370 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a30~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.119 ns ;
-; N/A ; 42.80 MHz ( period = 23.365 ns ) ; writeback_stage:writeback_st|wb_reg.address[21] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a29~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.050 ns ;
-; N/A ; 42.80 MHz ( period = 23.363 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a16~porta_we_reg ; sys_clk ; sys_clk ; None ; None ; 22.981 ns ;
-; N/A ; 42.82 MHz ( period = 23.352 ns ) ; writeback_stage:writeback_st|wb_reg.address[21] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.046 ns ;
-; N/A ; 42.83 MHz ( period = 23.350 ns ) ; writeback_stage:writeback_st|wb_reg.address[18] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a24~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.968 ns ;
-; N/A ; 42.83 MHz ( period = 23.349 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a12~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.098 ns ;
-; N/A ; 42.83 MHz ( period = 23.346 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a10~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.095 ns ;
-; N/A ; 42.84 MHz ( period = 23.345 ns ) ; writeback_stage:writeback_st|wb_reg.address[21] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a24~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.959 ns ;
-; N/A ; 42.84 MHz ( period = 23.344 ns ) ; writeback_stage:writeback_st|wb_reg.address[18] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a16~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.962 ns ;
-; N/A ; 42.85 MHz ( period = 23.339 ns ) ; writeback_stage:writeback_st|wb_reg.address[21] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a16~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.953 ns ;
-; N/A ; 42.85 MHz ( period = 23.335 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.015 ns ;
-; N/A ; 42.87 MHz ( period = 23.327 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a2~portb_address_reg0 ; sys_clk ; sys_clk ; None ; None ; 23.008 ns ;
-; N/A ; 42.87 MHz ( period = 23.326 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a2~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.007 ns ;
-; N/A ; 42.88 MHz ( period = 23.321 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a7~porta_we_reg ; sys_clk ; sys_clk ; None ; None ; 23.006 ns ;
-; N/A ; 42.88 MHz ( period = 23.321 ns ) ; writeback_stage:writeback_st|wb_reg.address[18] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a29~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.006 ns ;
-; N/A ; 42.89 MHz ( period = 23.317 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[25] ; sys_clk ; sys_clk ; None ; None ; 22.997 ns ;
-; N/A ; 42.89 MHz ( period = 23.316 ns ) ; writeback_stage:writeback_st|wb_reg.address[21] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a29~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.997 ns ;
-; N/A ; 42.90 MHz ( period = 23.308 ns ) ; writeback_stage:writeback_st|wb_reg.address[18] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.002 ns ;
-; N/A ; 42.91 MHz ( period = 23.303 ns ) ; writeback_stage:writeback_st|wb_reg.address[21] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.993 ns ;
-; N/A ; 42.92 MHz ( period = 23.301 ns ) ; writeback_stage:writeback_st|wb_reg.address[18] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a24~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.915 ns ;
-; N/A ; 42.93 MHz ( period = 23.295 ns ) ; writeback_stage:writeback_st|wb_reg.address[18] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a16~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.909 ns ;
-; N/A ; 42.93 MHz ( period = 23.294 ns ) ; writeback_stage:writeback_st|wb_reg.address[30] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 23.033 ns ;
-; N/A ; 42.97 MHz ( period = 23.272 ns ) ; writeback_stage:writeback_st|wb_reg.address[18] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a29~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.953 ns ;
-; N/A ; 42.97 MHz ( period = 23.271 ns ) ; writeback_stage:writeback_st|wb_reg.address[21] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~porta_address_reg0 ; sys_clk ; sys_clk ; None ; None ; 22.965 ns ;
-; N/A ; 42.98 MHz ( period = 23.269 ns ) ; writeback_stage:writeback_st|wb_reg.address[21] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a7~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.954 ns ;
-; N/A ; 42.99 MHz ( period = 23.259 ns ) ; writeback_stage:writeback_st|wb_reg.address[18] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.949 ns ;
-; N/A ; 43.00 MHz ( period = 23.254 ns ) ; writeback_stage:writeback_st|wb_reg.address[19] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 22.993 ns ;
-; N/A ; 43.00 MHz ( period = 23.254 ns ) ; writeback_stage:writeback_st|wb_reg.address[11] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.993 ns ;
-; N/A ; 43.01 MHz ( period = 23.248 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[23] ; sys_clk ; sys_clk ; None ; None ; 22.928 ns ;
-; N/A ; 43.02 MHz ( period = 23.246 ns ) ; writeback_stage:writeback_st|wb_reg.address[21] ; execute_stage:exec_st|reg.result[15] ; sys_clk ; sys_clk ; None ; None ; 22.985 ns ;
-; N/A ; 43.05 MHz ( period = 23.227 ns ) ; writeback_stage:writeback_st|wb_reg.address[18] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~porta_address_reg0 ; sys_clk ; sys_clk ; None ; None ; 22.921 ns ;
-; N/A ; 43.06 MHz ( period = 23.225 ns ) ; writeback_stage:writeback_st|wb_reg.address[18] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a7~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.910 ns ;
-; N/A ; 43.06 MHz ( period = 23.224 ns ) ; writeback_stage:writeback_st|wb_reg.address[27] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 22.963 ns ;
-; N/A ; 43.06 MHz ( period = 23.221 ns ) ; writeback_stage:writeback_st|wb_reg.address[20] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a24~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.839 ns ;
-; N/A ; 43.07 MHz ( period = 23.220 ns ) ; writeback_stage:writeback_st|wb_reg.address[21] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a7~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.901 ns ;
-; N/A ; 43.08 MHz ( period = 23.215 ns ) ; writeback_stage:writeback_st|wb_reg.address[20] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a16~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.833 ns ;
-; N/A ; 43.08 MHz ( period = 23.212 ns ) ; writeback_stage:writeback_st|wb_reg.address[2] ; execute_stage:exec_st|reg.result[15] ; sys_clk ; sys_clk ; None ; None ; 22.927 ns ;
-; N/A ; 43.09 MHz ( period = 23.205 ns ) ; writeback_stage:writeback_st|wb_reg.address[14] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 22.944 ns ;
-; N/A ; 43.10 MHz ( period = 23.202 ns ) ; writeback_stage:writeback_st|wb_reg.address[18] ; execute_stage:exec_st|reg.result[15] ; sys_clk ; sys_clk ; None ; None ; 22.941 ns ;
-; N/A ; 43.10 MHz ( period = 23.202 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a14~porta_address_reg4 ; sys_clk ; sys_clk ; None ; None ; 22.879 ns ;
-; N/A ; 43.10 MHz ( period = 23.201 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[7] ; sys_clk ; sys_clk ; None ; None ; 22.881 ns ;
-; N/A ; 43.11 MHz ( period = 23.198 ns ) ; writeback_stage:writeback_st|wb_reg.address[12] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a24~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.816 ns ;
-; N/A ; 43.12 MHz ( period = 23.193 ns ) ; writeback_stage:writeback_st|wb_reg.address[5] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 22.941 ns ;
-; N/A ; 43.12 MHz ( period = 23.192 ns ) ; writeback_stage:writeback_st|wb_reg.address[12] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a16~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.810 ns ;
-; N/A ; 43.12 MHz ( period = 23.192 ns ) ; writeback_stage:writeback_st|wb_reg.address[20] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a29~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.877 ns ;
-; N/A ; 43.13 MHz ( period = 23.184 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a21~porta_address_reg4 ; sys_clk ; sys_clk ; None ; None ; 22.861 ns ;
-; N/A ; 43.14 MHz ( period = 23.180 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[1] ; sys_clk ; sys_clk ; None ; None ; 22.919 ns ;
-; N/A ; 43.14 MHz ( period = 23.179 ns ) ; writeback_stage:writeback_st|wb_reg.address[20] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.873 ns ;
-; N/A ; 43.14 MHz ( period = 23.178 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a14~portb_address_reg0 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.501 ns ;
-; N/A ; 43.14 MHz ( period = 23.178 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a14~portb_address_reg1 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.501 ns ;
-; N/A ; 43.14 MHz ( period = 23.178 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a14~portb_address_reg2 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.501 ns ;
-; N/A ; 43.14 MHz ( period = 23.178 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a14~portb_address_reg3 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.501 ns ;
-; N/A ; 43.14 MHz ( period = 23.178 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a14~portb_address_reg4 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.501 ns ;
-; N/A ; 43.14 MHz ( period = 23.178 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a14~portb_address_reg5 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.501 ns ;
-; N/A ; 43.14 MHz ( period = 23.178 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a14~portb_address_reg6 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.501 ns ;
-; N/A ; 43.14 MHz ( period = 23.178 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a14~portb_address_reg7 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.501 ns ;
-; N/A ; 43.14 MHz ( period = 23.178 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a14~portb_address_reg8 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.501 ns ;
-; N/A ; 43.14 MHz ( period = 23.178 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a14~portb_address_reg9 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.501 ns ;
-; N/A ; 43.14 MHz ( period = 23.178 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a14~portb_address_reg10 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.501 ns ;
-; N/A ; 43.15 MHz ( period = 23.176 ns ) ; writeback_stage:writeback_st|wb_reg.address[18] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a7~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.857 ns ;
-; N/A ; 43.15 MHz ( period = 23.173 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a21~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.850 ns ;
-; N/A ; 43.16 MHz ( period = 23.172 ns ) ; writeback_stage:writeback_st|wb_reg.address[20] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a24~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.786 ns ;
-; N/A ; 43.16 MHz ( period = 23.169 ns ) ; writeback_stage:writeback_st|wb_reg.address[12] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a29~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.854 ns ;
-; N/A ; 43.17 MHz ( period = 23.166 ns ) ; writeback_stage:writeback_st|wb_reg.address[20] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a16~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.780 ns ;
-; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ;
-+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; tsu ;
-+-------+--------------+------------+---------+------------------------------------------------------------------------------------------------------------------------------+----------+
-; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
-+-------+--------------+------------+---------+------------------------------------------------------------------------------------------------------------------------------+----------+
-; N/A ; None ; 18.145 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ;
-; N/A ; None ; 18.070 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[1] ; sys_clk ;
-; N/A ; None ; 17.886 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[15] ; sys_clk ;
-; N/A ; None ; 17.811 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[7] ; sys_clk ;
-; N/A ; None ; 17.810 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[22] ; sys_clk ;
-; N/A ; None ; 17.809 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[5] ; sys_clk ;
-; N/A ; None ; 17.808 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[31] ; sys_clk ;
-; N/A ; None ; 17.807 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[17] ; sys_clk ;
-; N/A ; None ; 17.805 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[4] ; sys_clk ;
-; N/A ; None ; 17.802 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[16] ; sys_clk ;
-; N/A ; None ; 17.795 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[20] ; sys_clk ;
-; N/A ; None ; 17.790 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[21] ; sys_clk ;
-; N/A ; None ; 17.651 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[26] ; sys_clk ;
-; N/A ; None ; 17.651 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[19] ; sys_clk ;
-; N/A ; None ; 17.605 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[27] ; sys_clk ;
-; N/A ; None ; 17.604 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[23] ; sys_clk ;
-; N/A ; None ; 17.600 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[6] ; sys_clk ;
-; N/A ; None ; 17.598 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[24] ; sys_clk ;
-; N/A ; None ; 17.595 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[25] ; sys_clk ;
-; N/A ; None ; 17.141 ns ; sys_res ; execute_stage:exec_st|reg.result[26] ; sys_clk ;
-; N/A ; None ; 16.690 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a16~porta_we_reg ; sys_clk ;
-; N/A ; None ; 16.648 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a7~porta_we_reg ; sys_clk ;
-; N/A ; None ; 16.185 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a24~porta_we_reg ; sys_clk ;
-; N/A ; None ; 16.144 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a29~porta_we_reg ; sys_clk ;
-; N/A ; None ; 16.119 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~porta_we_reg ; sys_clk ;
-; N/A ; None ; 15.774 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a6~porta_we_reg ; sys_clk ;
-; N/A ; None ; 15.667 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.carry ; sys_clk ;
-; N/A ; None ; 15.650 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a2~porta_we_reg ; sys_clk ;
-; N/A ; None ; 15.623 ns ; sys_res ; execute_stage:exec_st|reg.result[24] ; sys_clk ;
-; N/A ; None ; 15.511 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a14~porta_we_reg ; sys_clk ;
-; N/A ; None ; 15.506 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a25~porta_we_reg ; sys_clk ;
-; N/A ; None ; 15.491 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a21~porta_we_reg ; sys_clk ;
-; N/A ; None ; 15.437 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a8~porta_we_reg ; sys_clk ;
-; N/A ; None ; 15.370 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a19~porta_we_reg ; sys_clk ;
-; N/A ; None ; 15.343 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a12~porta_we_reg ; sys_clk ;
-; N/A ; None ; 15.337 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a30~porta_we_reg ; sys_clk ;
-; N/A ; None ; 15.243 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a10~porta_we_reg ; sys_clk ;
-; N/A ; None ; 15.224 ns ; sys_res ; execute_stage:exec_st|reg.result[21] ; sys_clk ;
-; N/A ; None ; 15.223 ns ; sys_res ; execute_stage:exec_st|reg.result[22] ; sys_clk ;
-; N/A ; None ; 15.185 ns ; sys_res ; execute_stage:exec_st|reg.result[19] ; sys_clk ;
-; N/A ; None ; 14.915 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; sys_clk ;
-; N/A ; None ; 14.897 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a20~porta_we_reg ; sys_clk ;
-; N/A ; None ; 14.795 ns ; sys_res ; execute_stage:exec_st|reg.result[20] ; sys_clk ;
-; N/A ; None ; 14.407 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; sys_clk ;
-; N/A ; None ; 14.258 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; sys_clk ;
-; N/A ; None ; 14.258 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][24] ; sys_clk ;
-; N/A ; None ; 14.123 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][25] ; sys_clk ;
-; N/A ; None ; 14.123 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][22] ; sys_clk ;
-; N/A ; None ; 14.123 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][21] ; sys_clk ;
-; N/A ; None ; 14.112 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; sys_clk ;
-; N/A ; None ; 13.407 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][26] ; sys_clk ;
-; N/A ; None ; 13.406 ns ; sys_res ; execute_stage:exec_st|reg.result[12] ; sys_clk ;
-; N/A ; None ; 13.400 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][29] ; sys_clk ;
-; N/A ; None ; 13.400 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][28] ; sys_clk ;
-; N/A ; None ; 13.400 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][27] ; sys_clk ;
-; N/A ; None ; 13.320 ns ; sys_res ; execute_stage:exec_st|reg.result[11] ; sys_clk ;
-; N/A ; None ; 13.318 ns ; sys_res ; execute_stage:exec_st|reg.result[10] ; sys_clk ;
-; N/A ; None ; 13.316 ns ; sys_res ; execute_stage:exec_st|reg.result[8] ; sys_clk ;
-; N/A ; None ; 13.212 ns ; sys_res ; execute_stage:exec_st|reg.result[9] ; sys_clk ;
-; N/A ; None ; 13.097 ns ; sys_res ; execute_stage:exec_st|reg.result[1] ; sys_clk ;
-; N/A ; None ; 12.997 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; sys_clk ;
-; N/A ; None ; 12.997 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; sys_clk ;
-; N/A ; None ; 12.909 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; sys_clk ;
-; N/A ; None ; 12.909 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; sys_clk ;
-; N/A ; None ; 12.794 ns ; sys_res ; execute_stage:exec_st|reg.result[2] ; sys_clk ;
-; N/A ; None ; 12.776 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][19] ; sys_clk ;
-; N/A ; None ; 12.776 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][20] ; sys_clk ;
-; N/A ; None ; 12.776 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][14] ; sys_clk ;
-; N/A ; None ; 12.776 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][18] ; sys_clk ;
-; N/A ; None ; 12.776 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][17] ; sys_clk ;
-; N/A ; None ; 12.776 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][16] ; sys_clk ;
-; N/A ; None ; 12.776 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][15] ; sys_clk ;
-; N/A ; None ; 12.705 ns ; sys_res ; execute_stage:exec_st|reg.result[15] ; sys_clk ;
-; N/A ; None ; 12.661 ns ; sys_res ; execute_stage:exec_st|reg.result[13] ; sys_clk ;
-; N/A ; None ; 12.495 ns ; sys_res ; execute_stage:exec_st|reg.result[0] ; sys_clk ;
-; N/A ; None ; 12.360 ns ; sys_res ; execute_stage:exec_st|reg.result[3] ; sys_clk ;
-; N/A ; None ; 12.359 ns ; sys_res ; execute_stage:exec_st|reg.result[6] ; sys_clk ;
-; N/A ; None ; 12.357 ns ; sys_res ; execute_stage:exec_st|reg.result[4] ; sys_clk ;
-; N/A ; None ; 12.335 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][13] ; sys_clk ;
-; N/A ; None ; 12.335 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][12] ; sys_clk ;
-; N/A ; None ; 12.330 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; sys_clk ;
-; N/A ; None ; 12.330 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; sys_clk ;
-; N/A ; None ; 12.330 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; sys_clk ;
-; N/A ; None ; 12.307 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][23] ; sys_clk ;
-; N/A ; None ; 12.215 ns ; sys_res ; execute_stage:exec_st|reg.result[17] ; sys_clk ;
-; N/A ; None ; 12.114 ns ; sys_res ; execute_stage:exec_st|reg.result[31] ; sys_clk ;
-; N/A ; None ; 12.113 ns ; sys_res ; execute_stage:exec_st|reg.result[25] ; sys_clk ;
-; N/A ; None ; 12.112 ns ; sys_res ; execute_stage:exec_st|reg.result[27] ; sys_clk ;
-; N/A ; None ; 12.105 ns ; sys_res ; execute_stage:exec_st|reg.result[29] ; sys_clk ;
-; N/A ; None ; 12.084 ns ; sys_res ; execute_stage:exec_st|reg.result[18] ; sys_clk ;
-; N/A ; None ; 12.084 ns ; sys_res ; execute_stage:exec_st|reg.result[28] ; sys_clk ;
-; N/A ; None ; 12.072 ns ; sys_res ; execute_stage:exec_st|reg.result[5] ; sys_clk ;
-; N/A ; None ; 12.019 ns ; sys_res ; execute_stage:exec_st|reg.result[30] ; sys_clk ;
-; N/A ; None ; 11.981 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][11] ; sys_clk ;
-; N/A ; None ; 11.974 ns ; sys_res ; execute_stage:exec_st|reg.result[14] ; sys_clk ;
-; N/A ; None ; 11.971 ns ; sys_res ; execute_stage:exec_st|reg.result[16] ; sys_clk ;
-; N/A ; None ; 11.937 ns ; sys_res ; execute_stage:exec_st|reg.result[7] ; sys_clk ;
-; N/A ; None ; 11.787 ns ; sys_res ; execute_stage:exec_st|reg.result[23] ; sys_clk ;
-; N/A ; None ; 11.158 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[4] ; sys_clk ;
-; N/A ; None ; 11.054 ns ; sys_res ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; sys_clk ;
-; N/A ; None ; 10.345 ns ; sys_res ; writeback_stage:writeback_st|wb_reg.dmem_en ; sys_clk ;
-; N/A ; None ; 10.180 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[3] ; sys_clk ;
-; N/A ; None ; 10.094 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[6] ; sys_clk ;
-; N/A ; None ; 10.094 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[5] ; sys_clk ;
-; N/A ; None ; 9.929 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[10] ; sys_clk ;
-; N/A ; None ; 9.926 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[7] ; sys_clk ;
-; N/A ; None ; 9.926 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[8] ; sys_clk ;
-; N/A ; None ; 9.904 ns ; sys_res ; execute_stage:exec_st|reg.wr_en ; sys_clk ;
-; N/A ; None ; 9.903 ns ; sys_res ; execute_stage:exec_st|reg.alu_jump ; sys_clk ;
-; N/A ; None ; 9.873 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[0] ; sys_clk ;
-; N/A ; None ; 9.605 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[6] ; sys_clk ;
-; N/A ; None ; 9.403 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[9] ; sys_clk ;
-; N/A ; None ; 9.340 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[1] ; sys_clk ;
-; N/A ; None ; 9.338 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[0] ; sys_clk ;
-; N/A ; None ; 9.259 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[7] ; sys_clk ;
-; N/A ; None ; 9.257 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[2] ; sys_clk ;
-; N/A ; None ; 9.012 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[2] ; sys_clk ;
-; N/A ; None ; 8.582 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[5] ; sys_clk ;
-; N/A ; None ; 7.904 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|new_rx_data ; sys_clk ;
-; N/A ; None ; 7.904 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|bus_rx_int ; sys_clk ;
-; N/A ; None ; 6.963 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[3] ; sys_clk ;
-; N/A ; None ; 6.869 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[1] ; sys_clk ;
-; N/A ; None ; 6.867 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[4] ; sys_clk ;
-; N/A ; None ; 5.680 ns ; bus_rx ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|sync[1] ; sys_clk ;
-+-------+--------------+------------+---------+------------------------------------------------------------------------------------------------------------------------------+----------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------+
-; tco ;
-+-------+--------------+------------+------------------------------------------------------------------------------------+----------+------------+
-; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
-+-------+--------------+------------+------------------------------------------------------------------------------------+----------+------------+
-; N/A ; None ; 10.677 ns ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; bus_tx ; sys_clk ;
-; N/A ; None ; 10.627 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[2] ; sseg0[2] ; sys_clk ;
-; N/A ; None ; 9.877 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[1] ; sseg1[1] ; sys_clk ;
-; N/A ; None ; 9.406 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[0] ; sseg2[0] ; sys_clk ;
-; N/A ; None ; 9.395 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[4] ; sseg2[4] ; sys_clk ;
-; N/A ; None ; 9.182 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[6] ; sseg1[6] ; sys_clk ;
-; N/A ; None ; 9.091 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[2] ; sseg1[2] ; sys_clk ;
-; N/A ; None ; 9.079 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[0] ; sseg1[0] ; sys_clk ;
-; N/A ; None ; 8.940 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[3] ; sseg1[3] ; sys_clk ;
-; N/A ; None ; 8.778 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[6] ; sseg0[6] ; sys_clk ;
-; N/A ; None ; 8.704 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[2] ; sseg2[2] ; sys_clk ;
-; N/A ; None ; 8.694 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[3] ; sseg3[3] ; sys_clk ;
-; N/A ; None ; 8.693 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[2] ; sseg3[2] ; sys_clk ;
-; N/A ; None ; 8.684 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[6] ; sseg2[6] ; sys_clk ;
-; N/A ; None ; 8.663 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[4] ; sseg0[4] ; sys_clk ;
-; N/A ; None ; 8.607 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[1] ; sseg3[1] ; sys_clk ;
-; N/A ; None ; 8.606 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[5] ; sseg3[5] ; sys_clk ;
-; N/A ; None ; 8.605 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[4] ; sseg3[4] ; sys_clk ;
-; N/A ; None ; 8.592 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[3] ; sseg0[3] ; sys_clk ;
-; N/A ; None ; 8.503 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[6] ; sseg3[6] ; sys_clk ;
-; N/A ; None ; 8.484 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[1] ; sseg0[1] ; sys_clk ;
-; N/A ; None ; 8.475 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[0] ; sseg0[0] ; sys_clk ;
-; N/A ; None ; 8.230 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[5] ; sseg0[5] ; sys_clk ;
-; N/A ; None ; 8.188 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[0] ; sseg3[0] ; sys_clk ;
-; N/A ; None ; 7.759 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[5] ; sseg2[5] ; sys_clk ;
-; N/A ; None ; 7.360 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[3] ; sseg2[3] ; sys_clk ;
-; N/A ; None ; 7.356 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[1] ; sseg2[1] ; sys_clk ;
-; N/A ; None ; 7.295 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[4] ; sseg1[4] ; sys_clk ;
-; N/A ; None ; 7.293 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[5] ; sseg1[5] ; sys_clk ;
-+-------+--------------+------------+------------------------------------------------------------------------------------+----------+------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; th ;
-+---------------+-------------+------------+---------+------------------------------------------------------------------------------------------------------------------------------+----------+
-; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
-+---------------+-------------+------------+---------+------------------------------------------------------------------------------------------------------------------------------+----------+
-; N/A ; None ; -5.628 ns ; bus_rx ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|sync[1] ; sys_clk ;
-; N/A ; None ; -6.815 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[4] ; sys_clk ;
-; N/A ; None ; -6.817 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[1] ; sys_clk ;
-; N/A ; None ; -6.911 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[3] ; sys_clk ;
-; N/A ; None ; -7.852 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|new_rx_data ; sys_clk ;
-; N/A ; None ; -7.852 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|bus_rx_int ; sys_clk ;
-; N/A ; None ; -8.530 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[5] ; sys_clk ;
-; N/A ; None ; -8.960 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[2] ; sys_clk ;
-; N/A ; None ; -9.205 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[2] ; sys_clk ;
-; N/A ; None ; -9.207 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[7] ; sys_clk ;
-; N/A ; None ; -9.286 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[0] ; sys_clk ;
-; N/A ; None ; -9.288 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[1] ; sys_clk ;
-; N/A ; None ; -9.351 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[9] ; sys_clk ;
-; N/A ; None ; -9.553 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[6] ; sys_clk ;
-; N/A ; None ; -9.821 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[0] ; sys_clk ;
-; N/A ; None ; -9.851 ns ; sys_res ; execute_stage:exec_st|reg.alu_jump ; sys_clk ;
-; N/A ; None ; -9.852 ns ; sys_res ; execute_stage:exec_st|reg.wr_en ; sys_clk ;
-; N/A ; None ; -9.874 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[7] ; sys_clk ;
-; N/A ; None ; -9.874 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[8] ; sys_clk ;
-; N/A ; None ; -9.877 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[10] ; sys_clk ;
-; N/A ; None ; -10.042 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[6] ; sys_clk ;
-; N/A ; None ; -10.042 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[5] ; sys_clk ;
-; N/A ; None ; -10.128 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[3] ; sys_clk ;
-; N/A ; None ; -10.293 ns ; sys_res ; writeback_stage:writeback_st|wb_reg.dmem_en ; sys_clk ;
-; N/A ; None ; -11.002 ns ; sys_res ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; sys_clk ;
-; N/A ; None ; -11.106 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[4] ; sys_clk ;
-; N/A ; None ; -11.409 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[23] ; sys_clk ;
-; N/A ; None ; -11.410 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[25] ; sys_clk ;
-; N/A ; None ; -11.410 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[27] ; sys_clk ;
-; N/A ; None ; -11.412 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[24] ; sys_clk ;
-; N/A ; None ; -11.413 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[6] ; sys_clk ;
-; N/A ; None ; -11.494 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[15] ; sys_clk ;
-; N/A ; None ; -11.528 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[22] ; sys_clk ;
-; N/A ; None ; -11.529 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[7] ; sys_clk ;
-; N/A ; None ; -11.532 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[5] ; sys_clk ;
-; N/A ; None ; -11.536 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[31] ; sys_clk ;
-; N/A ; None ; -11.539 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[17] ; sys_clk ;
-; N/A ; None ; -11.541 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[4] ; sys_clk ;
-; N/A ; None ; -11.542 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[16] ; sys_clk ;
-; N/A ; None ; -11.544 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[20] ; sys_clk ;
-; N/A ; None ; -11.545 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[21] ; sys_clk ;
-; N/A ; None ; -11.583 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[19] ; sys_clk ;
-; N/A ; None ; -11.585 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[26] ; sys_clk ;
-; N/A ; None ; -11.735 ns ; sys_res ; execute_stage:exec_st|reg.result[23] ; sys_clk ;
-; N/A ; None ; -11.885 ns ; sys_res ; execute_stage:exec_st|reg.result[7] ; sys_clk ;
-; N/A ; None ; -11.919 ns ; sys_res ; execute_stage:exec_st|reg.result[16] ; sys_clk ;
-; N/A ; None ; -11.922 ns ; sys_res ; execute_stage:exec_st|reg.result[14] ; sys_clk ;
-; N/A ; None ; -11.929 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][11] ; sys_clk ;
-; N/A ; None ; -11.967 ns ; sys_res ; execute_stage:exec_st|reg.result[30] ; sys_clk ;
-; N/A ; None ; -12.020 ns ; sys_res ; execute_stage:exec_st|reg.result[5] ; sys_clk ;
-; N/A ; None ; -12.032 ns ; sys_res ; execute_stage:exec_st|reg.result[18] ; sys_clk ;
-; N/A ; None ; -12.032 ns ; sys_res ; execute_stage:exec_st|reg.result[28] ; sys_clk ;
-; N/A ; None ; -12.053 ns ; sys_res ; execute_stage:exec_st|reg.result[29] ; sys_clk ;
-; N/A ; None ; -12.060 ns ; sys_res ; execute_stage:exec_st|reg.result[27] ; sys_clk ;
-; N/A ; None ; -12.061 ns ; sys_res ; execute_stage:exec_st|reg.result[25] ; sys_clk ;
-; N/A ; None ; -12.062 ns ; sys_res ; execute_stage:exec_st|reg.result[31] ; sys_clk ;
-; N/A ; None ; -12.163 ns ; sys_res ; execute_stage:exec_st|reg.result[17] ; sys_clk ;
-; N/A ; None ; -12.255 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][23] ; sys_clk ;
-; N/A ; None ; -12.278 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; sys_clk ;
-; N/A ; None ; -12.278 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; sys_clk ;
-; N/A ; None ; -12.278 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; sys_clk ;
-; N/A ; None ; -12.283 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][13] ; sys_clk ;
-; N/A ; None ; -12.283 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][12] ; sys_clk ;
-; N/A ; None ; -12.305 ns ; sys_res ; execute_stage:exec_st|reg.result[4] ; sys_clk ;
-; N/A ; None ; -12.307 ns ; sys_res ; execute_stage:exec_st|reg.result[6] ; sys_clk ;
-; N/A ; None ; -12.308 ns ; sys_res ; execute_stage:exec_st|reg.result[3] ; sys_clk ;
-; N/A ; None ; -12.443 ns ; sys_res ; execute_stage:exec_st|reg.result[0] ; sys_clk ;
-; N/A ; None ; -12.609 ns ; sys_res ; execute_stage:exec_st|reg.result[13] ; sys_clk ;
-; N/A ; None ; -12.653 ns ; sys_res ; execute_stage:exec_st|reg.result[15] ; sys_clk ;
-; N/A ; None ; -12.724 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][19] ; sys_clk ;
-; N/A ; None ; -12.724 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][20] ; sys_clk ;
-; N/A ; None ; -12.724 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][14] ; sys_clk ;
-; N/A ; None ; -12.724 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][18] ; sys_clk ;
-; N/A ; None ; -12.724 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][17] ; sys_clk ;
-; N/A ; None ; -12.724 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][16] ; sys_clk ;
-; N/A ; None ; -12.724 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][15] ; sys_clk ;
-; N/A ; None ; -12.742 ns ; sys_res ; execute_stage:exec_st|reg.result[2] ; sys_clk ;
-; N/A ; None ; -12.857 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; sys_clk ;
-; N/A ; None ; -12.857 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; sys_clk ;
-; N/A ; None ; -12.945 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; sys_clk ;
-; N/A ; None ; -12.945 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; sys_clk ;
-; N/A ; None ; -13.045 ns ; sys_res ; execute_stage:exec_st|reg.result[1] ; sys_clk ;
-; N/A ; None ; -13.160 ns ; sys_res ; execute_stage:exec_st|reg.result[9] ; sys_clk ;
-; N/A ; None ; -13.264 ns ; sys_res ; execute_stage:exec_st|reg.result[8] ; sys_clk ;
-; N/A ; None ; -13.266 ns ; sys_res ; execute_stage:exec_st|reg.result[10] ; sys_clk ;
-; N/A ; None ; -13.268 ns ; sys_res ; execute_stage:exec_st|reg.result[11] ; sys_clk ;
-; N/A ; None ; -13.348 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][29] ; sys_clk ;
-; N/A ; None ; -13.348 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][28] ; sys_clk ;
-; N/A ; None ; -13.348 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][27] ; sys_clk ;
-; N/A ; None ; -13.354 ns ; sys_res ; execute_stage:exec_st|reg.result[12] ; sys_clk ;
-; N/A ; None ; -13.355 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][26] ; sys_clk ;
-; N/A ; None ; -13.682 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[1] ; sys_clk ;
-; N/A ; None ; -14.060 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; sys_clk ;
-; N/A ; None ; -14.071 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][25] ; sys_clk ;
-; N/A ; None ; -14.071 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][22] ; sys_clk ;
-; N/A ; None ; -14.071 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][21] ; sys_clk ;
-; N/A ; None ; -14.206 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; sys_clk ;
-; N/A ; None ; -14.206 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][24] ; sys_clk ;
-; N/A ; None ; -14.355 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; sys_clk ;
-; N/A ; None ; -14.743 ns ; sys_res ; execute_stage:exec_st|reg.result[20] ; sys_clk ;
-; N/A ; None ; -14.749 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a20~porta_we_reg ; sys_clk ;
-; N/A ; None ; -14.863 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; sys_clk ;
-; N/A ; None ; -15.095 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a10~porta_we_reg ; sys_clk ;
-; N/A ; None ; -15.133 ns ; sys_res ; execute_stage:exec_st|reg.result[19] ; sys_clk ;
-; N/A ; None ; -15.171 ns ; sys_res ; execute_stage:exec_st|reg.result[22] ; sys_clk ;
-; N/A ; None ; -15.172 ns ; sys_res ; execute_stage:exec_st|reg.result[21] ; sys_clk ;
-; N/A ; None ; -15.189 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a30~porta_we_reg ; sys_clk ;
-; N/A ; None ; -15.195 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a12~porta_we_reg ; sys_clk ;
-; N/A ; None ; -15.222 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a19~porta_we_reg ; sys_clk ;
-; N/A ; None ; -15.289 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a8~porta_we_reg ; sys_clk ;
-; N/A ; None ; -15.343 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a21~porta_we_reg ; sys_clk ;
-; N/A ; None ; -15.358 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a25~porta_we_reg ; sys_clk ;
-; N/A ; None ; -15.363 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a14~porta_we_reg ; sys_clk ;
-; N/A ; None ; -15.502 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a2~porta_we_reg ; sys_clk ;
-; N/A ; None ; -15.571 ns ; sys_res ; execute_stage:exec_st|reg.result[24] ; sys_clk ;
-; N/A ; None ; -15.615 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.carry ; sys_clk ;
-; N/A ; None ; -15.626 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a6~porta_we_reg ; sys_clk ;
-; N/A ; None ; -15.971 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~porta_we_reg ; sys_clk ;
-; N/A ; None ; -15.996 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a29~porta_we_reg ; sys_clk ;
-; N/A ; None ; -16.037 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a24~porta_we_reg ; sys_clk ;
-; N/A ; None ; -16.500 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a7~porta_we_reg ; sys_clk ;
-; N/A ; None ; -16.542 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a16~porta_we_reg ; sys_clk ;
-; N/A ; None ; -17.089 ns ; sys_res ; execute_stage:exec_st|reg.result[26] ; sys_clk ;
-; N/A ; None ; -18.093 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ;
-+---------------+-------------+------------+---------+------------------------------------------------------------------------------------------------------------------------------+----------+
-
-
-+--------------------------+
-; Timing Analyzer Messages ;
-+--------------------------+
-Info: *******************************************************************
-Info: Running Quartus II Classic Timing Analyzer
- Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
- Info: Processing started: Sun Dec 19 20:36:50 2010
-Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off dt -c dt --timing_analysis_only
-Warning: Classic Timing Analyzer will not be available in a future release of the Quartus II software. Use the TimeQuest Timing Analyzer to run timing analysis on your design. Convert all the project settings and the timing constraints to TimeQuest Timing Analyzer equivalents.
-Warning: Found pins functioning as undefined clocks and/or memory enables
- Info: Assuming node "sys_clk" is an undefined clock
-Info: Clock "sys_clk" has Internal fmax of 36.95 MHz between source register "writeback_stage:writeback_st|wb_reg.dmem_en" and destination register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero" (period= 27.067 ns)
- Info: + Longest register to register delay is 26.747 ns
- Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y17_N9; Fanout = 91; REG Node = 'writeback_stage:writeback_st|wb_reg.dmem_en'
- Info: 2: + IC(1.734 ns) + CELL(0.590 ns) = 2.324 ns; Loc. = LC_X24_Y13_N7; Fanout = 8; COMB Node = 'writeback_stage:writeback_st|regfile_val[0]~3'
- Info: 3: + IC(3.282 ns) + CELL(0.590 ns) = 6.196 ns; Loc. = LC_X24_Y9_N9; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|regfile_val[0]~48'
- Info: 4: + IC(2.117 ns) + CELL(0.442 ns) = 8.755 ns; Loc. = LC_X29_Y17_N8; Fanout = 5; COMB Node = 'writeback_stage:writeback_st|regfile_val[0]~49'
- Info: 5: + IC(1.568 ns) + CELL(0.114 ns) = 10.437 ns; Loc. = LC_X31_Y15_N1; Fanout = 1; COMB Node = 'execute_stage:exec_st|right_operand[0]~18'
- Info: 6: + IC(0.182 ns) + CELL(0.114 ns) = 10.733 ns; Loc. = LC_X31_Y15_N2; Fanout = 105; COMB Node = 'execute_stage:exec_st|right_operand[0]~19'
- Info: 7: + IC(1.760 ns) + CELL(0.114 ns) = 12.607 ns; Loc. = LC_X28_Y14_N8; Fanout = 13; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst|ShiftLeft0~14'
- Info: 8: + IC(2.460 ns) + CELL(0.114 ns) = 15.181 ns; Loc. = LC_X29_Y14_N0; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst|ShiftRight0~15'
- Info: 9: + IC(0.400 ns) + CELL(0.442 ns) = 16.023 ns; Loc. = LC_X29_Y14_N6; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst|ShiftLeft0~31'
- Info: 10: + IC(3.419 ns) + CELL(0.114 ns) = 19.556 ns; Loc. = LC_X27_Y11_N7; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst|ShiftLeft0~60'
- Info: 11: + IC(0.459 ns) + CELL(0.292 ns) = 20.307 ns; Loc. = LC_X27_Y11_N0; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector11~0'
- Info: 12: + IC(0.423 ns) + CELL(0.114 ns) = 20.844 ns; Loc. = LC_X27_Y11_N6; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector11~1'
- Info: 13: + IC(1.211 ns) + CELL(0.292 ns) = 22.347 ns; Loc. = LC_X23_Y11_N1; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector11~2'
- Info: 14: + IC(0.182 ns) + CELL(0.114 ns) = 22.643 ns; Loc. = LC_X23_Y11_N2; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector11~5'
- Info: 15: + IC(0.456 ns) + CELL(0.292 ns) = 23.391 ns; Loc. = LC_X23_Y11_N4; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Equal0~1'
- Info: 16: + IC(2.074 ns) + CELL(0.114 ns) = 25.579 ns; Loc. = LC_X28_Y18_N2; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Equal0~2'
- Info: 17: + IC(0.430 ns) + CELL(0.738 ns) = 26.747 ns; Loc. = LC_X28_Y18_N6; Fanout = 1; REG Node = 'execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero'
- Info: Total cell delay = 4.590 ns ( 17.16 % )
- Info: Total interconnect delay = 22.157 ns ( 82.84 % )
- Info: - Smallest clock skew is -0.059 ns
- Info: + Shortest clock path from clock "sys_clk" to destination register is 3.187 ns
- Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 1098; CLK Node = 'sys_clk'
- Info: 2: + IC(1.007 ns) + CELL(0.711 ns) = 3.187 ns; Loc. = LC_X28_Y18_N6; Fanout = 1; REG Node = 'execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero'
- Info: Total cell delay = 2.180 ns ( 68.40 % )
- Info: Total interconnect delay = 1.007 ns ( 31.60 % )
- Info: - Longest clock path from clock "sys_clk" to source register is 3.246 ns
- Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 1098; CLK Node = 'sys_clk'
- Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X25_Y17_N9; Fanout = 91; REG Node = 'writeback_stage:writeback_st|wb_reg.dmem_en'
- Info: Total cell delay = 2.180 ns ( 67.16 % )
- Info: Total interconnect delay = 1.066 ns ( 32.84 % )
- Info: + Micro clock to output delay of source is 0.224 ns
- Info: + Micro setup delay of destination is 0.037 ns
-Info: tsu for register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero" (data pin = "sys_res", clock pin = "sys_clk") is 18.145 ns
- Info: + Longest pin to register delay is 21.295 ns
- Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_42; Fanout = 504; PIN Node = 'sys_res'
- Info: 2: + IC(9.198 ns) + CELL(0.442 ns) = 11.109 ns; Loc. = LC_X28_Y20_N7; Fanout = 7; COMB Node = 'execute_stage:exec_st|alu:alu_inst|\calc:cond_met~1'
- Info: 3: + IC(5.851 ns) + CELL(0.590 ns) = 17.550 ns; Loc. = LC_X25_Y16_N7; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|calc~0'
- Info: 4: + IC(2.878 ns) + CELL(0.867 ns) = 21.295 ns; Loc. = LC_X28_Y18_N6; Fanout = 1; REG Node = 'execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero'
- Info: Total cell delay = 3.368 ns ( 15.82 % )
- Info: Total interconnect delay = 17.927 ns ( 84.18 % )
- Info: + Micro setup delay of destination is 0.037 ns
- Info: - Shortest clock path from clock "sys_clk" to destination register is 3.187 ns
- Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 1098; CLK Node = 'sys_clk'
- Info: 2: + IC(1.007 ns) + CELL(0.711 ns) = 3.187 ns; Loc. = LC_X28_Y18_N6; Fanout = 1; REG Node = 'execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero'
- Info: Total cell delay = 2.180 ns ( 68.40 % )
- Info: Total interconnect delay = 1.007 ns ( 31.60 % )
-Info: tco from clock "sys_clk" to destination pin "bus_tx" through register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int" is 10.677 ns
- Info: + Longest clock path from clock "sys_clk" to source register is 3.111 ns
- Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 1098; CLK Node = 'sys_clk'
- Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X27_Y8_N4; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int'
- Info: Total cell delay = 2.180 ns ( 70.07 % )
- Info: Total interconnect delay = 0.931 ns ( 29.93 % )
- Info: + Micro clock to output delay of source is 0.224 ns
- Info: + Longest register to pin delay is 7.342 ns
- Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X27_Y8_N4; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int'
- Info: 2: + IC(5.218 ns) + CELL(2.124 ns) = 7.342 ns; Loc. = PIN_166; Fanout = 0; PIN Node = 'bus_tx'
- Info: Total cell delay = 2.124 ns ( 28.93 % )
- Info: Total interconnect delay = 5.218 ns ( 71.07 % )
-Info: th for register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|sync[1]" (data pin = "bus_rx", clock pin = "sys_clk") is -5.628 ns
- Info: + Longest clock path from clock "sys_clk" to destination register is 3.246 ns
- Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 1098; CLK Node = 'sys_clk'
- Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X22_Y18_N3; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|sync[1]'
- Info: Total cell delay = 2.180 ns ( 67.16 % )
- Info: Total interconnect delay = 1.066 ns ( 32.84 % )
- Info: + Micro hold delay of destination is 0.015 ns
- Info: - Shortest pin to register delay is 8.889 ns
- Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 1; PIN Node = 'bus_rx'
- Info: 2: + IC(7.111 ns) + CELL(0.309 ns) = 8.889 ns; Loc. = LC_X22_Y18_N3; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|sync[1]'
- Info: Total cell delay = 1.778 ns ( 20.00 % )
- Info: Total interconnect delay = 7.111 ns ( 80.00 % )
-Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
- Info: Peak virtual memory: 192 megabytes
- Info: Processing ended: Sun Dec 19 20:36:51 2010
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:01
-
-
+++ /dev/null
---------------------------------------------------------------------------------------
-Timing Analyzer Summary
---------------------------------------------------------------------------------------
-
-Type : Worst-case tsu
-Slack : N/A
-Required Time : None
-Actual Time : 18.145 ns
-From : sys_res
-To : execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero
-From Clock : --
-To Clock : sys_clk
-Failed Paths : 0
-
-Type : Worst-case tco
-Slack : N/A
-Required Time : None
-Actual Time : 10.677 ns
-From : writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int
-To : bus_tx
-From Clock : sys_clk
-To Clock : --
-Failed Paths : 0
-
-Type : Worst-case th
-Slack : N/A
-Required Time : None
-Actual Time : -5.628 ns
-From : bus_rx
-To : writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|sync[1]
-From Clock : --
-To Clock : sys_clk
-Failed Paths : 0
-
-Type : Clock Setup: 'sys_clk'
-Slack : N/A
-Required Time : None
-Actual Time : 36.95 MHz ( period = 27.067 ns )
-From : writeback_stage:writeback_st|wb_reg.dmem_en
-To : execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero
-From Clock : sys_clk
-To Clock : sys_clk
-Failed Paths : 0
-
-Type : Total number of failed paths
-Slack :
-Required Time :
-Actual Time :
-From :
-To :
-From Clock :
-To Clock :
-Failed Paths : 0
-
---------------------------------------------------------------------------------------
-
projects / calu.git / commitdiff