cpu/src/execute_stage_b.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.common_pkg.all;
   6 use work.alu_pkg.all;
   7
   8 architecture behav of execute_stage is
   9
  10 signal condition : condition_t;
  11 signal op_group : op_info_t;
  12 signal op_detail : op_opt_t;
  13 signal left_operand, right_operand : gp_register_t;
  14 signal alu_state, alu_nxt : alu_result_rec;
  15
  16 signal psw : status_rec;
  17
  18 begin
  19
  20 alu_inst : alu
  21 port map(clk, reset, condition, op_group,
  22         op_detail, left_operand, right_operand, alu_state, alu_nxt);
  23
  24 syn: process(sys_clk, reset)
  25
  26 begin
  27
  28         if (reset = RESET_VALUE) then
  29                 condition <=
  30         elsif rising_edge(sys_clk) then
  31
  32         end if;
  33
  34 end process;
  35
  36 asyn: process(reset,condition)
  37 begin
  38
  39         condition <= dec_instr.condition;
  40         op_group <= dec_instr.op_group;
  41         op_detail <= dec_instr.op_detail;
  42         left_operand <= dec_instr.src1;
  43         right_operand <= dec_instr.src2;
  44
  45         alu_state.status <= psw;
  46         alu_state.result_addr <= dec_instr.daddr;
  47         alu_state.brpr <= brpr;
  48         alu_state.reg_op <= '0';
  49         alu_state.mem_op <= '0';
  50         alu_state.
  51
  52         if reset = RESET_VALUE then
  53                 condition <= COND_NEVER;
  54         else
  55
  56         end if;
  57
  58 end process asyn;
  59
  60 end behav;
  61