--- writeback_st : writeback_stage
--- generic map(RESET_VALUE, '1', "altera")
--- port map(sys_clk, sys_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred,
--- vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
--- reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,
--- -- instruction memory program port :D
--- new_im_data, im_addr, im_data,
--- sseg0, sseg1, sseg2, sseg3, int_req);
---