cpu/src/core_top.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.common_pkg.all;
   6 use work.core_pkg.all;
   7 use work.extension_pkg.all;
   8
   9 entity core_top is
  10
  11         port(
  12                 --System input pins
  13                    sys_res : in std_logic;
  14                         sys_clk : in std_logic;
  15 --                      result : out gp_register_t;
  16 --                      reg_wr_data : out gp_register_t
  17                   -- uart
  18                         bus_tx : out std_logic;
  19                         bus_rx : in std_logic;
  20                         led2 : out std_logic;
  21
  22                         sseg0 : out std_logic_vector(0 to 6);
  23                         sseg1 : out std_logic_vector(0 to 6);
  24                         sseg2 : out std_logic_vector(0 to 6);
  25                         sseg3 : out std_logic_vector(0 to 6)
  26                 );
  27
  28 end core_top;
  29
  30 architecture behav of core_top is
  31
  32                 constant SYNC_STAGES : integer := 2;
  33                 constant RESET_VALUE : std_logic := '0';
  34
  35                 signal jump_result : instruction_addr_t;
  36                 signal jump_result_pin : instruction_addr_t;
  37                 signal prediction_result_pin : instruction_addr_t;
  38                 signal branch_prediction_bit_pin : std_logic;
  39                 signal alu_jump_bit_pin : std_logic;
  40                 signal instruction_pin : instruction_word_t;
  41                 signal prog_cnt_pin : instruction_addr_t;
  42
  43                 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
  44                 signal reg_wr_data_pin : gp_register_t;
  45                 signal reg_we_pin : std_logic;
  46                 signal to_next_stage : dec_op;
  47
  48 --              signal reg1_rd_data_pin : gp_register_t;
  49 --              signal reg2_rd_data_pin : gp_register_t;
  50
  51                  signal result_pin : gp_register_t;--reg
  52                  signal result_addr_pin : gp_addr_t;--reg
  53                  signal addr_pin : word_t; --memaddr
  54                  signal data_pin : gp_register_t; --mem data --ureg
  55                  signal alu_jump_pin : std_logic;--reg
  56                  signal brpr_pin  : std_logic;  --reg
  57                  signal wr_en_pin : std_logic;--regop --reg
  58                  signal dmem_pin  : std_logic;--memop
  59                  signal dmem_wr_en_pin : std_logic;
  60                  signal hword_pin  : std_logic;
  61                  signal byte_s_pin : std_logic;
  62
  63                  signal gpm_in_pin : extmod_rec;
  64                  signal gpm_out_pin : gp_register_t;
  65                  signal nop_pin : std_logic;
  66
  67                  signal sync : std_logic_vector(1 to SYNC_STAGES);
  68                  signal sys_res_n : std_logic;
  69
  70                  signal int_req : interrupt_t;
  71
  72                  signal new_im_data : std_logic;
  73                  signal im_addr, im_data : gp_register_t;
  74
  75                  signal vers, vers_nxt : exec2wb_rec;
  76 begin
  77
  78         fetch_st : fetch_stage
  79                 generic map (
  80
  81                         '0',
  82                         '1'
  83                 )
  84
  85                 port map (
  86                 --System inputs
  87                         clk => sys_clk, --: in std_logic;
  88                         reset => sys_res_n, --: in std_logic;
  89
  90                 --Data inputs
  91                         jump_result => jump_result_pin, --: in instruction_addr_t;
  92                         prediction_result => prediction_result_pin, --: in instruction_addr_t;
  93                         branch_prediction_bit => branch_prediction_bit_pin,  --: in std_logic;
  94                         alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
  95                         int_req => int_req,
  96                 -- instruction memory program port :D
  97                         new_im_data_in => new_im_data,
  98                         im_addr => im_addr,
  99                         im_data => im_data,
 100                 --Data outputs
 101                         instruction => instruction_pin, --: out instruction_word_t
 102                         prog_cnt => prog_cnt_pin,
 103                         led2 => led2
 104                 );
 105
 106         decode_st : decode_stage
 107                 generic map (
 108                         -- active reset value
 109                         '0',
 110                         -- active logic value
 111                         '1'
 112
 113                         )
 114                 port map (
 115                 --System inputs
 116                         clk => sys_clk, --: in std_logic;
 117                         reset => sys_res_n, -- : in std_logic;
 118
 119                 --Data inputs
 120                         instruction => instruction_pin, --: in instruction_word_t;
 121                         prog_cnt => prog_cnt_pin,
 122                         reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
 123                         reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
 124                         reg_we => reg_we_pin, --: in std_logic;
 125                         nop => nop_pin,
 126
 127                 --Data outputs
 128                         branch_prediction_res => prediction_result_pin, --: instruction_word_t;
 129                         branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
 130                         to_next_stage => to_next_stage
 131                 );
 132
 133           exec_st : execute_stage
 134                 generic map('0')
 135                 port map(sys_clk, sys_res_n,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
 136                 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
 137
 138
 139                         vers_nxt.result <= result_pin;
 140                         vers_nxt.result_addr <= result_addr_pin;
 141                         vers_nxt.address <= addr_pin;
 142                         vers_nxt.ram_data <= data_pin;
 143                         vers_nxt.alu_jmp <= alu_jump_pin;
 144                         vers_nxt.br_pred <= brpr_pin;
 145                         vers_nxt.write_en <= wr_en_pin;
 146                         vers_nxt.dmem_en <= dmem_pin;
 147                         vers_nxt.dmem_write_en <= dmem_wr_en_pin;
 148                         vers_nxt.hword <= hword_pin;
 149                         vers_nxt.byte_s <= byte_s_pin;
 150
 151 --          writeback_st : writeback_stage
 152 --                generic map('0', '1')
 153 --                port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
 154 --                wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
 155 --                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, sseg0, sseg1, sseg2, sseg3);
 156 --
 157
 158                         writeback_st : writeback_stage
 159                 generic map('0', '1', "altera")
 160                 port map(sys_clk, sys_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred,
 161                 vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
 162                 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,
 163                                 -- instruction memory program port :D
 164                                 new_im_data, im_addr, im_data,
 165                                 sseg0, sseg1, sseg2, sseg3, int_req);
 166
 167
 168 syn: process(sys_clk, sys_res)
 169
 170 begin
 171
 172         if sys_res = '1' then
 173 --                      vers.result <= (others => '0');
 174 --                      vers.result_addr <= (others => '0');
 175 --                      vers.address <= (others => '0');
 176 --                      vers.ram_data <= (others => '0');
 177 --                      vers.alu_jmp <= '0';
 178 --                      vers.br_pred <= '0';
 179 --                      vers.write_en <= '0';
 180 --                      vers.dmem_en <= '0';
 181 --                      vers.dmem_write_en <= '0';
 182 --                      vers.hword <= '0';
 183 --                      vers.byte_s <= '0';
 184
 185                 sync <= (others => '0');
 186
 187         elsif rising_edge(sys_clk) then
 188 --              vers <= vers_nxt;
 189                         sync(1) <= not sys_res;
 190                         for i in 2 to SYNC_STAGES loop
 191                                 sync(i) <= sync(i - 1);
 192                         end loop;
 193
 194         end if;
 195
 196 end process;
 197
 198 sys_res_n <= sync(SYNC_STAGES);
 199
 200 --init : process(all)
 201
 202 --begin
 203 --      jump_result_pin <= (others => '0');
 204 --      alu_jump_bit_pin <= '0';
 205 --      reg_w_addr_pin <= (others => '0');
 206 --      reg_wr_data_pin <= (others => '0');
 207 --      reg_we_pin <= '0';
 208
 209 --end process;
 210
 211 --      result <= result_pin;
 212         nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin);
 213
 214         jump_result <= prog_cnt_pin; --jump_result_pin;
 215 --      sys_res <= '1';
 216
 217 --      reg_wr_data <= reg_wr_data_pin;
 218
 219 end behav;