cpu/src/core_top_c2de1.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.common_pkg.all;
   6 use work.core_pkg.all;
   7 use work.extension_pkg.all;
   8
   9 entity core_top_c2de1 is
  10
  11         port(
  12                 --System input pins
  13                    sys_res : in std_logic;
  14                         sys_clk : in std_logic;
  15 --                      result : out gp_register_t;
  16 --                      reg_wr_data : out gp_register_t
  17                   -- uart
  18                         bus_tx : out std_logic;
  19                         bus_rx : in std_logic;
  20                         led2 : out std_logic;
  21
  22                         sseg0 : out std_logic_vector(0 to 6);
  23                         sseg1 : out std_logic_vector(0 to 6);
  24                         sseg2 : out std_logic_vector(0 to 6);
  25                         sseg3 : out std_logic_vector(0 to 6)
  26                 );
  27
  28 end core_top_c2de1;
  29
  30 architecture behav of core_top_c2de1 is
  31
  32                 constant SYNC_STAGES : integer := 2;
  33                 constant RESET_VALUE : std_logic := '0';
  34
  35                 signal jump_result : instruction_addr_t;
  36                 signal jump_result_pin : instruction_addr_t;
  37                 signal prediction_result_pin : instruction_addr_t;
  38                 signal branch_prediction_bit_pin : std_logic;
  39                 signal alu_jump_bit_pin : std_logic;
  40                 signal instruction_pin : instruction_word_t;
  41                 signal prog_cnt_pin : instruction_addr_t;
  42
  43                 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
  44                 signal reg_wr_data_pin : gp_register_t;
  45                 signal reg_we_pin : std_logic;
  46                 signal to_next_stage : dec_op;
  47
  48       signal result_pin : gp_register_t;--reg
  49       signal result_addr_pin : gp_addr_t;--reg
  50       signal addr_pin : word_t; --memaddr
  51       signal data_pin : gp_register_t; --mem data --ureg
  52       signal alu_jump_pin : std_logic;--reg
  53       signal brpr_pin  : std_logic;  --reg
  54       signal wr_en_pin : std_logic;--regop --reg
  55       signal dmem_pin  : std_logic;--memop
  56       signal dmem_wr_en_pin : std_logic;
  57       signal hword_pin  : std_logic;
  58       signal byte_s_pin : std_logic;
  59
  60                  signal gpm_in_pin : extmod_rec;
  61                  signal gpm_out_pin : gp_register_t;
  62                  signal nop_pin : std_logic;
  63
  64                  signal sync : std_logic_vector(1 to SYNC_STAGES);
  65                  signal sys_res_n : std_logic;
  66
  67                  signal int_req : interrupt_t;
  68
  69                  signal new_im_data : std_logic;
  70                  signal im_addr, im_data : gp_register_t;
  71 --               signal led2 : std_logic;
  72
  73                  signal vers, vers_nxt : exec2wb_rec;
  74 begin
  75
  76         fetch_st : fetch_stage
  77                 generic map (
  78
  79                         RESET_VALUE,
  80                         '1'
  81                 )
  82
  83                 port map (
  84                 --System inputs
  85                         clk => sys_clk, --: in std_logic;
  86                         reset => sys_res_n, --: in std_logic;
  87
  88                 --Data inputs
  89                         jump_result => jump_result_pin, --: in instruction_addr_t;
  90                         prediction_result => prediction_result_pin, --: in instruction_addr_t;
  91                         branch_prediction_bit => branch_prediction_bit_pin,  --: in std_logic;
  92                         alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
  93                         int_req => int_req,
  94                 -- instruction memory program port :D
  95                         new_im_data_in => new_im_data,
  96                         im_addr => im_addr,
  97                         im_data => im_data,
  98                 --Data outputs
  99                         instruction => instruction_pin, --: out instruction_word_t
 100                         prog_cnt => prog_cnt_pin,
 101                         led2 => led2
 102                 );
 103
 104         decode_st : decode_stage
 105                 generic map (
 106                         -- active reset value
 107                         RESET_VALUE,
 108                         -- active logic value
 109                         '1'
 110
 111                         )
 112                 port map (
 113                 --System inputs
 114                         clk => sys_clk, --: in std_logic;
 115                         reset => sys_res_n, -- : in std_logic;
 116
 117                 --Data inputs
 118                         instruction => instruction_pin, --: in instruction_word_t;
 119                         prog_cnt => prog_cnt_pin,
 120                         reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
 121                         reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
 122                         reg_we => reg_we_pin, --: in std_logic;
 123                         nop => nop_pin,
 124
 125                 --Data outputs
 126                         branch_prediction_res => prediction_result_pin, --: instruction_word_t;
 127                         branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
 128                         to_next_stage => to_next_stage
 129                 );
 130
 131           exec_st : execute_stage
 132                 generic map(RESET_VALUE)
 133                 port map(sys_clk, sys_res_n,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
 134                 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
 135
 136
 137 --                      vers_nxt.result <= result_pin;
 138 --                      vers_nxt.result_addr <= result_addr_pin;
 139 --                      vers_nxt.address <= addr_pin;
 140 --                      vers_nxt.ram_data <= data_pin;
 141 --                      vers_nxt.alu_jmp <= alu_jump_pin;
 142 --                      vers_nxt.br_pred <= brpr_pin;
 143 --                      vers_nxt.write_en <= wr_en_pin;
 144 --                      vers_nxt.dmem_en <= dmem_pin;
 145 --                      vers_nxt.dmem_write_en <= dmem_wr_en_pin;
 146 --                      vers_nxt.hword <= hword_pin;
 147 --                      vers_nxt.byte_s <= byte_s_pin;
 148
 149           writeback_st : writeback_stage
 150                 generic map(RESET_VALUE, '1', "altera")
 151                 port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
 152                 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
 153                 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,
 154                                          new_im_data, im_addr, im_data, sseg0, sseg1, sseg2, sseg3, int_req);
 155
 156
 157 --                      writeback_st : writeback_stage
 158 --                generic map(RESET_VALUE, '1', "altera")
 159 --                port map(sys_clk, sys_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred,
 160 --                vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
 161 --                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,
 162 --                              -- instruction memory program port :D
 163 --                              new_im_data, im_addr, im_data,
 164 --                              sseg0, sseg1, sseg2, sseg3, int_req);
 165 --
 166
 167 syn: process(sys_clk, sys_res)
 168
 169 begin
 170
 171         if sys_res = RESET_VALUE then
 172
 173                 sync <= (others => RESET_VALUE);
 174
 175         elsif rising_edge(sys_clk) then
 176                         sync(1) <= sys_res;
 177                         for i in 2 to SYNC_STAGES loop
 178                                 sync(i) <= sync(i - 1);
 179                         end loop;
 180
 181         end if;
 182
 183 end process;
 184
 185 sys_res_n <= sync(SYNC_STAGES);
 186 nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin);
 187 jump_result <= prog_cnt_pin; --jump_result_pin;
 188
 189 end behav;