cpu/src/fetch_stage_b.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.core_pkg.all;
   6 use work.common_pkg.all;
   7 use work.mem_pkg.all;
   8
   9 architecture behav of fetch_stage is
  10
  11 signal instr_w_addr      : instruction_addr_t;
  12 signal instr_r_addr      : instruction_addr_t;
  13 signal instr_r_addr_nxt  : instruction_addr_t;
  14 signal instr_we          : std_logic;
  15 signal instr_wr_data     : instruction_word_t;
  16 signal instr_rd_data_rom, instr_rd_data          : instruction_word_t;
  17 signal rom_ram, rom_ram_nxt : std_logic;
  18
  19 begin
  20
  21         instruction_ram : r_w_ram --rom
  22                 generic map (
  23                         PHYS_INSTR_ADDR_WIDTH,
  24                         WORD_WIDTH
  25                 )
  26
  27                 port map (
  28                         clk,
  29                         im_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
  30                         instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
  31                         new_im_data_in,
  32                         im_data,
  33                         instr_rd_data
  34                 );
  35
  36         instruction_rom : rom
  37                 generic map (
  38                         ROM_INSTR_ADDR_WIDTH,
  39                         WORD_WIDTH
  40                 )
  41
  42                 port map (
  43                         clk,
  44                         instr_r_addr_nxt(ROM_INSTR_ADDR_WIDTH-1 downto 0),
  45                         instr_rd_data_rom
  46                 );
  47
  48
  49 syn: process(clk, reset)
  50
  51 begin
  52
  53         if (reset = RESET_VALUE) then
  54                 instr_r_addr <= (others => '0');
  55                 rom_ram <= ROM_USE;
  56                 led2 <= '0';
  57         elsif rising_edge(clk) then
  58                 instr_r_addr <= instr_r_addr_nxt;
  59                 rom_ram <= rom_ram_nxt;
  60                 led2 <= rom_ram_nxt;
  61         end if;
  62
  63 end process;
  64
  65
  66 asyn: process(reset, instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data, rom_ram, instr_rd_data_rom, int_req)
  67 variable instr_pc  : instruction_addr_t;
  68 begin
  69         rom_ram_nxt <= rom_ram;
  70
  71         case rom_ram is
  72                 when ROM_USE =>
  73                         instruction <= instr_rd_data_rom;
  74                 when RAM_USE =>
  75                         instruction <= instr_rd_data;
  76                 when others =>
  77                         instruction <= x"F0000000";
  78         end case;
  79         instr_pc := std_logic_vector(unsigned(instr_r_addr) + 1);
  80         instr_r_addr_nxt <= instr_pc;
  81
  82         if (instr_pc = x"0000007f" and rom_ram = ROM_USE) then
  83                 rom_ram_nxt <= RAM_USE;
  84                 -- TODO: wenn genau auf adresse 0 im RAM ein br steht kracht es... :/
  85                 instr_r_addr_nxt <= x"00000000";
  86         end if;
  87
  88         if (reset = RESET_VALUE) then
  89                 instr_r_addr_nxt <= (others => '0');
  90         end if;
  91
  92         if (alu_jump_bit = LOGIC_ACT and int_req = IDLE) then
  93                 instr_r_addr_nxt <= jump_result;
  94                 instruction(31 downto 28) <= "1111";
  95         elsif (branch_prediction_bit = LOGIC_ACT) then
  96                 instr_r_addr_nxt <= prediction_result;
  97         end if;
  98
  99         case int_req is
 100                 when UART =>
 101                         instruction(31 downto 0) <= (others => '0');
 102                         instruction(31 downto 28) <= "1110";
 103                         instruction(27 downto 23) <= "10110";
 104                         instruction(PHYS_INSTR_ADDR_WIDTH + 7 - 1 downto 7) <= UART_INT_VECTOR;
 105                         instruction(6 downto 4) <= "001";
 106                         instruction(3 downto 2) <= "01";
 107                         instruction(1 downto 0) <= "10";
 108
 109 --                      instr_r_addr_nxt <= instr_r_addr;
 110                 when others => null;
 111         end case;
 112
 113 end process;
 114
 115 out_logic : process (instr_r_addr, alu_jump_bit, int_req, jump_result)
 116
 117 begin
 118         prog_cnt(10 downto 0) <= std_logic_vector(unsigned(instr_r_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0)));
 119         prog_cnt(31 downto 11) <= (others => '0');
 120
 121         if (int_req /= IDLE and alu_jump_bit = LOGIC_ACT ) then
 122                 prog_cnt(10 downto 0) <= jump_result(10 downto 0);
 123         end if;
 124
 125 end process;
 126
 127 end behav;
 128