--- /dev/null
+/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */\r
+/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */\r
+/* ELIGIBILITY FOR ANY PURPOSES. */\r
+/* (C) Fujitsu Microelectronics Europe GmbH */\r
+;=========================================================================================\r
+; 1 Contents\r
+;=========================================================================================\r
+; 1 Contents\r
+; 2 Disclaimer\r
+;\r
+; 3 History\r
+;\r
+; 4 Settings\r
+; 4.1 Controller device\r
+; 4.2 Boot / flash security \r
+; 4.3 Stack type and stack size\r
+; 4.4 Copy code from flash to I-RAM\r
+; 4.5 C++ start-up \r
+; 4.6 Low-level library interface\r
+; 4.7 Clock Configuration\r
+; 4.7.1 Clock selection\r
+; 4.7.2 Select Clock Modulator\r
+; 4.8 External bus interface\r
+; 4.8.1 Select chipselect \r
+; 4.8.2 Set memory addressing for chipselects\r
+; 4.8.3 Configure chipselect area\r
+; 4.8.4 Set wait cycles for chipselects\r
+; 4.8.5 Configure chipselects SDRAM memory only \r
+; 4.8.6 Referesh control register RCR \r
+; 4.8.7 Terminal and timing control register\r
+; 4.8.8 Enable / disable I-cache\r
+; 4.8.9 Enable CACHE for chipselect\r
+; 4.8.10 Select external bus mode (data lines)\r
+; 4.8.11 Select external bus mode (address lines)\r
+; 4.8.12 Select external bus mode (control signals)\r
+;\r
+; 5 Definitions of Configurations\r
+;\r
+; 6 Section and data declaration\r
+; 6.1 Define stack size\r
+; 6.2 Define sections\r
+;\r
+; 7. S T A R T \r
+; 7.1 Initialise stack pointer and table base register\r
+; 7.2 Check for CSV reset and set CSV\r
+; 7.3 Check clock condition\r
+; 7.4 Restore default settings after reset\r
+; 7.4.1 Disable clock modulator\r
+; 7.4.2 Check if running on sub clock, change to main clock\r
+; 7.4.3 Disable sub clock\r
+; 7.4.4 Check if running on PLL, gear down PLL\r
+; 7.4.5 Disable PLL\r
+; 7.4.6 Set to main clock\r
+; 7.5 Set memory controller\r
+; 7.6 Clock startup\r
+; 7.6.1 Set Voltage Regulator Settings\r
+; 7.6.2 Power on clock modulator - clock modulator part I\r
+; 7.6.3 Set CLKR register w/o clock mode\r
+; 7.6.4 Start PLLs \r
+; 7.6.5 Wait for PLL oscillation stabilisation\r
+; 7.6.6 Set clocks \r
+; 7.6.6.1 Set CPU and peripheral clock\r
+; 7.6.6.2 Set external bus interface clock\r
+; 7.6.6.3 Set CAN clock prescaler\r
+; 7.6.6.4 Switch main clock mode\r
+; 7.6.6.5 Switch sub clock mode\r
+; 7.6.6.6 Switch to PLL mode\r
+; 7.6.7 Enable frequncy modulation - clock modulator part II\r
+; 7.7 Set BusInterface\r
+; 7.7.1 Disable all CS\r
+; 7.7.2 Clear TCR register\r
+; 7.7.3 Set CS0 \r
+; 7.7.4 Set CS1 \r
+; 7.7.5 Set CS2 \r
+; 7.7.6 Set CS3\r
+; 7.7.7 Set CS4\r
+; 7.7.8 Set CS5 \r
+; 7.7.9 Set CS6\r
+; 7.7.10 Set CS7 \r
+; 7.7.11 Set special SDRAM config register \r
+; 7.7.12 set Port function register\r
+; 7.7.13 Set TCR register\r
+; 7.7.14 Enable cache for selected CS\r
+; 7.7.15 Set SDRAM referesh control register\r
+; 7.7.16 Enable used CS\r
+; 7.7.17 I-cache on/off\r
+; 7.7.18 Set port function register to general as I/O-port\r
+; 7.8 Copy code from flash to I-RAM\r
+; 7.9 Fill stacks\r
+; 7.10 Clear data \r
+; 7.11 Copy Init section from ROM to RAM\r
+; 7.12 C library initialization\r
+; 7.13 Call C++ constructors\r
+; 7.14 Call main routine\r
+; 7.15 Return from main function\r
+;\r
+;=========================================================================================\r
+; 2 Disclaimer\r
+;=========================================================================================\r
+; Fujitsu Microelectronics Europe GmbH \r
+; http://emea.fujitsu.com/microelectronics \r
+; \r
+; The following software is for demonstration purposes only. It is not fully \r
+; tested, nor validated in order to fullfill its task under all circumstances. \r
+; Therefore, this software or any part of it must only be used in an evaluation \r
+; laboratory environment. \r
+; This software is subject to the rules of our standard DISCLAIMER, that is\r
+; delivered with our SW-tools on the Fujitsu Microcontrollers CD/DVD (V3.4 or \r
+; higher "\START.HTM") or on our Internet Pages: \r
+; http://www.fme.gsdc.de/gsdc.htm\r
+; http://emea.fujitsu.com/microelectronics \r
+;\r
+;=========================================================================================\r
+; 3 History\r
+;=========================================================================================\r
+;\r
+;=========================================================================================\r
+; MB914xx (FR60 CORE ONLY) Series C Compiler's \r
+;\r
+; Startup file for memory and basic controller initialisation\r
+;=========================================================================================\r
+;History:\r
+;\r
+; 2005-04-18 V1.0 UMa Release first version\r
+; 2005-06-17 V1.1 UMa Added bus interface, modified c++ startup\r
+; 2005-06-28 V1.2 UMa minor changes\r
+; 2005-07-27 V1.3 UMa default values changed\r
+; 2005-10-04 V1.4 UMa changed code 'Call main Routine'\r
+; Added secutiy section for MB91F467D \r
+; Added Flash Access Read Timing setting section;\r
+; 2005-10-04 V1.5 UMa Added Flash Controller Section\r
+; 2005-10-28 V1.6 UMa Check for CSV reset\r
+; 2005-11.16 V1.7 UMa Monitor Debugger support added: Copy of intvect Table\r
+; Ext. Int 0 as abort function\r
+; Changed PLL-Startup, Reset HWWD added\r
+; 2005-11-16 V1.7 UMa Examples for MUL_G changed\r
+; 2006-02-14 V1.8 UMa mb91464a added\r
+; Settings for Clock Spervisor added\r
+; Name of Section SECURITY changed to SECURITY_VECTORS\r
+; Example values for gear-up changed\r
+; 2006-03-17 V1.9 UMa Changed Startup for Monitor Debugger\r
+; 2006-04-24 v2.0 UMa Added MB91465K and MB91469G\r
+; 2006-05-03 v2.1 UMa Added MB91461R; removed MB91V460A\r
+; Added settings for the external bus-interface\r
+; 2006-07-28 v2.2 UMa Added I-RAM copy function (ROM -> IRAM)\r
+; Added default settings for FLASH Access Read Timing \r
+; Settings \r
+; Changed default settings for FLASH cache configuration \r
+; Register\r
+; Changed check for clock startup\r
+; 2006-08-16 v2.3 MVo Corrected Boot Security Sector Addresses for MB91469G\r
+; 2006-10-06 v2.4 UMa Added new devices\r
+; Corrected typo in I_RAM to flash copy function\r
+; Changed default settings for flash cache configuration\r
+; Changed comments for SDRAM bus interface configuration\r
+; Changed comments and default setting of CAN Prescaler\r
+; Added Stack filler\r
+; Added Settings for REGSEL Register\r
+; 2007-02-13 v2.5 UMa Introduction of default configurations\r
+; Changed I_RAM to flash copy function \r
+;\r
+;\r
+;=========================================================================================\r
+; 4 Settings\r
+;=========================================================================================\r
+;\r
+; CHECK ALL OPTIONS WHETHER THEY FIT TO THE APPLICATION;\r
+;\r
+; Configure this startup file in the "Settings" section. Search for\r
+; comments with leading "; <<<". This points to the items to be set.\r
+;=========================================================================================\r
+;\r
+#set OFF 0\r
+#set ON 1\r
+#set DEFAULT 2\r
+#set LOW_PRIOR 31\r
+;\r
+;=========================================================================================\r
+; 4.1 Controller Device\r
+;=========================================================================================\r
+#set MB91464A 2 ; MB91460 series\r
+;\r
+#set MB91467B 10 ; MB91460 series\r
+;\r
+#set MB91467C 11 ; MB91460 series\r
+;\r
+#set MB91467D 4 ; MB91460 series\r
+;\r
+#set MB91469G 6 ; MB91460 series\r
+;\r
+#set MB91465K 3 ; MB91460 series\r
+;\r
+#set MB91463N 8 ; MB91460 series\r
+;\r
+#set MB91461R 1 ; MB91460 series\r
+#set MB91467R 5 ; MB91460 series\r
+;\r
+#set MB91465X 9 ; MB91460 series\r
+;\r
+#set others 7 ; MB91460 series\r
+;\r
+;\r
+;\r
+#set DEVICE MB91465K ; <<< select device\r
+;\r
+;=========================================================================================\r
+; 4.2 Boot / Flash Security \r
+;=========================================================================================\r
+;\r
+#set BOOT_FLASH_SEC OFF ; <<< BOOT and Flash Security Vector \r
+;\r
+; The flash devices have two flash and two boot security vectors. It is important to set\r
+; the four vectors correctly. Otherwise it might be possible, that the flash device is \r
+; not accessible any more via the bootrom. Please read carefully the hardware manual.\r
+; \r
+; OFF: The security feature is switch off. The section SECURITY_VECTORS is reserved and\r
+; the vectors are set.\r
+; ON: IMPORTANT! The security vectors are not set. But the section SECURITY_VECTORS \r
+; is reserved. \r
+;\r
+; Note: This feature is not supported by every device. Please check the data sheet. This \r
+; feature is not available on MB91461R.\r
+;\r
+;=========================================================================================\r
+; 4.3 Stack Type and Stack Size\r
+;=========================================================================================\r
+;\r
+#set USRSTACK 0 ; user stack: for main program\r
+#set SYSSTACK 1 ; system stack: for main program and \r
+; ; interrupts\r
+;\r
+;\r
+#set STACKUSE SYSSTACK ; <<< set active stack\r
+;\r
+#set STACK_RESERVE ON ; <<< reserve stack area in \r
+; ; this module\r
+#set STACK_SYS_SIZE 0x400-4 ; <<< byte size of System stack\r
+#set STACK_USR_SIZE 0x2 ; <<< byte size of User stack \r
+;\r
+#set STACK_FILL OFF ; <<< fills the stack area with pattern\r
+#set STACK_PATTERN 0x55AA6699 ; <<< the pattern to write to stack\r
+;\r
+; - If the active stack is set to SYSSTACK, it is used for main program and interrupts. \r
+; In this case, the user stack could be set to a dummy size. If the active stack is \r
+; set to user stack, it is used for the main program but the system stack is \r
+; automatically activated, if an interrupt is serviced. Both stack areas must have a \r
+; reasonable size.\r
+; - If STACK_RESERVE is ON, the sections USTACK and SSTACK are reserved in this module. \r
+; Otherwise, they have to be reserved in other modules. If STACK_RESERVE is OFF, the \r
+; size definitions STACK_SYS_SIZE and STACK_USR_SIZE have no meaning.\r
+; - Even if they are reverved in other modules, they are still initialised in this \r
+; start-up file.\r
+;\r
+; Note: Several library functions require quite a big stack (due to ANSI). \r
+; Check the stack information files (*.stk) in the LIB\911 directory.\r
+;\r
+;=========================================================================================\r
+; 4.4 Copy code from Flash to I-RAM\r
+;=========================================================================================\r
+;\r
+#set I_RAM ON ; <<< select if code in section IRAM\r
+; should be copied\r
+;\r
+; If this option is activated code located in the section IRAM is copied during startup \r
+; from ROM to the instruction-RAM. The code is linked for the instruction-RAM.\r
+;\r
+;=========================================================================================\r
+; 4.5 Low-Level Library Interface\r
+;=========================================================================================\r
+;\r
+#set CLIBINIT OFF ; <<< select ext. libray usage\r
+;\r
+; This option has only to be set, if stream-IO/standard-IO function of the C-libraray \r
+; have to be used (printf(), fopen()...). This also requires low-level functions to be \r
+; defined by the application software.\r
+; For other library functions like (e.g. sprintf()) all this is not necessary. However, \r
+; several functions consume a large amount of stack.\r
+;\r
+;=========================================================================================\r
+; 4.6 C++ start-up \r
+;=========================================================================================\r
+;\r
+#set CPLUSPLUS OFF ; <<< activate if c++ files are used\r
+;\r
+; In the C++ specifications, when external or static objects are used, a constructor \r
+; must be called followed by the main function. Because four-byte pointers to the main \r
+; function are stored in the EXT_CTOR_DTOR section, call a constructor sequentially from\r
+; the lower address of the four addresses in that section. If using C++ sources, \r
+; activate this function to create the section EXT_CTOR_DTOR. \r
+;\r
+;=========================================================================================\r
+; 4.7 Clock Configuration\r
+;=========================================================================================\r
+;=========================================================================================\r
+; 4.7.1 Clock Selection\r
+;=========================================================================================\r
+;\r
+; No clock settings\r
+#set NO_CLOCK 0x01\r
+;\r
+; Sub-oscillation input: 32 kHz \r
+#set SUB_32KHZ_CPU__32KHZ_PER_32KHZ_EXT_32KHZ_CAN__2MHZ 0x11\r
+;\r
+; Oscillation input: 4 MHz \r
+#set MAIN_4MHZ_CPU___2MHZ_PER__1MHZ_EXT__1MHZ_CAN__2MHZ 0x21\r
+#set PLL_4MHZ__CPU__48MHZ_PER_16MHZ_EXT_24MHZ_CAN_16MHZ 0x22\r
+#set PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ 0x23\r
+#set PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_27MHZ_CAN_20MHZ 0x24\r
+#set PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_40MHZ_CAN_20MHZ 0x25\r
+#set PLL_4MHZ__CPU__96MHZ_PER_16MHZ_EXT_48MHZ_CAN_16MHZ 0x26 ;not MB91V460, ...\r
+#set PLL_4MHZ__CPU_100MHZ_PER_20MHZ_EXT_50MHZ_CAN_20MHZ 0x27 ;not MB91V460, ...\r
+;\r
+; MB91461R only: Oscillation input: 10 MHz\r
+#set PLL_10MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ 0x41\r
+;\r
+; MB91461R only: Oscillation input: 20 MHz\r
+#set PLL_20MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ 0x51\r
+;\r
+; User settings\r
+#set CLOCK_USER 0x61\r
+;\r
+;\r
+;\r
+#set CLOCKSPEED PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ\r
+; ; <<< Select clock configuration \r
+;\r
+; There are different default configurations available, where all necessary settings for \r
+; clocks and the related registers are made. Beside this configurations, there is the\r
+; possibility to define a user configuration in the chapter "Definition of \r
+; Configurations"\r
+; \r
+; - NO_CLOCK means: \r
+; The clock registers are not set by the start-up file.\r
+;\r
+; - PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ means:\r
+; Main oszillation = 4 MHz, PLL is activated\r
+; CPU clock (CLKB) = 64 MHZ\r
+; Peripheral clock (CLKP) = 16 MHZ\r
+; Ext. bus clock (CLKT) = 32 MHZ\r
+; CAN clock (CLKCAN) = 16 MHz, using PLLx \r
+;\r
+; - CLOCK_USER: \r
+; The user configuration definded in the chapter "Definition of Configurations" is set.\r
+;\r
+; Note: Not all frequencies are supported by every device. Please see the hardware \r
+; manual.\r
+;\r
+;=========================================================================================\r
+; 4.7.2 Select Clock Modulator \r
+;=========================================================================================\r
+;\r
+#set CLOMO OFF ; <<< Enable /disable clock modulator \r
+;\r
+#set CMPR 0x026F ; <<< Ref. to the data sheet, CMPR\r
+; \r
+; Please refer to the data sheet of the device if you enable clock modulation. The \r
+; register CMPR dependant on the PLL-Clock.\r
+;\r
+; Note: If the CLKCAN source is set either to main oscillator or to PLL output then the\r
+; clock for the CAN is not influenced by the clock modulation. If the CLKCAN \r
+; source is set CPU clock (CLKB) then the clock for the CAN is also modulated (if \r
+; the clock modulator is enabled).\r
+;\r
+; Note: If the clock modulator is enabled, the wait states of the internal flash wait \r
+; states must be adapted to maximum frequency. Please check the wait states \r
+; settings.\r
+;\r
+; Note: This feature is not supported by every device, e.g. MB91461. Please check the \r
+; data sheet.\r
+;\r
+;=========================================================================================\r
+; 4.8 External Bus Interface\r
+;\r
+; The rest of the configuration is only applicable for devices with an external bus \r
+; interface.\r
+;\r
+; If the device does not offer an external bus interface, the configuration can be \r
+; stoped at this point.\r
+;\r
+;=========================================================================================\r
+;\r
+#set EXTBUS DEFAULT ; <<< Ext. Bus on/off\r
+;\r
+; ON - The ext. bus interface is enabled and is configured as\r
+; set below. \r
+; \r
+; OFF - The ext. bus interface is diabled. The port function \r
+; registers are set to general I/O. The registers of \r
+; ext. bus interface will not be touched by the start-up \r
+; file. \r
+; Be aware, that the device might be conifgured in ext.\r
+; bus mode by default after reset.\r
+;\r
+; DEFAULT - Neither the register nor the respective port function\r
+; registers are touched by the start-up file.\r
+; Be aware, that the device might be conifgured in ext. \r
+; bus mode by default after reset.\r
+;\r
+;\r
+; Note: This feature is not supported by every device. Please check the data sheet. The \r
+; following devices for example do not offer an external bus interface: MB91464A, \r
+; MB91467C, MB91465K, MB91463N, MB91465X.\r
+;\r
+;=========================================================================================\r
+; 4.8.1 Select Chipselect (Only EXTBUS == ON)\r
+;=========================================================================================\r
+;\r
+#set CS0 OFF ; <<< select CS (ON/OFF)\r
+#set CS1 OFF ; <<< select CS (ON/OFF)\r
+#set CS2 OFF ; <<< select CS (ON/OFF)\r
+#set CS3 OFF ; <<< select CS (ON/OFF)\r
+#set CS4 OFF ; <<< select CS (ON/OFF)\r
+#set CS5 OFF ; <<< select CS (ON/OFF)\r
+#set CS6 OFF ; <<< select CS (ON/OFF)\r
+#set CS7 OFF ; <<< select CS (ON/OFF)\r
+#set SDRAM OFF ; <<< select if a SDRAM is connected \r
+;\r
+;\r
+#set ENACSX B'00000000 ; <<< set CS, ENACSX\r
+; ||||||||\r
+; ||||||||__ CS0 bit, enable/disable CS0 (1/0)\r
+; |||||||___ CS1 bit, enable/disable CS1 (1/0)\r
+; ||||||____ CS2 bit, enable/disable CS2 (1/0)\r
+; |||||_____ CS3 bit, enable/disable CS3 (1/0)\r
+; ||||______ CS4 bit, enable/disable CS4 (1/0)\r
+; |||_______ CS5 bit, enable/disable CS5 (1/0) \r
+; ||________ CS6 bit, enable/disable CS6 (1/0)\r
+; |_________ CS7 bit, enable/disable CS7 (1/0)\r
+;\r
+; Note: If the SWB Monitor Debugger is used, set the CS1 (external RAM only) or CS0 and \r
+; CS 1 (external RAM and flash) to off.\r
+;\r
+; Note: Not all Chipselects are supported by the different devices. Please check the \r
+; data sheet.\r
+;\r
+;=========================================================================================\r
+; 4.8.2 Set memory addressing for Chipselects (only EXTBUS == ON)\r
+;=========================================================================================\r
+;\r
+#set AREASEL0 0x0000 ; <<< set start add. for CS0, ASR0 \r
+#set AREASEL1 0x0000 ; <<< set start add. for CS1, ASR1 \r
+#set AREASEL2 0x0000 ; <<< set start add. for CS2, ASR2 \r
+#set AREASEL3 0x0000 ; <<< set start add. for CS3, ASR3 \r
+#set AREASEL4 0x0000 ; <<< set start add. for CS4, ASR4 \r
+#set AREASEL5 0x0000 ; <<< set start add. for CS5, ASR5 \r
+#set AREASEL6 0x0000 ; <<< set start add. for CS6, ASR6 \r
+#set AREASEL7 0x0000 ; <<< set start add. for CS7, ASR7 \r
+;\r
+; Configure the starting address of each used Chipselect. Chipselects which are not used\r
+; (not set to ON in "Select Chipselect") need not be set (setting ignored).\r
+;\r
+; NOTE: Just the upper 16-bit of the start address must be set, e.g. when using start \r
+; address 0x00080000 set 0x0008.\r
+;\r
+;=========================================================================================\r
+; 4.8.3 Configure Chipselect Area (only EXTBUS == ON)\r
+;=========================================================================================\r
+;\r
+#set CONFIGCS0 B'0000000000000000 ; <<< Config. CS0, ACR0\r
+#set CONFIGCS1 B'0000000000000000 ; <<< Config. CS1, ACR1 \r
+#set CONFIGCS2 B'0000000000000000 ; <<< Config. CS2, ACR2 \r
+#set CONFIGCS3 B'0000000000000000 ; <<< Config. CS3, ACR3 \r
+#set CONFIGCS4 B'0000000000000000 ; <<< Config. CS4, ACR4 \r
+#set CONFIGCS5 B'0000000000000000 ; <<< Config. CS5, ACR5 \r
+#set CONFIGCS6 B'0000000000000000 ; <<< Config. CS6, ACR6 \r
+#set CONFIGCS7 B'0000000000000000 ; <<< Config. CS7, ACR7 \r
+; ||||||||||||||||\r
+; ||||||||||||||||__ TYP0 bit, TYP0-4 bits select access type\r
+; |||||||||||||||___ TYP1 bit\r
+; ||||||||||||||____ TYP2 bit\r
+; |||||||||||||_____ TYP3 bit\r
+; ||||||||||||______ LEND bit, select little '1' or big endian '0'\r
+; |||||||||||_______ WREN bit, en-/disable (1/0) Write access\r
+; ||||||||||________ PFEN bit, en-/disable (1/0) pre-fetch\r
+; |||||||||_________ SREN bit, en-/disable (1/0) share of BRQ & BGRNTX\r
+; ||||||||__________ BST0 bit, BSTx bits select burst size\r
+; |||||||___________ BST1 bit\r
+; ||||||____________ DBW0 bit, DBWx select data bus width\r
+; |||||_____________ DBW1 bit\r
+; ||||______________ ASZ0 bit, ASZx bits select address size of CS\r
+; |||_______________ ASZ1 bit\r
+; ||________________ ASZ2 bit\r
+; |_________________ ASZ3 bit\r
+;\r
+; Bit description:\r
+;\r
+; TYP3 TYP2 TYP1 TYP0 : Select access type of each CS\r
+; 0 0 X X : Normal access (asynchronous SRAM, I/O, \r
+; single/page/busrt-ROM/FLASH) \r
+; 0 1 X X : Address/data multiplexed (8bit / 16bit bus width only)\r
+; 0 X X 0 : WAIT insertion by RDY disabled\r
+; 0 X X 1 : WAIT insertion by RDY enabled\r
+; 0 X 0 X : The WR0X pin to the WR3X pin are used as write strobes \r
+; (WRX is fixed at H-Level)\r
+; 0 X 1 X : The WRX pin is used as write strobe \r
+; 1 0 0 0 : Memory type A: SDRAM/FCRAM (Auto pre-charge used) \r
+; 1 0 0 1 : Memory type B: FCRAM (Auto pre-charge used) \r
+; 1 0 1 0 : setting not allowed\r
+; 1 0 1 1 : setting not allowed\r
+; 1 1 0 0 : setting not allowed\r
+; 1 1 0 1 : setting not allowed\r
+; 1 1 1 0 : setting not allowed\r
+; 1 1 1 1 : mask area setting\r
+;\r
+; LEND : select BYTE ordering \r
+; 0 : Big endian\r
+; 1 : Little endian\r
+;\r
+; WREN : enable or disable write access \r
+; 0 : disabled \r
+; 1 : enabled, \r
+;\r
+; PFEN : Enable or disable the pre-fetch\r
+; 0 : disabled \r
+; 1 : enabled, \r
+;\r
+; SREN : Enable or disable the sharing of BRQ and BGRNTX \r
+; 0 : disabled \r
+; 1 : enabled (CSx pin High-Z)\r
+;\r
+; BST1 BST0 : set burst size of chip select area\r
+; 0 0 : 1 burst (single access)\r
+; 0 1 : 2 bursts (Address boundary 1 bit) \r
+; 1 0 : 4 bursts (Address boundary 2 bit)\r
+; 1 1 : 8 bursts (Address boundary 3 bit)\r
+;\r
+; DBW1 DBW0 : Set data bus width\r
+; 0 0 : 8-bit (BYTE access) \r
+; 0 1 : 16-bit (HALF-WORD access) \r
+; 1 0 : 32-bit (WORD access) \r
+; 1 1 : Reserved \r
+;\r
+; ASZ3 ASZ2 ASZ1 ASZ0 : Select memory size of each chipselect \r
+; 0 0 0 0 : 64 Kbyte (0x01.0000 bytes; use ASR A[31:16] bits) \r
+; 0 0 0 1 : 128 Kbyte (0x02.0000 bytes; use ASR A[31:17] bits)\r
+; 0 0 1 0 : 256 Kbyte (0x04.0000 bytes; use ASR A[31:18] bits)\r
+; 0 0 1 1 : 512 Kbyte (0x08.0000 bytes; use ASR A[31:19] bits)\r
+; 0 1 0 0 : 1 Mbyte (0x10.0000 bytes; use ASR A[31:20] bits)\r
+; 0 1 0 1 : 2 Mbyte (0x20.0000 bytes; use ASR A[31:21] bits)\r
+; 0 1 1 0 : 4 Mbyte (0x40.0000 bytes; use ASR A[31:22] bits)\r
+; 0 1 1 1 : 8 Mbyte (0x80.0000 bytes; use ASR A[31:23] bits)\r
+; 1 0 0 0 : 16 Mbyte (0x100.0000 bytes; use ASR A[31:24] bits)\r
+; 1 0 0 1 : 32 Mbyte (0x200.0000 bytes; use ASR A[31:25] bits)\r
+; 1 0 1 0 : 64 Mbyte (0x400.0000 bytes; use ASR A[31:26] bits)\r
+; 1 0 1 1 : 128 Mbyte (0x800.0000 bytes; use ASR A[31:27] bits)\r
+; 1 1 0 0 : 256 Mbyte (0x1000.0000 bytes; use ASR A[31:28] bits)\r
+; 1 1 0 1 : 512 Mbyte (0x2000.0000 bytes; use ASR A[31:29] bits)\r
+; 1 1 1 0 : 1024 Mbyte(0x4000.0000 bytes; use ASR A[31:30] bits)\r
+; 1 1 1 1 : 2048 Mbyte(0x8000.0000 bytes; use ASR A[31] bit)\r
+;\r
+;=========================================================================================\r
+; 4.8.4 Set Wait cycles for Chipselects for ordinary businterface (only EXTBUS == ON)\r
+;=========================================================================================\r
+;\r
+; Ordinary bus interface (w/o SDRAM and FRAM) (ACRx_Type = 0xxx)\r
+;\r
+#set WAITREG0 B'0000000000000000 ; <<< CS0 Waitstates, AWR0 \r
+#set WAITREG1 B'0000000000000000 ; <<< CS1 Waitstates, AWR1 \r
+#set WAITREG2 B'0000000000000000 ; <<< CS2 Waitstates, AWR2 \r
+#set WAITREG3 B'0000000000000000 ; <<< CS3 Waitstates, AWR3 \r
+#set WAITREG4 B'0000000000000000 ; <<< CS4 Waitstates, AWR4 \r
+#set WAITREG5 B'0000000000000000 ; <<< CS5 Waitstates, AWR5 \r
+; ||||||||||||||||\r
+; ||||||||||||||||__ W00 bit, RDY/WRY-> CSX hold cycle\r
+; |||||||||||||||___ W01 bit, CSX->RDX/WRX setup extension cycle\r
+; ||||||||||||||____ W02 bit, Address -> CSX Delay selection\r
+; |||||||||||||_____ W03 bit, WR0X to WR3X/WRX outout timing \r
+; ||||||||||||______ W04 bit, W04/W05 Write recovery cycle\r
+; |||||||||||_______ W05 bit \r
+; ||||||||||________ W06 bit, W06/07 Read -> Write idle cycle \r
+; |||||||||_________ W07 bit selection\r
+; ||||||||__________ W08 bit, W08-W11 Intra-page access cycle \r
+; |||||||___________ W09 bit select (0-15 cycles)\r
+; ||||||____________ W10 bit \r
+; |||||_____________ W11 bit\r
+; ||||______________ W12 bit, W12-W15 First access wait cycle \r
+; |||_______________ W13 bit select (0-15 cycles)\r
+; ||________________ W14 bit\r
+; |_________________ W15 bit\r
+;\r
+;\r
+; SDRAM and FRAM bus interface (ACRx_Type = 100x) \r
+;\r
+#set WAITREG6 B'0000000000000000 ; <<< CS6 Waitstates, AWR6 \r
+#set WAITREG7 B'0000000000000000 ; <<< CS7 Waitstates, AWR7\r
+; ||||||||||||||||\r
+; ||||||||||||||||__ W00 bit, W0-W1 RAS precharge cycles\r
+; |||||||||||||||___ W01 bit\r
+; ||||||||||||||____ W02 bit, W2-W3 RAS active Time\r
+; |||||||||||||_____ W03 bit\r
+; ||||||||||||______ W04 bit, W4-W5 Write recovery cycle\r
+; |||||||||||_______ W05 bit \r
+; ||||||||||________ W06 bit, W6-W7 Read->Write idle cycle\r
+; |||||||||_________ W07 bit\r
+; ||||||||__________ W08 bit, W8-W10 CAS latency \r
+; |||||||___________ W09 bit\r
+; ||||||____________ W10 bit \r
+; |||||_____________ W11 bit, reserved\r
+; ||||______________ W12 bit, W12-W16 RAS-CAS delay \r
+; |||_______________ W13 bit\r
+; ||________________ W14 bit \r
+; |_________________ W15 bit, reserved\r
+;\r
+;\r
+; The bit meaning depends on the configured bus interface type. The bus interface can be \r
+; configured for different memory types. Depending on the memory type, the wait register \r
+; bits have a differnt meaning. CS0-5 should be configurable as ordinary bus interface \r
+; (w/o SDRAM and FRAM) and CS6-7 should be configurable as SDRAM and FRAM. It is also \r
+; possible and for some devices neccessary to configure other two chip selects as SDRAM \r
+; or FRAM interface. In such a case be aware of the bit meanings.\r
+;\r
+;\r
+; Ordinary bus interface (w/o SDRAM and FRAM) (ACRx_Type = 0xxx)\r
+; --------------------------------------------------------------\r
+;\r
+; Bit description:\r
+;\r
+; W00 : RDY/WRX -> CSX hold extension cycle\r
+; 0 : 0 cycle\r
+; 1 : 1 cycle\r
+;\r
+; W01 : CSX -> RDX/WRX setup extention cycle\r
+; 0 : 0 cycle\r
+; 1 : 1 cycle\r
+;\r
+; W02 : Address -> CSX Delay selection\r
+; 0 : no delay selected\r
+; 1 : delay selected\r
+;\r
+; W03 : WR0X to WR3X/WRX outout timing selection\r
+; 0 : MCLK synchronous write output enable (ASX=L)\r
+; 1 : Asynchronous write strobe output (norma operation)\r
+;\r
+; W05 W04 : select Write recovery cycle\r
+; 0 0 : 0 cycle\r
+; 0 1 : 1 cycle\r
+; 1 0 : 2 cycles\r
+; 1 1 : 3 cycles\r
+;\r
+; W07 W06 : Read -> Write idle cycle selection\r
+; 0 0 : 0 cycle\r
+; 0 1 : 1 cycle\r
+; 1 0 : 2 cycles\r
+; 1 1 : 3 cycles\r
+; \r
+; W11 W10 W09 W08 : Intra-page access cycle select (0-15 cycles)\r
+; 0 0 0 0 : 0 Wait state\r
+; 0 0 0 1 : 1 Auto-wait cycle\r
+; 0 0 1 0 : 2 Auto-wait cycle\r
+; ....\r
+; 1 1 1 1 : 15 Auto wait cycles\r
+;\r
+; W15 W14 W13 W12 : First access wait cycle can be set (0-15 cycles)\r
+; 0 0 0 0 : 0 Wait state\r
+; 0 0 0 1 : 1 Auto-wait cycle\r
+; 0 0 1 0 : 2 Auto-wait cycle\r
+; ....\r
+; 1 1 1 1 : 15 Auto wait cycles\r
+; \r
+;\r
+;\r
+; SDRAM and FRAM bus interface (ACRx_Type = 100x)\r
+; -----------------------------------------------\r
+;\r
+; Bit description:\r
+;\r
+; W01 W00 : RAS precharge cycles.\r
+; 0 0 : 1 cycle\r
+; 0 1 : 2 cycles\r
+; 1 0 : 5 cycles\r
+; 1 1 : 6 cycles\r
+;\r
+; W03 W02 : RAS active Time\r
+; 0 0 : 1 cycle\r
+; 0 1 : 2 cycles\r
+; 1 0 : 5 cycles\r
+; 1 1 : 6 cycles\r
+;\r
+; W05 W04 : set Write recovery cycle (1 - 4 cycles)\r
+; 0 0 : Prohibited\r
+; 0 1 : 2 cycles\r
+; 1 0 : 3 cycles\r
+; 1 1 : 4 cycles\r
+;\r
+; W07 W06 : set Read -> Write idle Cycle (1 - 4 cycles)\r
+; 0 0 : 1 cycle\r
+; 0 1 : 2 cycles\r
+; 1 0 : 3 cycles\r
+; 1 1 : 4 cycles\r
+;\r
+; W10 W09 W08 : set CAS latency (1 - 8 cycles)\r
+; 0 0 0 : 1 cycle\r
+; 0 0 1 : 2 cycle\r
+; ...\r
+; 1 1 1 : 8 cycle\r
+;\r
+; W11 : RESERVED, ALWAYS WRITE 0 !\r
+;\r
+; W14 W13 W12 : set RAS-CAS delay (1 - 8 cycles)\r
+; 0 0 0 : 1 cycle\r
+; 0 0 1 : 2 cycle\r
+; ...\r
+; 1 1 1 : 8 cycle\r
+;\r
+; W15 : RESERVED, ALWAYS WRITE 0 !\r
+;\r
+\r
+; The bit meaning depends on the configured bus interface type\r
+;\r
+;=========================================================================================\r
+; 4.8.5 Configure Chipselects for SDRAM memory only (only EXTBUS == ON and SDRAM)\r
+;=========================================================================================\r
+;\r
+#set MEMCON B'00000111 ; <<< set special SDRAM register, MCRA\r
+; ||||||||\r
+; ||||||||__ ABS0 bit, set max. active banks (ABS1,0)\r
+; |||||||___ ABS1 bit\r
+; ||||||____ BANK bit, set number of banks connected to CS\r
+; |||||_____ WBST bit, Write burst enable/disable\r
+; ||||______ PSZ0 bit, Set page size (PSZ2-0)\r
+; |||_______ PSZ1 bit \r
+; ||________ PSZ2 bit\r
+; |_________ reserved, always write 0 \r
+;\r
+; When connecting SDRAM/FCRAM TYP3-0=1000 in ACRx register the following register must \r
+; be setup.\r
+;\r
+; Bit description:\r
+;\r
+; ABS1 ABS0 : Set maximum number of bank, active at same time\r
+; 0 0 : 1 bank\r
+; 0 1 : 2 banks\r
+; 1 0 : 3 banks\r
+; 1 1 : 4 banks\r
+;\r
+; BANK : Set number of connected SDRAM banks\r
+; 0 : 2 banks\r
+; 1 : 4 banks\r
+;\r
+; WBST : Write burst enable\r
+; 0 : Single Write\r
+; 1 : Busrt Write\r
+;\r
+; PSZ2 PSZ1 PS0 : Select page size of connected memory\r
+; 0 0 0 : 8-bit column address = A0 to A7 \r
+; 0 0 1 : 9-bit column address = A0 to A8 \r
+; 0 1 0 : 10-bit column address = A0 to A9 \r
+; 0 1 1 : 11-bit column address = A0 to A9, A11 \r
+; 1 X X : setting disabled\r
+;\r
+;\r
+;=========================================================================================\r
+; 4.8.6 Referesh Control Register RCR (only EXTBUS == ON and SDRAM)\r
+;=========================================================================================\r
+;\r
+#set REFRESH B'1110001001000111 ; <<< set Refresh Control Register, RCR\r
+; ||||||||||||||||\r
+; ||||||||||||||||__ TRC0 bit, set refresh cycle (TRC2-0)\r
+; |||||||||||||||___ TRC1 bit\r
+; ||||||||||||||____ TRC2 bit\r
+; |||||||||||||_____ PON bit, set power-on control\r
+; ||||||||||||______ RFC0 bit, set refresh count (RFC2-0)\r
+; |||||||||||_______ RFC1 bit \r
+; ||||||||||________ RFC2 bit \r
+; |||||||||_________ BRST bit, set burst refresh control \r
+; ||||||||__________ RFINT0 bit, set auto refresh interval\r
+; |||||||___________ RFINT1 bit, (RFINT5-0)\r
+; ||||||____________ RFINT2 bit\r
+; |||||_____________ RFINT3 bit\r
+; ||||______________ RFINT4 bit\r
+; |||_______________ RFINT5 bit\r
+; ||________________ RRLD bit, counter refresh strat control\r
+; |_________________ SELF bit, self refresh control\r
+;\r
+;\r
+; This register sets various SDRAM refresh controls. When SDRAM control is not set for \r
+; any area, the setting of this register is meaningless, but do not change the register \r
+; value at initial state. When a read is performed using a read-modify-write \r
+; instruction, 0 always returns from the SELF, RRLD, and PON bits.\r
+;\r
+; Bit description:\r
+;\r
+;\r
+; TRC2 TRC1 TRC0 : Refresh Cycle \r
+; 0 0 0 : 4\r
+; 0 0 1 : 5\r
+; 0 1 0 : 6\r
+; 0 1 1 : 7\r
+; 1 0 0 : 8\r
+; 1 0 1 : 9\r
+; 1 1 0 : 10\r
+; 1 1 1 : 11\r
+;\r
+; PON : Power-on control\r
+; 0 : disabled\r
+; 1 : power-on sequence started\r
+;\r
+; RFC2 RFC1 RFC0 : Refresh Count\r
+; 0 0 0 : 256\r
+; 0 0 1 : 512\r
+; 0 1 0 : 1024\r
+; 0 1 1 : 2048\r
+; 1 0 0 : 4096\r
+; 1 0 1 : 8192\r
+; 1 1 0 : Setting disabled\r
+; 1 1 1 : Refresh disabled\r
+;\r
+; BRST : Burst refresh control\r
+; 0 : Decentralised refresh \r
+; 1 : burst refresh\r
+; \r
+; RFINT[5-0] : auto refresh interval\r
+;\r
+; RRLD : Refresh counter Activation Control\r
+; 0 : Disabled, \r
+; 1 : Autorefresh performed once, then value of RFINT reloaded\r
+;\r
+; SELF : Self refresh control\r
+; 0 : auto refresh or power down\r
+; 1 : Transitions to self-refresch mode\r
+;\r
+; NOTE: PON bit is set after the above setting. Do not set PON bit to 1 in the \r
+; above setting. Otherwise the settings are not correct set.\r
+;\r
+;=========================================================================================\r
+; 4.8.7 Terminal and Timing Control Register (only EXTBUS == ON)\r
+;=========================================================================================\r
+;\r
+#set TIMECONTR B'00000000 ; <<< set TCR register, TCR\r
+; ||||||||\r
+; ||||||||__ RDW0 bit, set wait cycle reduction (RDW0,1)\r
+; |||||||___ RDW1 bit\r
+; ||||||____ OHT0 bit, set output hold delay (OHT1,0)\r
+; |||||_____ OHT1 bit\r
+; ||||______ reserved, always write 0 \r
+; |||_______ PCLR bit, prefetch buffer clear \r
+; ||________ PSUS bit, prefetch suspend\r
+; |_________ BREN bit, BRQ input enable \r
+;\r
+; This register controls the general functions of the external bus interface controller \r
+; such as the common-pin function setting and timing control.\r
+;\r
+; Bit description:\r
+;\r
+; RDW1 RDW0 : Wait cycle reduction \r
+; 0 0 : Normal Wait (AWR0 - 7 setting)\r
+; 0 1 : 1/2 of AWR0 - 7 setting value\r
+; 1 0 : 1/4 of AWR0 - 7 setting value\r
+; 1 1 : 1/8 of AWR0 - 7 setting value\r
+;\r
+; OHT1 OHT0 : Output hold selection bit\r
+; 0 0 : Output performed at falling edge of SYSCLK/MCLK\r
+; 0 1 : Output performed about 3ns after falling edge of SYSCLK/MCLK\r
+; 1 0 : Output performed about 4ns after falling edge of SYSCLK/MCLK\r
+; 1 1 : Output performed about 5ns after falling edge of SYSCLK/MCLK\r
+;\r
+; PCLR : Prefetch buffer all clear\r
+; 0 : normal state\r
+; 1 : Prefetch buffer cleared\r
+;\r
+; PSUS : prefetch suspension bit \r
+; 0 : Prefetch enabled\r
+; 1 : Prefetch disabled\r
+;\r
+; BREN : BRQ input enable\r
+; 0 : disabled, \r
+; 1 : enabled, Bus sharing of BRQ/BGRNTX performed\r
+;\r
+; Note: This function is used to prevent an excessive access cycle wait while operating \r
+; at a low-speed clock (such as while base clock operating at low speed or \r
+; high frequency division rate for external bus clock).\r
+;\r
+;=========================================================================================\r
+; 4.8.8 Enable/Disable I-CACHE (only EXTBUS == ON)\r
+;=========================================================================================\r
+;\r
+#set C1024 1 ; CACHE Size: 1024 BYTE\r
+#set C2048 2 ; CACHE Size: 2048 BYTE\r
+#set C4096 3 ; CACHE Size: 4096 BYTE\r
+;\r
+;\r
+#set CACHE OFF ; <<< Select use of cache \r
+#set CACHE_SIZE C4096 ; <<< Select size of cache, ISIZE\r
+;\r
+; It is possible to use cache functionality on the I-Bus on several devices. Please \r
+; check the corresponidng data sheet if this feature is available on a certain device \r
+; and for the size of the cache. This is the general cache configuration. It is possible \r
+; to configure for each CS area, if the cache should be used.\r
+;\r
+; Note: This feature is not supported by every device. Please check the data sheet. The \r
+; feature is for example supported by MB91461R, MB91469G.\r
+;\r
+;=========================================================================================\r
+; 4.8.9 Enable CACHE for chipselect (only EXTBUS == ON)\r
+;=========================================================================================\r
+;\r
+#set CHEENA B'11111111 ; <<< en-/disable cache, CHER\r
+; ||||||||\r
+; ||||||||__ CHE0 bit, CS0 area\r
+; |||||||___ CHE1 bit, CS1 area\r
+; ||||||____ CHE2 bit, CS2 area\r
+; |||||_____ CHE3 bit, CS3 area\r
+; ||||______ CHE4 bit, CS4 area \r
+; |||_______ CHE5 bit, CS5 area \r
+; ||________ CHE6 bit, CS6 area\r
+; |_________ CHE7 bit, CS7 area \r
+;\r
+; Additional to the general cache enable setting, select which CS area should be used \r
+; with cache functionality.\r
+;\r
+; Note: Not all Chipselects are supported by the different devices. Please check the \r
+; data sheet.\r
+;\r
+; Note: This feature is not supported by every device. Please check the data sheet. The \r
+; Feature is supported by MB91461R, MB91469G.\r
+;\r
+;=========================================================================================\r
+; 4.8.10 Select External bus mode (Data lines) (only EXTBUS == ON)\r
+;=========================================================================================\r
+;\r
+#set PFUNC0 B'11111111 ;<<< Data lines or GIO, PFR00\r
+; ||||||||\r
+; ||||||||__ D24 / P00_0\r
+; |||||||___ D25 / P00_1\r
+; ||||||____ D26 / P00_2\r
+; |||||_____ D27 / P00_3\r
+; ||||______ D28 / P00_4\r
+; |||_______ D29 / P00_5\r
+; ||________ D30 / P00_6\r
+; |_________ D31 / P00_7\r
+;\r
+#set PFUNC1 B'11111111 ;<<< Data lines or GIO, PFR01\r
+; ||||||||\r
+; ||||||||__ D16 / P01_0\r
+; |||||||___ D17 / P01_1\r
+; ||||||____ D18 / P01_2\r
+; |||||_____ D19 / P01_3\r
+; ||||______ D20 / P01_4\r
+; |||_______ D21 / P01_5\r
+; ||________ D22 / P01_6\r
+; |_________ D23 / P01_7\r
+;\r
+#set PFUNC2 B'11111111 ;<<< Data lines or GIO, PFR02\r
+; ||||||||\r
+; ||||||||__ D8 / P02_0\r
+; |||||||___ D9 / P02_1\r
+; ||||||____ D10 / P02_2\r
+; |||||_____ D11 / P02_3\r
+; ||||______ D12 / P02_4\r
+; |||_______ D13 / P02_5\r
+; ||________ D14 / P02_6\r
+; |_________ D15 / P02_7\r
+;\r
+#set PFUNC3 B'11111111 ;<<< Data lines or GIO, PFR03\r
+; ||||||||\r
+; ||||||||__ D0 / P03_0\r
+; |||||||___ D1 / P03_1\r
+; ||||||____ D2 / P03_2\r
+; |||||_____ D3 / P03_3\r
+; ||||______ D4 / P03_4\r
+; |||_______ D5 / P03_5\r
+; ||________ D6 / P03_6\r
+; |_________ D7 / P03_7\r
+;\r
+; Select if the ports are set to\r
+; 1 : External bus mode, I/O for data lines or\r
+; 0 : General I/O port (GIO)\r
+;\r
+; Note: Not all data-lines are supported by the different devices. Please check the data\r
+; sheet.\r
+;\r
+;=========================================================================================\r
+; 4.8.11 Select External bus mode (Address lines) (only EXTBUS == ON)\r
+;=========================================================================================\r
+;\r
+#set PFUNC4 B'11111111 ;<<< Address lines or GIO, PFR04\r
+; ||||||||\r
+; ||||||||__ A24 / P04_0\r
+; |||||||___ A25 / P04_1\r
+; ||||||____ A26 / P04_2\r
+; |||||_____ A27 / P04_3\r
+; ||||______ A28 / P04_4\r
+; |||_______ A29 / P04_5\r
+; ||________ A30 / P04_6\r
+; |_________ A31 / P04_7\r
+;\r
+#set PFUNC5 B'11111111 ;<<< Address lines or GIO, PFR05\r
+; ||||||||\r
+; ||||||||__ A16 / P05_0\r
+; |||||||___ A17 / P05_1\r
+; ||||||____ A18 / P05_2\r
+; |||||_____ A19 / P05_3\r
+; ||||______ A20 / P05_4\r
+; |||_______ A21 / P05_5\r
+; ||________ A22 / P05_6\r
+; |_________ A23 / P05_7\r
+;\r
+#set PFUNC6 B'11111111 ;<<< Address lines or GIO, PFR06\r
+; ||||||||\r
+; ||||||||__ A8 / P06_0\r
+; |||||||___ A9 / P06_1\r
+; ||||||____ A10 / P06_2\r
+; |||||_____ A11 / P06_3\r
+; ||||______ A12 / P06_4\r
+; |||_______ A13 / P06_5\r
+; ||________ A14 / P06_6\r
+; |_________ A15 / P06_7\r
+;\r
+#set PFUNC7 B'11111111 ;<<< Address lines or GIO, PFR07\r
+; ||||||||\r
+; ||||||||__ A0 / P07_0\r
+; |||||||___ A1 / P07_1\r
+; ||||||____ A2 / P07_2\r
+; |||||_____ A3 / P07_3\r
+; ||||______ A4 / P07_4\r
+; |||_______ A5 / P07_5\r
+; ||________ A6 / P07_6\r
+; |_________ A7 / P07_7\r
+;\r
+; Select if the ports are set to\r
+; 1 : External bus mode, I/O for address lines or\r
+; 0 : General I/O port (GIO)\r
+;\r
+; Note: Not all address-lines are supported by the different devices. Please check the\r
+; data sheet.\r
+;\r
+;=========================================================================================\r
+; 4.8.12 Select External bus mode (Control signals) (only EXTBUS == ON)\r
+;=========================================================================================\r
+;\r
+#set PFUNC8 B'11111111 ;<<< Control signals or GIO, PFR08\r
+; ||||||||\r
+; ||||||||__ WRX0 / P08_0\r
+; |||||||___ WRX1 / P08_1\r
+; ||||||____ WRX2 / P08_2\r
+; |||||_____ WRX3 / P08_3\r
+; ||||______ RDX / P08_4\r
+; |||_______ BGRNTX / P08_5\r
+; ||________ BRQ / P08_6\r
+; |_________ RDY / P08_7\r
+;\r
+#set PFUNC9 B'11111111 ;<<< Control signals or GIO, PFR09\r
+; ||||||||\r
+; ||||||||__ CSX0 / P09_0\r
+; |||||||___ CSX1 / P09_1\r
+; ||||||____ CSX2 / P09_2\r
+; |||||_____ CSX3 / P09_3\r
+; ||||______ CSX4 / P09_4\r
+; |||_______ CSX5 / P09_5\r
+; ||________ CSX6 / P09_6\r
+; |_________ CSX7 / P09_7\r
+;\r
+#set PFUNC10 B'01011111 ;<<< Control signals or GIO, PFR10\r
+; ||||||||\r
+; ||||||||__ SYSCLK or !SYSCLK / P10_0 \r
+; |||||||___ ASX / P10_1 \r
+; ||||||____ BAAX / P10_2 \r
+; |||||_____ WEX / P10_3 \r
+; ||||______ MCLKO or !MCLKO / P10_4 \r
+; |||_______ MCLKI or !MCLKI/ P10_5 \r
+; ||________ MCLKE / P10_6\r
+; |_________ - \r
+;\r
+#set EPFUNC10 B'00000000 ;<<< Control signals or GIO, EPFR10\r
+; ||||||||\r
+; ||||||||__ 0:SYSCLK / 1:!SYSCLK\r
+; |||||||___ - \r
+; ||||||____ -\r
+; |||||_____ -\r
+; ||||______ 0:MCLKO / 1:!MCLKO\r
+; |||_______ 0:MCLKI / 1:!MCLKI\r
+; ||________ 0:MCLKI / 1:!MCLKI\r
+; |_________ -\r
+;\r
+;\r
+; Select if the ports are set to\r
+; 1 : External bus mode, I/O for control lines or\r
+; 0 : General I/O port (GIO)\r
+;\r
+; Note: Not all control-lines are supported by the different devices. Please check the\r
+; data sheet.\r
+;\r
+;=========================================================================================\r
+; 5 Definition of Configurations\r
+;=========================================================================================\r
+;\r
+#set NOCLOCK 0 ; do not touch CKSCR register\r
+#set MAINCLOCK 1 ; select main clock \r
+; ; MB91461R : 1/4 of oscillation input\r
+; ; Others: 1/2 of oscillation input\r
+#set MAINPLLCLOCK 2 ; select main clock with PLL\r
+#set SUBCLOCK 3 ; select subclock (if available)\r
+;\r
+#set PSCLOCK_CLKB 0x00 ; select core clock (initial)\r
+#set PSCLOCK_PLL 0x10 ; select PLL output (x)\r
+#set PSCLOCK_MAIN 0x30 ; select Main Oscillation\r
+;\r
+;=========================================================================================\r
+; 5.1 CLOCKSPEED == CLOCK_USER <<<\r
+;=========================================================================================\r
+; Must be configured only in the case of CLOCKSPEED is set to CLOCK_USER. Please see the \r
+; corresponding application note.\r
+;\r
+#if (CLOCKSPEED == CLOCK_USER )\r
+ #set CLOCKSOURCE MAINPLLCLOCK ; <<< Clocksource\r
+ #set ENABLE_SUBCLOCK OFF ; <<< Subclock: ON/OFF\r
+ #set PLLSPEED 0x010F ; <<< 0x48Ch, 0x48Dh: PLLDIVM/N ; 64 MHz\r
+ #set DIV_G 0x0F ; <<< 0x48Eh: PLLDIVG; \r
+ #set MUL_G 0x0F ; <<< 0x48Fh: PLLMULG; \r
+ ; Clock Divider\r
+ #set CPUCLOCK 0x00 ; <<< 0x486h: DIV0R_B; => /1 ; 64 MHz \r
+ #set PERCLOCK 0x03 ; <<< 0x486h: DIV0R_P; => /4 ; 16 MHz \r
+ #set EXTBUSCLOCK 0x01 ; <<< 0x487h: DIV1R_T; => /2 ; 32 MHz \r
+ ; CAN Clock\r
+ #set PSCLOCKSOURCE PSCLOCK_PLL ; <<< 0x4C0h: CANPRE; => PLLx;128 MHz\r
+ #set PSDVC 0x07 ; <<< 0x4C0h: CANPRE_DVC;=> /8 ; 16 MHz\r
+ #set CANCLOCK 0x00 ; <<< 0x4C1h: CANCKD; \r
+ ; Voltage Regulator \r
+ #set REGULATORSEL 0x06 ; <<< 0x4CEh: REGSEL;\r
+ #set REGULATORCTRL 0x00 ; <<< 0x4CFh: REGCTR;\r
+ ; Memory Controller\r
+ #set FLASHCONTROL 0x032 ; <<< 0x7002h: FCHCR;\r
+ #set FLASHREADT 0xC413 ; <<< 0x7004h: FMWT;\r
+ #set FLASHMWT2 0x10 ; <<< 0x7006h: FMWT2;\r
+#endif \r
+;\r
+;=========================================================================================\r
+; 5.2 CLOCKSPEED == NO_CLOCK\r
+;=========================================================================================\r
+;\r
+#if (CLOCKSPEED == NO_CLOCK )\r
+ #set CLOCKSOURCE NOCLOCK \r
+#endif \r
+;\r
+;=========================================================================================\r
+; 5.2 CLOCKSPEED == SUB_32KHZ_CPU__32KHZ_PER_32KHZ_EXT_32KHZ_CAN__2MHZ \r
+;=========================================================================================\r
+;\r
+#if (CLOCKSPEED == SUB_32KHZ_CPU__32KHZ_PER_32KHZ_EXT_32KHZ_CAN__2MHZ )\r
+;\r
+; Start restriction; Maximum frequency\r
+ #if (DEVICE == MB91463N) || (DEVICE == MB91461R) \r
+ #error: Frequency is not supported by this device.\r
+ #endif \r
+; End restriction\r
+;\r
+ #set CLOCKSOURCE SUBCLOCK ; Clocksource\r
+ #set ENABLE_SUBCLOCK ON ; Subclock: ON/OFF\r
+ #set PLLSPEED 0x010F ; 0x48Ch, 0x48Dh: PLLDIVM/N ; n. a.\r
+ #set DIV_G 0x0F ; 0x48Eh: PLLDIVG; \r
+ #set MUL_G 0x0F ; 0x48Fh: PLLMULG; \r
+ ; Clock Divider\r
+ #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 32 KHz \r
+ #set PERCLOCK 0x00 ; 0x486h: DIV0R_P; => /1 ; 32 KHz \r
+ #set EXTBUSCLOCK 0x00 ; 0x487h: DIV1R_T; => /1 ; 32 KHz \r
+ ; CAN Clock\r
+ #set PSCLOCKSOURCE PSCLOCK_MAIN ; 0x4C0h: CANPRE; => MAIN ; 4 MHz\r
+ #set PSDVC 0x01 ; 0x4C0h: CANPRE_DVC; => /2 ; 2 MHz\r
+ #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled\r
+ ; Voltage Regulator \r
+ #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;\r
+ #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR;\r
+ ; Memory Controller\r
+ #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;\r
+ #set FLASHREADT 0xC100 ; 0x7004h: FMWT; \r
+ #set FLASHMWT2 0x00 ; 0x7006h: FMWT2;\r
+#endif \r
+;\r
+;=========================================================================================\r
+; 5.3 CLOCKSPEED == MAIN__4MHZ_CPU___2MHZ_PER__1MHZ_EXT__1MHZ_CAN__2MHZ \r
+;=========================================================================================\r
+;\r
+#if (CLOCKSPEED == MAIN_4MHZ_CPU___2MHZ_PER__1MHZ_EXT__1MHZ_CAN__2MHZ )\r
+;\r
+; Start restriction; Maximum frequency\r
+ #if (DEVICE == MB91461R) \r
+ #error: Frequency is not supported by this device.\r
+ #endif \r
+; End restriction\r
+;\r
+ #set CLOCKSOURCE MAINCLOCK ; Clocksource\r
+ #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF\r
+ #set PLLSPEED 0x010F ; 0x48Ch, 0x48Dh: PLLDIVM/N ; n. a.\r
+ #set DIV_G 0x0F ; 0x48Eh: PLLDIVG; \r
+ #set MUL_G 0x0F ; 0x48Fh: PLLMULG; \r
+ ; Clock Divider\r
+ #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 2 MHz \r
+ #set PERCLOCK 0x01 ; 0x486h: DIV0R_P; => /2 ; 1 MHz \r
+ #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 1 MHz \r
+ ; CAN Clock\r
+ #set PSCLOCKSOURCE PSCLOCK_MAIN ; 0x4C0h: CANPRE; => PLLx ; 4 MHz\r
+ #set PSDVC 0x01 ; 0x4C0h: CANPRE_DVC; => /2 ; 2 MHz\r
+ #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled\r
+ ; Voltage Regulator \r
+ #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;\r
+ #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR;\r
+ ; Memory Controller\r
+ #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;\r
+ #set FLASHREADT 0xC100 ; 0x7004h: FMWT;\r
+ #set FLASHMWT2 0x00 ; 0x7006h: FMWT2; \r
+#endif \r
+;\r
+;=========================================================================================\r
+; 5.4 CLOCKSPEED == PLL_4MHZ__CPU__48MHZ_PER_16MHZ_EXT_24MHZ_CAN_16MHZ \r
+;=========================================================================================\r
+;\r
+#if (CLOCKSPEED == PLL_4MHZ__CPU__48MHZ_PER_16MHZ_EXT_24MHZ_CAN_16MHZ )\r
+;\r
+; Start restriction; Maximum frequency\r
+ #if (DEVICE == MB91461R) \r
+ #error: Frequency is not supported by this device.\r
+ #endif \r
+; End restriction\r
+;\r
+ #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource\r
+ #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF\r
+ #set PLLSPEED 0x010B ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 48 MHz\r
+ #set DIV_G 0x0F ; 0x48Eh: PLLDIVG; \r
+ #set MUL_G 0x0B ; 0x48Fh: PLLMULG; \r
+ ; Clock Divider\r
+ #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 48 MHz \r
+ #set PERCLOCK 0x02 ; 0x486h: DIV0R_P; => /3 ; 16 MHz \r
+ #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 24 MHz \r
+ ; CAN Clock\r
+ #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 96 MHz\r
+ #set PSDVC 0x05 ; 0x4C0h: CANPRE_DVC; => /6 ; 16 MHz\r
+ #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled\r
+ ; Voltage Regulator \r
+ #if (DEVICE == MB91469G) \r
+ #set REGULATORSEL 0x36 ; 0x4CEh: REGSEL;\r
+ #else\r
+ #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;\r
+ #endif \r
+ #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR; \r
+ ; Memory Controller\r
+ #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;\r
+ #set FLASHREADT 0xC201 ; 0x7004h: FMWT;\r
+ #set FLASHMWT2 0x00 ; 0x7006h: FMWT2; \r
+#endif \r
+;\r
+;=========================================================================================\r
+; 5.5 CLOCKSPEED == PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ \r
+;=========================================================================================\r
+;\r
+#if (CLOCKSPEED == PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ )\r
+;\r
+; Start restriction; Maximum frequency\r
+ #if (DEVICE == MB91461R) \r
+ #error: Frequency is not supported by this device.\r
+ #endif \r
+; End restriction\r
+;\r
+ #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource\r
+ #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF\r
+ #set PLLSPEED 0x010F ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 64 MHz\r
+ #set DIV_G 0x0F ; 0x48Eh: PLLDIVG; \r
+ #set MUL_G 0x0F ; 0x48Fh: PLLMULG; \r
+ ; Clock Divider\r
+ #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 64 MHz \r
+ #set PERCLOCK 0x03 ; 0x486h: DIV0R_P; => /4 ; 16 MHz \r
+ #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 32 MHz \r
+ ; CAN Clock\r
+ #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 128 MHz\r
+ #set PSDVC 0x07 ; 0x4C0h: CANPRE_DVC; => /8 ; 16 MHz\r
+ #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled\r
+ ; Voltage Regulator \r
+ #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;\r
+ #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR;\r
+ ; Memory Controller\r
+ #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;\r
+ #set FLASHREADT 0xC413 ; 0x7004h: FMWT;\r
+ #set FLASHMWT2 0x10 ; 0x7006h: FMWT2;\r
+#endif \r
+;\r
+;=========================================================================================\r
+; 5.6 CLOCKSPEED == PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_27MHZ_CAN_20MHZ \r
+;=========================================================================================\r
+;\r
+#if (CLOCKSPEED == PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_27MHZ_CAN_20MHZ )\r
+;\r
+; Start restriction; Maximum frequency\r
+ #if (DEVICE == MB91461R) \r
+ #error: Frequency is not supported by this device.\r
+ #endif \r
+; End restriction\r
+;\r
+ #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource\r
+ #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF\r
+ #set PLLSPEED 0x0113 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 80 MHz\r
+ #set DIV_G 0x0F ; 0x48Eh: PLLDIVG; \r
+ #set MUL_G 0x13 ; 0x48Fh: PLLMULG; \r
+ ; Clock Divider\r
+ #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 80 MHz \r
+ #set PERCLOCK 0x03 ; 0x486h: DIV0R_P; => /4 ; 20 MHz \r
+ #set EXTBUSCLOCK 0x02 ; 0x487h: DIV1R_T; => /3 ; 27 MHz \r
+ ; CAN Clock\r
+ #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 160 MHz\r
+ #set PSDVC 0x07 ; 0x4C0h: CANPRE_DVC; => /8 ; 8 MHz\r
+ #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled\r
+ ; Voltage Regulator \r
+ #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;\r
+ #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR;\r
+ ; Memory Controller\r
+ #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;\r
+ #set FLASHREADT 0xC413 ; 0x7004h: FMWT;\r
+ #set FLASHMWT2 0x10 ; 0x7006h: FMWT2;\r
+#endif \r
+;\r
+;=========================================================================================\r
+; 5.7 CLOCKSPEED == PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_40MHZ_CAN_20MHZ \r
+;=========================================================================================\r
+;\r
+#if (CLOCKSPEED == PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_40MHZ_CAN_20MHZ )\r
+;\r
+; Start restriction; Maximum frequency\r
+ #if (DEVICE == MB91461R) \r
+ #error: Frequency is not supported by this device.\r
+ #endif \r
+; End restriction\r
+;\r
+ #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource\r
+ #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF\r
+ #set PLLSPEED 0x0113 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 80 MHz\r
+ #set DIV_G 0x0F ; 0x48Eh: PLLDIVG; \r
+ #set MUL_G 0x13 ; 0x48Fh: PLLMULG; \r
+ ; Clock Divider\r
+ #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 80 MHz \r
+ #set PERCLOCK 0x03 ; 0x486h: DIV0R_P; => /4 ; 20 MHz \r
+ #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 40 MHz \r
+ ; CAN Clock\r
+ #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 160 MHz\r
+ #set PSDVC 0x07 ; 0x4C0h: CANPRE_DVC; => /8 ; 8 MHz\r
+ #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled\r
+ ; Voltage Regulator \r
+ #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;\r
+ #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR;\r
+ ; Memory Controller\r
+ #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;\r
+ #set FLASHREADT 0xC413 ; 0x7004h: FMWT;\r
+ #set FLASHMWT2 0x10 ; 0x7006h: FMWT2;\r
+#endif \r
+;\r
+;=========================================================================================\r
+; 5.8 CLOCKSPEED == PLL_4MHZ__CPU__96MHZ_PER_16MHZ_EXT_48MHZ_CAN_16MHZ \r
+;=========================================================================================\r
+;\r
+#if (CLOCKSPEED == PLL_4MHZ__CPU__96MHZ_PER_16MHZ_EXT_48MHZ_CAN_16MHZ )\r
+;\r
+; Start restriction; Maximum frequency\r
+ #if (DEVICE == MB91464A) || (DEVICE == MB91465K) || (DEVICE == MB91463N) ||\\r
+ (DEVICE == MB91461R) || (DEVICE == MB91467R)\r
+ #error: Frequency is not supported by this device.\r
+ #endif \r
+; End restriction\r
+;\r
+ #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource\r
+ #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF\r
+ #set PLLSPEED 0x0117 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 96 MHz\r
+ #set DIV_G 0x0F ; 0x48Eh: PLLDIVG; \r
+ #set MUL_G 0x17 ; 0x48Fh: PLLMULG; \r
+ ; Clock Divider\r
+ #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 64 MHz \r
+ #set PERCLOCK 0x05 ; 0x486h: DIV0R_P; => /6 ; 16 MHz \r
+ #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 32 MHz \r
+ ; CAN Clock\r
+ #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 192 MHz\r
+ #set PSDVC 0x0B ; 0x4C0h: CANPRE_DVC; => /12 ; 16 MHz\r
+ #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled\r
+ ; Voltage Regulator \r
+ #if (DEVICE == MB91469G) \r
+ #set REGULATORSEL 0x36 ; 0x4CEh: REGSEL;\r
+ #else\r
+ #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;\r
+ #endif \r
+ #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR; \r
+ ; Memory Controller\r
+ #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;\r
+ #set FLASHREADT 0xC413 ; 0x7004h: FMWT;\r
+ #set FLASHMWT2 0x10 ; 0x7006h: FMWT2;\r
+#endif \r
+;\r
+;=========================================================================================\r
+; 5.9 CLOCKSPEED == PLL_4MHZ__CPU_100MHZ_PER_20MHZ_EXT_50MHZ_CAN_20MHZ \r
+;=========================================================================================\r
+;\r
+#if (CLOCKSPEED == PLL_4MHZ__CPU_100MHZ_PER_20MHZ_EXT_50MHZ_CAN_20MHZ )\r
+;\r
+; Start restriction; Maximum frequency\r
+ #if (DEVICE == MB91464A) || (DEVICE == MB91465K) || (DEVICE == MB91463N) ||\\r
+ (DEVICE == MB91461R) || (DEVICE == MB91467R) || (DEVICE == MB91467D)\r
+ #error: Frequency is not supported by this device.\r
+ #endif \r
+; End restriction\r
+;\r
+ #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource\r
+ #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF\r
+ #set PLLSPEED 0x0118 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 100 MHz\r
+ #set DIV_G 0x0F ; 0x48Eh: PLLDIVG; \r
+ #set MUL_G 0x17 ; 0x48Fh: PLLMULG; \r
+ ; Clock Divider\r
+ #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 100 MHz \r
+ #set PERCLOCK 0x04 ; 0x486h: DIV0R_P; => /5 ; 20 MHz \r
+ #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 50 MHz \r
+ ; CAN Clock\r
+ #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 200 MHz\r
+ #set PSDVC 0x09 ; 0x4C0h: CANPRE_DVC; => /10 ; 20 MHz\r
+ #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled\r
+ ; Voltage Regulator \r
+ #if (DEVICE == MB91469G) \r
+ #set REGULATORSEL 0x36 ; 0x4CEh: REGSEL;\r
+ #else\r
+ #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;\r
+ #endif \r
+ #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR; \r
+ ; Memory Controller\r
+ #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;\r
+ #set FLASHREADT 0xC413 ; 0x7004h: FMWT;\r
+ #set FLASHMWT2 0x10 ; 0x7006h: FMWT2;\r
+#endif \r
+;\r
+;=========================================================================================\r
+; 5.10 CLOCKSPEED == PLL_10MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ \r
+;=========================================================================================\r
+;\r
+#if (CLOCKSPEED == PLL_10MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ )\r
+;\r
+; Start restriction; Maximum frequency\r
+ #if (DEVICE == MB91464A) || (DEVICE == MB91467B) || (DEVICE == MB91467C) ||\\r
+ (DEVICE == MB91467D) || (DEVICE == MB91469G) || (DEVICE == MB91465K) ||\\r
+ (DEVICE == MB91463N) || (DEVICE == MB91467R) || (DEVICE == MB91465X) \r
+ #error: Frequency is not supported by this device.\r
+ #endif \r
+; End restriction\r
+;\r
+ #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource\r
+ #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF\r
+ #set PLLSPEED 0x0105 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 60 MHz\r
+ #set DIV_G 0x0B ; 0x48Eh: PLLDIVG; \r
+ #set MUL_G 0x1F ; 0x48Fh: PLLMULG; \r
+ ; Clock Divider\r
+ #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 60 MHz \r
+ #set PERCLOCK 0x02 ; 0x486h: DIV0R_P; => /3 ; 20 MHz \r
+ #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 30 MHz \r
+ ; CAN Clock\r
+ #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 120 MHz\r
+ #set PSDVC 0x05 ; 0x4C0h: CANPRE_DVC; => /6 ; 20 MHz\r
+ #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled\r
+ ; Voltage Regulator \r
+ ; -\r
+ ; Memory Controller\r
+ ; -\r
+#endif \r
+;\r
+;=========================================================================================\r
+; 5.11 CLOCKSPEED == PLL_20MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ \r
+;=========================================================================================\r
+;\r
+#if (CLOCKSPEED == PLL_20MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ )\r
+;\r
+; Start restriction; Maximum frequency\r
+ #if (DEVICE == MB91464A) || (DEVICE == MB91467B) || (DEVICE == MB91467C) ||\\r
+ (DEVICE == MB91467D) || (DEVICE == MB91469G) || (DEVICE == MB91465K) ||\\r
+ (DEVICE == MB91463N) || (DEVICE == MB91467R) || (DEVICE == MB91465X) \r
+ #error: Frequency is not supported by this device.\r
+ #endif \r
+; End restriction\r
+;\r
+ #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource\r
+ #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF\r
+ #set PLLSPEED 0x0102 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 60 MHz\r
+ #set DIV_G 0x0F ; 0x48Eh: PLLDIVG; \r
+ #set MUL_G 0x1F ; 0x48Fh: PLLMULG; \r
+ ; Clock Divider\r
+ #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 60 MHz \r
+ #set PERCLOCK 0x02 ; 0x486h: DIV0R_P; => /3 ; 20 MHz \r
+ #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 30 MHz \r
+ ; CAN Clock\r
+ #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 120 MHz\r
+ #set PSDVC 0x05 ; 0x4C0h: CANPRE_DVC; => /6 ; 20 MHz\r
+ #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled\r
+ ; Voltage Regulator \r
+ ; -\r
+ ; Memory Controller\r
+ ; -\r
+#endif \r
+; \r
+;=========================================================================================\r
+; 6 Section and Data Declaration\r
+;=========================================================================================\r
+\r
+ .export __start \r
+ .import _main\r
+ .import _RAM_INIT\r
+ .import _ROM_INIT\r
+ \r
+#if CLIBINIT == ON \r
+ .export __exit \r
+ .import _exit\r
+ .import __stream_init\r
+#endif\r
+\r
+#if CPLUSPLUS == ON\r
+ .export __abort\r
+ .import ___call_dtors\r
+ .import _atexit\r
+#endif\r
+;=========================================================================================\r
+; 6.1 Define Stack Size\r
+;=========================================================================================\r
+ .SECTION SSTACK, STACK, ALIGN=4\r
+#if STACK_RESERVE == ON\r
+ .EXPORT __systemstack, __systemstack_top\r
+ __systemstack:\r
+ .RES.B STACK_SYS_SIZE\r
+ __systemstack_top: \r
+#endif\r
+ \r
+ .SECTION USTACK, STACK, ALIGN=4\r
+#if STACK_RESERVE == ON\r
+ .EXPORT __userstack, __userstack_top\r
+ __userstack:\r
+ .RES.B STACK_USR_SIZE\r
+ __userstack_top:\r
+ \r
+#endif\r
+;=========================================================================================\r
+; 6.2 Define Sections\r
+;=========================================================================================\r
+ .section DATA, data, align=4\r
+ .section INIT, data, align=4\r
+ .section IRAM, code, align=4\r
+ .section CONST, const, align=4\r
+ .section INTVECT, const, align=4 \r
+ \r
+#if I_RAM \r
+ .import _RAM_IRAM\r
+ .import _ROM_IRAM\r
+#endif\r
+ \r
+#if (DEVICE != MB91461R)\r
+ #if (DEVICE == MB91469G)\r
+ .section SECURITY_VECTORS, code, locate = 0x248000\r
+ #else \r
+ .section SECURITY_VECTORS, code, locate = 0x148000\r
+ #endif\r
+ \r
+ #if (BOOT_FLASH_SEC == OFF) \r
+ .data.w 0xFFFFFFFF\r
+ .data.w 0xFFFFFFFF\r
+ .data.w 0xFFFFFFFF\r
+ .data.w 0xFFFFFFFF \r
+ #else\r
+ .res.w 4\r
+ #endif \r
+#endif \r
+ \r
+#if CPLUSPLUS == ON\r
+ .section EXT_CTOR_DTOR, const, align=4 ; C++ constructors\r
+#endif \r
+ \r
+;-----------------------------------------------------------------------------------------\r
+; MACRO Clear RC Watchdog\r
+;-----------------------------------------------------------------------------------------\r
+#macro ClearRCwatchdog\r
+ LDI #0x4C7,R7 ; clear RC watchdog\r
+ BANDL #0x7,@R7\r
+#endm\r
+;-----------------------------------------------------------------------------------------\r
+; MACRO WAIT_LOOP\r
+;-----------------------------------------------------------------------------------------\r
+#macro wait_loop loop_number\r
+#local _wait64_loop\r
+ LDI #loop_number, R0\r
+_wait64_loop:\r
+ ADD #-1, R0\r
+ BNE _wait64_loop\r
+#endm\r
+ .section CODE, code, align=4\r
+ .section CODE_START, code, align=4\r
+\r
+\r
+;=========================================================================================\r
+; 7. S T A R T \r
+;=========================================================================================\r
+__start: ; start point \r
+startnop: \r
+ NOP \r
+; \r
+ ANDCCR #0xEF ; disable interrupts \r
+ STILM #LOW_PRIOR ; set interrupt level to low prior\r
+ ClearRCwatchdog ; clear harware watchdog\r
+\r
+;=========================================================================================\r
+; 7.1 Initialise Stack Pointer and Table Base Register\r
+;=========================================================================================\r
+#if STACKUSE == SYSSTACK \r
+ ORCCR #0x20\r
+ LDI #__userstack_top, SP ; initialize SP\r
+ ANDCCR #0xDF\r
+ LDI #__systemstack_top, SP ; initialize SP\r
+#endif\r
+\r
+#if STACKUSE == USRSTACK\r
+ ANDCCR #0xDF\r
+ LDI #__systemstack_top, SP ; initialize SP\r
+ ORCCR #0x20\r
+ LDI #__userstack_top, SP ; initialize SP\r
+#endif\r
+\r
+ LDI #INTVECT, R0 ; set Table Base\r
+smd_tbr: \r
+ MOV R0, TBR \r
+\r
+#if (CLOCKSOURCE != NOCLOCK) \r
+;=========================================================================================\r
+; 7.2 Check for CSV reset and set CSV\r
+;=========================================================================================\r
+; Start restriction; No clock supervisor (CSV)\r
+#if (DEVICE != MB91461R) && (DEVICE != MB91467R) && (DEVICE != MB91463N)\r
+; End restriction\r
+ LDI:20 #0x04AD, R0 ; CSVCR\r
+ BORL #0x8, @R0 ; Enable Main Osc CSV\r
+ BTSTH #0x4, @R0 ; Check for Main Osc missing\r
+ BEQ NoMAINCSVreset ; Main osc available -> branch \r
+ ; to NoCSVreset\r
+ BANDL #0x7, @R0 ; Disable Main Osc CSV\r
+ \r
+ LDI #noClockStartup, R0 ; Main Clock missing -> no\r
+ JMP @R0 ; clock startup\r
+ \r
+NoMAINCSVreset: \r
+\r
+\r
+ BORL #0x4, @R0 ; Enable Sub Osc CSV\r
+ BTSTH #0x2, @R0 ; Check for Sub Osc missing\r
+ BEQ NoSUBCSVreset ; Sub osc available -> branch \r
+ ; to NoCSVreset\r
+ BANDL #0xB, @R0 ; Disable Sub Osc SCSV\r
+#if (CLOCKSOURCE == SUBCLOCK)\r
+ LDI #noClockStartup, R0 ; Sub Clock missing -> no\r
+ JMP @R0 ; clock startup\r
+#endif \r
+NoSUBCSVreset: \r
+#endif \r
+;=========================================================================================\r
+; 7.3 Check Clock Condition\r
+;=========================================================================================\r
+ LDI #0x484, R0 ; Check for Default Values\r
+ LDI #0x0F, R1 \r
+ ANDB R1, @R0\r
+ BEQ clock_startup \r
+\r
+;=========================================================================================\r
+; 7.4 Restore Default Settings after Reset\r
+;=========================================================================================\r
+;=========================================================================================\r
+; 7.4.1 Disable Clock Modulator\r
+;=========================================================================================\r
+ LDI #0x04BB, R0 ; Clock Modulator Control Reg\r
+ BANDL #0xD, @R0 ; Disable Frequency modulation\r
+FMODwait: \r
+ BTSTL #8, @R0 ; Wait until Frequency modulation\r
+ BNE FMODwait ; is disabled\r
+ \r
+ BANDL #0xE, @R0 ; Power down clock modulator\r
+\r
+;=========================================================================================\r
+; 7.4.2 Check if running on Sub Clock, change to Main Clock\r
+;=========================================================================================\r
+ LDI:20 #0x0484,R12 ; Check if running on sub clock\r
+ LDUB @R12,R0\r
+ LDI:8 #0x3,R1\r
+ AND R1,R0\r
+ CMP #0x3,R0\r
+ BNE notOnSubClock\r
+ \r
+ LDI:20 #0x04CC,R12 ; Check if Main Clock is stopped\r
+ BTSTL #1, @R12\r
+ BEQ mainNotStopped\r
+\r
+ BANDL #0xE, @R12 ; Start Main Oscillation\r
+ \r
+ LDI #0x4C8, R0 ; Main Stabilisation Wait Time\r
+ LDI #0x04, R1 ; 32.7 ms\r
+ AND R1, @R0 \r
+ BORH #0x02, @R0 \r
+ \r
+ mainStabTime: ; Wait for stabilisation time\r
+ ClearRCwatchdog ; clear harware watchdog\r
+ BTSTH #8, @R0\r
+ BEQ mainStabTime\r
+ LDI #0x0, R1\r
+ STB R1, @R0\r
+\r
+mainNotStopped: \r
+ LDI:20 #0x0484, R12 ; disable sub clock as source\r
+ BANDL #0xD, @R12 ; Clock source = 0x01 (Main/2) \r
+ \r
+notOnSubClock:\r
+;=========================================================================================\r
+; 7.4.3 Disable Sub Clock\r
+;=========================================================================================\r
+#if ENABLE_SUBCLOCK != ON\r
+ LDI #0x0484, R0 ; Clock source control reg CLKR\r
+ BANDL #0x7, @R0 ; Disable PLL\r
+#endif \r
+\r
+;=========================================================================================\r
+; 7.4.4 Check if running on PLL, Gear Down PLL\r
+;=========================================================================================\r
+ LDI:20 #0x0484,R12 ; Check if running on PLL\r
+ LDUB @R12,R0\r
+ LDI:8 #0x3,R1\r
+ AND R1,R0\r
+ CMP #0x2,R0\r
+ BNE notOnPll\r
+ \r
+ LDI:20 #0x0490, R11 ; clear flags \r
+ LDI:8 #0x0,R1 \r
+ STB R1, @R11\r
+ LDI #0x04,R1\r
+ STB R1, @R11 ; Set Flag for Simulator; no Effekt on\r
+ ; Emulator \r
+\r
+ BANDL #0xC, @R12 ; disable PLL as clock source \r
+ ; Clock Source = 0x00 (Main/2)\r
+ \r
+ LDI:20 #0x048E,R12 ; check if DivG != 0\r
+ LDUB @R12, R0\r
+ LDI:8 #0xFF,R1\r
+ AND R1,R0\r
+ BEQ notOnPll\r
+ \r
+gearDownLoop: \r
+ ClearRCwatchdog ; clear harware watchdog\r
+ BTSTL #4, @R11 ; Gear Down\r
+ BEQ gearDownLoop ; \r
+ \r
+ LDI #0x00,R1 ; Clear Flags\r
+ STB R1, @R11 ; \r
+ \r
+notOnPll:\r
+;=========================================================================================\r
+; 7.4.5 Disable PLL\r
+;=========================================================================================\r
+ LDI #0x0484, R0 ; Clock source control reg CLKR\r
+ BANDL #0xB, @R0 ; Disable PLL\r
+ \r
+;=========================================================================================\r
+; 7.4.6 Set to Main Clock\r
+;=========================================================================================\r
+ LDI:20 #0x0484,R12 ; Check if running on PLL\r
+ BANDL #0xC, @R12 ; disable PLL as clock source \r
+ ; Clock Source = 0x00 (Main/2)\r
+\r
+clock_startup:\r
+;=========================================================================================\r
+; 7.5 Set Memory Controller\r
+;=========================================================================================\r
+; Start restriction; No embedded flash\r
+#if DEVICE != MB91461R\r
+; End restriction\r
+ LDI #0x7002, R1 ; FLASH Controller Reg.\r
+ LDI #FLASHCONTROL, R2 ; Flash Controller Settings\r
+ STH R2, @R1 ; set register\r
+ LDI #0x7004, R1 ; FLASH Memory Wait Timing Reg.\r
+ LDI #FLASHREADT, R2 ; wait settings\r
+ STH R2, @R1 ; set register\r
+ LDI #0x7006, R1 ; FLASH Memory Wait Timing Reg.\r
+ LDI #FLASHMWT2, R2 ; wait settings\r
+ STB R2, @R1 ; set register \r
+#endif \r
+ ClearRCwatchdog \r
+ \r
+;=========================================================================================\r
+; 7.6 Clock startup\r
+;=========================================================================================\r
+;=========================================================================================\r
+; 7.6.1 Set Voltage Regulator Settings\r
+;=========================================================================================\r
+; Start restriction; No regulator settings\r
+#if DEVICE != MB91461R\r
+; End restriction\r
+ LDI #0x04CF, R0 ; REGCTR\r
+ LDI #REGULATORCTRL, R1\r
+ STB R1, @R0\r
+\r
+ LDI #0x04CE, R0 ; REGSEL\r
+ LDI #REGULATORSEL, R1\r
+ STB R1, @R0\r
+#endif\r
+\r
+;=========================================================================================\r
+; 7.6.2 Power on Clock Modulator - Clock Modulator Part I\r
+;=========================================================================================\r
+#if CLOMO == ON \r
+ LDI #0x04BB, R0 ; Clock Modulator Control Reg\r
+ LDI #0x11, R1 ; Load value to Power on CM\r
+ ORB R1, @R0 ; Power on clock modulaor\r
+#endif\r
+\r
+;=========================================================================================\r
+; 7.6.3 Set CLKR Register w/o Clock Mode\r
+;=========================================================================================\r
+; Set Clock source (Base Clock) for the three clock tree selections\r
+; This select Base clock is used to select afterwards the 3\r
+; Clocks for the diffenrent internal trees.\r
+; When PLL is used, first pll multiplication ratio is set and PLL is\r
+; enabled. After waiting the PLL stabilisation time via timebase\r
+; timer, PLL clock is selected as clock source. \r
+ LDI #0x048C, R0 ; PLL Cntl Reg. PLLDIVM/N\r
+ LDI:20 #PLLSPEED, R1\r
+ STH R1, @R0\r
+\r
+ LDI #0x048E, R0 ; PLL Cntl Reg. PLLDIVG\r
+ LDI #DIV_G, R1\r
+ STB R1, @R0\r
+\r
+ LDI #0x048F, R0 ; PLL Cntl Reg. PLLMULG\r
+ LDI #MUL_G, R1\r
+ STB R1, @R0\r
+\r
+;=========================================================================================\r
+; 7.6.4 Start PLL \r
+;=========================================================================================\r
+#if ( ( CLOCKSOURCE == MAINPLLCLOCK ) || ( PSCLOCKSOURCE == PSCLOCK_PLL ) )\r
+ LDI #0x0484, R0 ; Clock source control reg CLKR\r
+ LDI #0x04, R1 ; Use PLL x1, enable PLL \r
+ ORB R1, @R0 ; store data to CLKR register\r
+#endif\r
+ \r
+ \r
+#if ENABLE_SUBCLOCK == ON\r
+ LDI #0x0484, R0 ; Clock source control reg CLKR\r
+ LDI #0x08, R1 ; enable subclock operation\r
+ ORB R1, @R0 ; store data to CLKR register\r
+ LDI #0x4CA, R0 ; Sub Clock oszilation \r
+ LDI #0x00, R1 ; stabilitsation time = 32 ms\r
+ AND R1, @R0 \r
+ BORH #0x02, @R0 \r
+#endif \r
+ \r
+;=========================================================================================\r
+; 7.6.5 Wait for PLL oscillation stabilisation\r
+;=========================================================================================\r
+#if ((CLOCKSOURCE==MAINPLLCLOCK)||(PSCLOCKSOURCE==PSCLOCK_PLL))\r
+ LDI #0x0482, R12 ; TimeBaseTimer TBCR\r
+ LDI #0x00, R1 ; set 1024 us @ 2 MHz \r
+ STB R1, @R12\r
+\r
+ BANDH #7, @R12 ; clear interrupt flag\r
+ \r
+ LDI #0x0483, R0 ; clearTimeBaseTimer CTBR\r
+ LDI #0xA5, R1 \r
+ STB R1, @R0\r
+ LDI #0x5A, R1 \r
+ STB R1, @R0\r
+ \r
+ BANDH #7, @R12 ; clear interrupt flag\r
+ BORH #8, @R12 ; set interrupt flag for simulator\r
+\r
+PLLwait: \r
+ ClearRCwatchdog ; clear harware watchdog\r
+ BTSTH #8, @R12\r
+ BEQ PLLwait\r
+#endif\r
+\r
+;=========================================================================================\r
+; 7.6.6 Set clocks \r
+;=========================================================================================\r
+;=========================================================================================\r
+; 7.6.6.1 Set CPU and peripheral clock \r
+;=========================================================================================\r
+; CPU and peripheral clock are set in one register\r
+ LDI #0x0486, R2 ; Set DIVR0 (CPU-clock (CLKB) \r
+ LDI #((CPUCLOCK << 4) + PERCLOCK), R3 ; Load CPU clock setting\r
+ STB R3, @R2 \r
+;=========================================================================================\r
+; 7.6.6.2 Set External Bus interface clock\r
+;=========================================================================================\r
+; set External Bus clock\r
+; Be aware to do smooth clock setting, to avoid wrong clock setting\r
+; Take care, always write 0 to the lower 4 bits of DIVR1 register\r
+ LDI #0x0487, R2 ; Set DIVR1 \r
+ LDI #(EXTBUSCLOCK << 4), R3 ; Load Peripheral clock setting\r
+ STB R3, @R2 \r
+ \r
+;=========================================================================================\r
+; 7.6.6.3 Set CAN clock prescaler\r
+;=========================================================================================\r
+; Set CAN Prescaler, only clock relevant parameter \r
+ LDI #0x04C0, R0 ; Set CAN ClockParameter Register\r
+ LDI #(PSCLOCKSOURCE + PSDVC), R1 ; Load Divider\r
+ STB R1, @R0 ; Set Divider\r
+; enable CAN clocks\r
+ LDI #0x04c1, R0 ; Set CAN Clock enable Register\r
+ LDI #CANCLOCK, R1 ; Load CANCLOCK\r
+ STB R1, @R0 ; set CANCLOCK\r
+\r
+;=========================================================================================\r
+; 7.6.6.4 Switch Main Clock Mode\r
+;=========================================================================================\r
+#if CLOCKSOURCE == MAINCLOCK\r
+\r
+;=========================================================================================\r
+; 7.6.6.5 Switch Subclock Mode\r
+;=========================================================================================\r
+#elif ( (CLOCKSOURCE == SUBCLOCK) )\r
+ #if ENABLE_SUBCLOCK == ON\r
+ LDI #0x4CA, R12\r
+subStabTime: \r
+ ClearRCwatchdog ; clear harware watchdog\r
+ BTSTH #8, @R12 ; wait until sub clock stabilisation\r
+ BEQ subStabTime ; time is over\r
+ LDI #0x0, R1\r
+ STB R1, @R12\r
+\r
+ LDI #0x0484, R0 ; Clock source control reg CLKR\r
+ LDI #0x01, R1 ; load value to select main clock\r
+ ORB R1, @R0 ; enable main clock (1/2 external) \r
+ LDI #0x03, R1 ; load value to select subclock\r
+ ORB R1, @R0 ; enable subclock as clock source \r
+ #else\r
+ #error: Wrong setting! The clock source is subclock, but the subclock is disabled.\r
+ #endif\r
+\r
+;=========================================================================================\r
+; 7.6.7 Switch to PLL Mode\r
+;=========================================================================================\r
+#elif ( (CLOCKSOURCE == MAINPLLCLOCK) )\r
+\r
+#if (DIV_G != 0x00)\r
+ LDI #0x0490, R0 ; PLL Ctrl Register \r
+ LDI #0x00,R1\r
+ STB R1, @R0 ; Clear Flag\r
+ LDI #0x01,R1\r
+ STB R1, @R0 ; Set Flag for Simulator; no Effekt on\r
+#endif ; Emulator\r
+ \r
+ LDI #0x0484, R3 ; Clock source control reg CLKR\r
+ BORL #0x2, @R3 ; enable PLL as clock source \r
+ \r
+#if (DIV_G != 0x00) \r
+gearUpLoop: \r
+ ClearRCwatchdog ; clear harware watchdog\r
+ LDUB @R0, R2 ; LOAD PLLCTR to R2\r
+ AND R1, R2 ; GRUP, counter reach 0\r
+ BEQ gearUpLoop\r
+\r
+ LDI #0x00,R1\r
+ STB R1, @R0 ; Clear Gear-Up Flag\r
+#endif \r
+ \r
+#endif\r
+\r
+;=========================================================================================\r
+; 7.6.8 Enable Frequncy Modulation - Clock Modulator Part II\r
+;=========================================================================================\r
+#if CLOMO == ON ; Only applicable if Modulator is on\r
+ LDI #0x04B8, R0 ; Clock Modulation Parameter Reg\r
+ LDI #CMPR, R1 ; Load CMP value\r
+ STH R1, @R0 ; Store CMP value in CMPR\r
+\r
+ LDI #0x04BB, R0 ; Clock Modulator Control Reg\r
+ LDI #0x13, R1 ; Load value to FM on CM\r
+ ORB R1, @R0 ; FM on \r
+#endif\r
+\r
+#endif\r
+noClockStartup:\r
+\r
+;=========================================================================================\r
+; 7.7 Set BusInterface\r
+;=========================================================================================\r
+; Start restriction; No ext. bus interface\r
+#if (DEVICE != MB91464A) && (DEVICE != MB91467C) && (DEVICE != MB91465K) && \\r
+ (DEVICE != MB91463N) && (DEVICE != MB91465X)\r
+; End restriction\r
+#if (EXTBUS == ON) \r
+;=========================================================================================\r
+; 7.7.1 Disable all CS\r
+;=========================================================================================\r
+; Start restriction; Flashless device\r
+#if(DEVICE != MB91461R)\r
+; End restriction\r
+ LDI #0x0680, R3 ; chip select enable register CSER\r
+ LDI #(0x00), R2 ; load disable settings \r
+smd_cs: \r
+ ANDB R2, @R3 ; set register \r
+#endif \r
+\r
+;=========================================================================================\r
+; 7.7.2 Clear TCR Register\r
+;=========================================================================================\r
+ LDI #0x0683, R1 ; Pin/Timing Control Register TCR\r
+ BORH #0x6,@R1 ; load timing settings \r
+\r
+;=========================================================================================\r
+; 7.7.3 Set CS0\r
+;=========================================================================================\r
+#if CS0\r
+ LDI #0x0640, R1 ; area select reg ASR0, ACR0 \r
+ LDI #(AREASEL0<<16)+CONFIGCS0, R0 ; load settings\r
+ ST R0, @R1 ; set registers\r
+ \r
+ LDI #0x660, R1 ; area wait register awr0\r
+ LDI #WAITREG0, R2 ; wait settings\r
+ STH R2, @R1 ; set register\r
+#endif\r
+\r
+;=========================================================================================\r
+; 7.7.4 Set CS1 \r
+;=========================================================================================\r
+#if CS1 \r
+ LDI #0x0644, R1 ; area select reg ASR1, ACR1 \r
+ LDI #(AREASEL1<<16)+CONFIGCS1, R0 ; load settings\r
+ ST R0, @R1 ; set registers\r
+\r
+ LDI #0x662, R1 ; area wait register awr1\r
+ LDI #WAITREG1, R2 ; wait settings\r
+ STH R2, @R1 ; set register\r
+#endif\r
+smd_cs_mb91461r:\r
+;=========================================================================================\r
+; 7.7.5 Set CS2 \r
+;=========================================================================================\r
+#if CS2\r
+ LDI #0x0648, R1 ; area select reg ASR2, ACR2 \r
+ LDI #(AREASEL2<<16)+CONFIGCS2, R0 ; load settings\r
+ ST R0, @R1 ; set registers\r
+ LDI #0x664, R1 ; area wait register awr2\r
+ LDI #WAITREG2, R2 ; wait settings\r
+ STH R2, @R1 ; set register\r
+#endif\r
+;=========================================================================================\r
+; 7.7.6 Set CS3 \r
+;=========================================================================================\r
+#if CS3\r
+ LDI #0x064C, R1 ; area select reg ASR3, ACR3 \r
+ LDI #(AREASEL3<<16)+CONFIGCS3, R0 ; load settings\r
+ ST R0, @R1 ; set registers\r
+ LDI #0x666, R1 ; area wait register awr3\r
+ LDI #WAITREG3, R2 ; wait settings\r
+ STH R2, @R1 ; set register\r
+#endif\r
+;=========================================================================================\r
+; 7.7.7 Set CS4 \r
+;=========================================================================================\r
+#if CS4\r
+ LDI #0x0650, R1 ; area select reg ASR4, ACR4 \r
+ LDI #(AREASEL4<<16)+CONFIGCS4, R0 ; load settings\r
+ ST R0, @R1 ; set registers\r
+ LDI #0x668, R1 ; area wait register awr4\r
+ LDI #WAITREG4, R2 ; wait settings\r
+ STH R2, @R1 ; set register\r
+#endif\r
+;=========================================================================================\r
+; 7.7.8 Set CS5 \r
+;=========================================================================================\r
+#if CS5\r
+ LDI #0x0654, R1 ; area select reg ASR5, ACR5 \r
+ LDI #(AREASEL5<<16)+CONFIGCS5, R0 ; load settings\r
+ ST R0, @R1 ; set registers\r
+ LDI #0x66A, R1 ; area wait register awr5\r
+ LDI #WAITREG5, R2 ; wait settings\r
+ STH R2, @R1 ; set register\r
+#endif\r
+;=========================================================================================\r
+; 7.7.9 Set CS6\r
+;=========================================================================================\r
+#if (CS6) \r
+ LDI #0x0658, R1 ; area select reg ASR6, ACR6 \r
+ LDI #(AREASEL6<<16)+CONFIGCS6, R0 ; load settings\r
+ ST R0, @R1 ; set registers\r
+ LDI #0x66C, R1 ; area wait register awr6\r
+ LDI #WAITREG6, R2 ; wait settings\r
+ STH R2, @R1 ; set register\r
+#endif\r
+;=========================================================================================\r
+; 7.7.10 Set CS7 \r
+;=========================================================================================\r
+#if CS7\r
+ LDI #0x065C, R1 ; area select reg ASR7, ACR7 \r
+ LDI #(AREASEL7<<16)+CONFIGCS7, R0 ; load settings\r
+ ST R0, @R1 ; set registers\r
+ LDI #0x66E, R1 ; area wait register awr7\r
+ LDI #WAITREG7, R2 ; wait settings\r
+ STH R2, @R1 ; set register\r
+#endif \r
+;=========================================================================================\r
+; 7.7.11 Set special SDRAM config register \r
+;=========================================================================================\r
+#if (SDRAM)\r
+ LDI #0x670, R1 ; SDRAM memory config register\r
+ LDI #MEMCON, R2 ; wait settings\r
+ STB R2, @R1 ; set register\r
+#endif\r
+\r
+;=========================================================================================\r
+; 7.7.12 set Port Function Register\r
+;=========================================================================================\r
+;=========================================================================================\r
+; 7.7.12.1 set PFR00 Register. External bus mode (D[24-31]) or General purpose port\r
+;=========================================================================================\r
+ LDI #0x0D80, R1 ; Port Function Register 0, (PFR00)\r
+ LDI #PFUNC0, R0 ; load port settings \r
+ STB R0, @R1 ; set register \r
+;=========================================================================================\r
+; 7.7.12.2 set PFR01 Register. External bus mode (D[16-23]) or General purpose port\r
+;=========================================================================================\r
+ LDI #0x0D81, R1 ; Port Function Register 1, (PFR01)\r
+ LDI #PFUNC1, R0 ; load port settings \r
+ STB R0, @R1 ; set register \r
+;=========================================================================================\r
+; 7.7.12.3 set PFR02 Register. External bus mode (D[8-15]) or General purpose port\r
+;=========================================================================================\r
+ LDI #0x0D82, R1 ; Port Function Register 2, (PFR02)\r
+ LDI #PFUNC2, R0 ; load port settings \r
+ STB R0, @R1 ; set register \r
+;=========================================================================================\r
+; 7.7.12.4 set PFR03 Register. External bus mode (D[0-7]) or General purpose port\r
+;=========================================================================================\r
+ LDI #0x0D83, R1 ; Port Function Register 3, (PFR03)\r
+ LDI #PFUNC3, R0 ; load port settings \r
+ STB R0, @R1 ; set register \r
+;=========================================================================================\r
+; 7.7.12.5 set PFR04 Register. External bus mode (Adr[24-31]) or General purpose port\r
+;=========================================================================================\r
+ LDI #0x0D84, R1 ; Port Function Register 4, (PFR04)\r
+ LDI #PFUNC4, R0 ; load port settings \r
+ STB R0, @R1 ; set register \r
+;=========================================================================================\r
+; 7.7.12.6 set PFR05 Register. External bus mode (Adr[16-23]) or General purpose port\r
+;=========================================================================================\r
+ LDI #0x0D85, R1 ; Port Function Register 5, (PFR05)\r
+ LDI #PFUNC5, R0 ; load port settings \r
+ STB R0, @R1 ; set register \r
+;=========================================================================================\r
+; 7.7.12.7 set PFR06 Register. External bus mode (Adr[8-15]) or General purpose port\r
+;=========================================================================================\r
+ LDI #0x0D86, R1 ; Port Function Register 6, (PFR06)\r
+ LDI #PFUNC6, R0 ; load port settings \r
+ STB R0, @R1 ; set register \r
+;=========================================================================================\r
+; 7.7.12.8 set PFR07 Register. External bus mode (Adr[0-7]) or General purpose port\r
+;=========================================================================================\r
+ LDI #0x0D87, R1 ; Port Function Register 7, (PFR07)\r
+ LDI #PFUNC7, R0 ; load port settings \r
+ STB R0, @R1 ; set register \r
+;=========================================================================================\r
+; 7.7.12.9 set PFR08 Register. External bus mode (Control Signals) or GIO port\r
+;=========================================================================================\r
+ LDI #0x0D88, R1 ; Port Function Register 8, (PFR08)\r
+ LDI #PFUNC8, R0 ; load port settings \r
+ STB R0, @R1 ; set register \r
+;=========================================================================================\r
+; 7.7.12.10 set PFR09 Register. External bus mode (Control Signals) or GIO port\r
+;=========================================================================================\r
+ LDI #0x0D89, R1 ; Port Function Register 9, (PFR09)\r
+ LDI #PFUNC9, R0 ; load port settings \r
+ STB R0, @R1 ; set register \r
+;=========================================================================================\r
+; 7.7.12.11 set PFR10 Register. External bus mode (Control Signals) or GIO port\r
+;=========================================================================================\r
+ LDI #0x0D8A, R1 ; Port Function Register 10, (PFR10)\r
+ LDI #PFUNC10, R0 ; load port settings \r
+ STB R0, @R1 ; set register \r
+;=========================================================================================\r
+; 7.7.12.12 set EPFR10 Register. External bus mode (Control Signals) or GIO port\r
+;=========================================================================================\r
+ LDI #0x0DCA, R1 ; Extended PFR 10, (EPFR10)\r
+ LDI #EPFUNC10, R0 ; load port settings \r
+ STB R0, @R1 ; set register \r
+;=========================================================================================\r
+; 7.7.13 Set TCR Register\r
+;=========================================================================================\r
+ LDI #0x0683, R1 ; Pin/Timing Control Register TCR\r
+ LDI #TIMECONTR, R0 ; load timing settings \r
+ STB R0, @R1 ; set register\r
+;=========================================================================================\r
+; 7.7.14 Enable CACHE for selected CS\r
+;=========================================================================================\r
+ LDI #0x0681, R3 ; chip select enable register CSER\r
+ LDI #CHEENA, R2 \r
+ ORB R2, @R3 \r
+;=========================================================================================\r
+; 7.7.15 set SDRAM Referesh Control Register\r
+;=========================================================================================\r
+#if (SDRAM)\r
+ LDI #0x0684, R1 ; Refresh Control Register RCR\r
+ LDI #REFRESH, R0 ; load refresh settings \r
+ STH R0, @R1 ; set register \r
+ LDI #0x0008, R2\r
+ OR R2, R0 ; Set PON bit to 1 \r
+ STH R0, @R1 ; set register \r
+#endif\r
+;=========================================================================================\r
+; 7.7.16 Enable used CS\r
+;=========================================================================================\r
+ LDI #0x0680, R3 ; chip select enable register CSER\r
+ LDI #ENACSX, R2 \r
+; Start restriction; Flashless device\r
+#if (DEVICE == MB91461R)\r
+; End restriction\r
+emu_sram_cs_mb91461r: \r
+ ANDB R2, @R3 ; set register\r
+#else \r
+ ORB R2, @R3\r
+#endif \r
+;=========================================================================================\r
+; 7.7.17 I-cache on/off\r
+;=========================================================================================\r
+; Start restriction; No cache\r
+#if (DEVICE == MB91461R) || (DEVICE == MB91469G) || (DEVICE == others) \r
+; End restriction\r
+ #if CACHE\r
+ #if CACHE_SIZE == C1024\r
+ LDI #0x03C7, R1 ; Cache size register ISIZE\r
+ LDI #0x00, R2\r
+ STB R2, @R1\r
+ LDI #0x03E7, R1 ; Cache control reg ICHCR\r
+ LDI #0x07, R2 ; Release entry locks, flush and enable \r
+ STB R2, @R1 ; cache \r
+ #elif CACHE_SIZE == C2048\r
+ LDI #0x03C7, R1 ; Cache size register ISIZE\r
+ LDI #0x01, R2\r
+ STB R2, @R1\r
+ LDI #0x03E7, R1 ; Cache control reg ICHCR\r
+ LDI #0x07, R2 ; Release entry locks, flush and enable \r
+ STB R2, @R1 ; cache\r
+ #elif CACHE_SIZE == C4096\r
+ LDI #0x03C7, R1 ; Cache size register ISIZE\r
+ LDI #0x02, R2\r
+ STB R2, @R1\r
+ LDI #0x03E7, R1 ; Cache control reg ICHCR\r
+ LDI #0x07, R2 ; Release entry locks, flush and enable \r
+ STB R2, @R1 ; cache\r
+ #else \r
+ #error: Wrong Cache size selected!\r
+ #endif \r
+ #else\r
+ LDI #0x03E7, R1 ; Cache control reg ICHCR\r
+ LDI #0x06, R2 ; Release entry locks, flush and disable\r
+ STB R2, @R1 ; cache\r
+ #endif\r
+#endif\r
+#elif (EXTBUS == OFF) \r
+;=========================================================================================\r
+; 7.7.18 set Port Function Register to general as I/O-Port\r
+;=========================================================================================\r
+;=========================================================================================\r
+; 7.7.18.1 set PFR00 Register. External bus mode as General purpose port\r
+;=========================================================================================\r
+ LDI #0x0D80, R1 ; Port Function Register 0, (PFR00)\r
+ LDI #0x00, R0 ; load port settings \r
+ STB R0, @R1 ; set register \r
+;=========================================================================================\r
+; 7.7.18.2 set PFR01 Register. External bus mode as General purpose port\r
+;=========================================================================================\r
+ LDI #0x0D81, R1 ; Port Function Register 1, (PFR01)\r
+ LDI #0x00, R0 ; load port settings \r
+ STB R0, @R1 ; set register \r
+;=========================================================================================\r
+; 7.7.18.3 set PFR02 Register. External bus mode as General purpose port\r
+;=========================================================================================\r
+ LDI #0x0D82, R1 ; Port Function Register 2, (PFR02)\r
+ LDI #0x00, R0 ; load port settings \r
+ STB R0, @R1 ; set register \r
+;=========================================================================================\r
+; 7.7.18.4 set PFR03 Register. External bus mode as General purpose port\r
+;=========================================================================================\r
+ LDI #0x0D83, R1 ; Port Function Register 3, (PFR03)\r
+ LDI #0x00, R0 ; load port settings \r
+ STB R0, @R1 ; set register \r
+;=========================================================================================\r
+; 7.7.18.5 set PFR04 Register. External bus mode as General purpose port\r
+;=========================================================================================\r
+ LDI #0x0D84, R1 ; Port Function Register 4, (PFR04)\r
+ LDI #0x00, R0 ; load port settings \r
+ STB R0, @R1 ; set register \r
+;=========================================================================================\r
+; 7.7.18.6 set PFR05 Register. External bus mode as General purpose port\r
+;=========================================================================================\r
+ LDI #0x0D85, R1 ; Port Function Register 5, (PFR05)\r
+ LDI #0x00, R0 ; load port settings \r
+ STB R0, @R1 ; set register \r
+;=========================================================================================\r
+; 7.7.18.7 set PFR06 Register. External bus mode as General purpose port\r
+;=========================================================================================\r
+ LDI #0x0D86, R1 ; Port Function Register 6, (PFR06)\r
+ LDI #0x00, R0 ; load port settings \r
+ STB R0, @R1 ; set register \r
+;=========================================================================================\r
+; 7.7.18.8 set PFR07 Register. External bus mode as General purpose port\r
+;=========================================================================================\r
+ LDI #0x0D87, R1 ; Port Function Register 7, (PFR07)\r
+ LDI #0x00, R0 ; load port settings \r
+ STB R0, @R1 ; set register \r
+;=========================================================================================\r
+; 7.7.18.9 set PFR08 Register. External bus mode as General purpose port\r
+;=========================================================================================\r
+ LDI #0x0D88, R1 ; Port Function Register 8, (PFR08)\r
+ LDI #0x00, R0 ; load port settings \r
+ STB R0, @R1 ; set register \r
+;=========================================================================================\r
+; 7.7.18.10 set PFR09 Register. External bus mode as General purpose port\r
+;=========================================================================================\r
+ LDI #0x0D89, R1 ; Port Function Register 9, (PFR09)\r
+ LDI #0x00, R0 ; load port settings \r
+ STB R0, @R1 ; set register \r
+;=========================================================================================\r
+; 7.7.18.11 set PFR10 Register. External bus mode as General purpose port\r
+;=========================================================================================\r
+ LDI #0x0D8A, R1 ; Port Function Register 10, (PFR10)\r
+ LDI #0x00, R0 ; load port settings \r
+ STB R0, @R1 ; set register \r
+;=========================================================================================\r
+; 7.7.18.12 set EPFR10 Register. External bus mode as General purpose port\r
+;=========================================================================================\r
+ LDI #0x0DCA, R1 ; Extended PFR10, (EPFR10)\r
+ LDI #0x00, R0 ; load port settings \r
+ STB R0, @R1 ; set register \r
+;=========================================================================================\r
+\r
+#elif (EXTBUS == DEFAULT)\r
+ NOP\r
+smd_cs_mb91461r:\r
+emu_sram_cs_mb91461r:\r
+smd_cs:\r
+#endif ; #endif (EXTBUS)\r
+#endif ; #endif (excl. devices)\r
+ ClearRCwatchdog\r
+\r
+;=========================================================================================\r
+; 7.8 Copy code from Flash to I-RAM \r
+;=========================================================================================\r
+#if I_RAM == ON\r
+ LDI #_RAM_IRAM, R0\r
+ LDI #_ROM_IRAM, R1\r
+ LDI #sizeof(IRAM), R13\r
+ CMP #0, R13\r
+ BEQ copy_iram_end\r
+copy_iram1: \r
+ ADD #-1, R13\r
+ LDUB @(R13, R1), R12\r
+ BNE:D copy_iram1\r
+ STB R12, @(R13, R0)\r
+copy_iram_end: \r
+ ClearRCwatchdog\r
+#endif\r
+\r
+;=========================================================================================\r
+; 7.9 Fill stacks\r
+;=========================================================================================\r
+#if STACK_FILL == ON\r
+ LDI #STACK_PATTERN, R0\r
+ LDI #SSTACK, R1\r
+ LDI #sizeof(SSTACK), R2\r
+ CMP #0, R2\r
+ BEQ:D fill_sstack_end\r
+ MOV R2, R13\r
+ LDI #3, R12\r
+ AND R2, R12\r
+ BEQ:D fill_sstack2\r
+ MOV R2, R3\r
+ SUB R12, R3\r
+ LDI #0x3, R4\r
+ SUB R12, R4\r
+ LSL #0x3, R4 \r
+ LDI #STACK_PATTERN, R5\r
+ LSR R4, R5 \r
+ LDI #0x8, R4\r
+fill_sstack1:\r
+ ADD #-1, R13\r
+ LSR R4, R5 \r
+ CMP R3, R13\r
+ BHI:D fill_sstack1\r
+ STB R5, @(R13, R1)\r
+ CMP #0, R3\r
+ BEQ:D fill_sstack_end\r
+fill_sstack2:\r
+ ADD #-4, R13\r
+ BGT:D fill_sstack2\r
+ ST R0, @(R13, R1)\r
+fill_sstack_end:\r
+\r
+ LDI #STACK_PATTERN, R0\r
+ LDI #USTACK, R1\r
+ LDI #sizeof(USTACK), R2\r
+ CMP #0, R2\r
+ BEQ:D fill_ustack_end\r
+ MOV R2, R13\r
+ LDI #3, R12\r
+ AND R2, R12\r
+ BEQ:D fill_ustack2\r
+ MOV R2, R3\r
+ SUB R12, R3\r
+ LDI #0x3, R4\r
+ SUB R12, R4\r
+ LSL #0x3, R4 \r
+ LDI #STACK_PATTERN, R5\r
+ LSR R4, R5 \r
+ LDI #0x8, R4\r
+fill_ustack1:\r
+ ADD #-1, R13\r
+ LSR R4, R5 \r
+ CMP R3, R13\r
+ BHI:D fill_ustack1\r
+ STB R5, @(R13, R1)\r
+ CMP #0, R3\r
+ BEQ:D fill_ustack_end\r
+fill_ustack2:\r
+ ADD #-4, R13\r
+ BGT:D fill_ustack2\r
+ ST R0, @(R13, R1)\r
+fill_ustack_end:\r
+ ClearRCwatchdog\r
+#endif \r
+\r
+;=========================================================================================\r
+; Standard C startup\r
+;=========================================================================================\r
+;=========================================================================================\r
+; 7.10 Clear data \r
+;=========================================================================================\r
+; clear DATA section\r
+; According to ANSI, the DATA section must be cleared during start-up\r
+ LDI:8 #0, R0\r
+ LDI #sizeof DATA &~0x3, R1\r
+ LDI #DATA, R13\r
+ CMP #0, R1\r
+ BEQ data_clr1\r
+data_clr0:\r
+ ADD2 #-4, R1\r
+ BNE:D data_clr0\r
+ ST R0, @(R13, R1)\r
+data_clr1:\r
+ LDI:8 #sizeof DATA & 0x3, R1\r
+ LDI #DATA + (sizeof DATA & ~0x3), R13\r
+\r
+ CMP #0, R1\r
+ BEQ data_clr_end\r
+data_clr2:\r
+ ADD2 #-1, R1\r
+ BNE:D data_clr2\r
+ STB R0, @(R13, R1)\r
+data_clr_end:\r
+ ClearRCwatchdog\r
+ \r
+;=========================================================================================\r
+; 7.11 Copy Init section from ROM to RAM\r
+;=========================================================================================\r
+; copy rom\r
+; All initialised data's (e.g. int i=1) must be stored in ROM/FLASH area. \r
+; (start value)\r
+; The Application must copy the Section (Init) into the RAM area.\r
+ LDI #_RAM_INIT, R0\r
+ LDI #_ROM_INIT, R1\r
+ LDI #sizeof(INIT), R2\r
+ CMP #0, R2\r
+ BEQ:D copy_rom_end\r
+ LDI #3, R12\r
+ AND R2, R12\r
+ BEQ:D copy_rom2\r
+ MOV R2, R13\r
+ MOV R2, R3\r
+ SUB R12, R3\r
+copy_rom1:\r
+ ADD #-1, R13\r
+ LDUB @(R13, R1), R12\r
+ CMP R3, R13\r
+ BHI:D copy_rom1\r
+ STB R12, @(R13, R0)\r
+ CMP #0, R3\r
+ BEQ:D copy_rom_end\r
+copy_rom2:\r
+ ADD #-4, R13\r
+ LD @(R13, R1), R12\r
+ BGT:D copy_rom2\r
+ ST R12, @(R13, R0)\r
+copy_rom_end:\r
+ ClearRCwatchdog\r
+\r
+;=========================================================================================\r
+; 7.12 C library initialization\r
+;=========================================================================================\r
+#if CLIBINIT == ON\r
+ CALL32 __stream_init, r12 ; initialise library \r
+#endif\r
+;=========================================================================================\r
+; 7.13 call C++ constructors\r
+;=========================================================================================\r
+#if CPLUSPLUS == ON\r
+ LDI #___call_dtors, r4\r
+ CALL32 _atexit, r12\r
+\r
+ LDI #EXT_CTOR_DTOR, r8\r
+ LDI #EXT_CTOR_DTOR + sizeof(EXT_CTOR_DTOR), r9\r
+ CMP r9, r8\r
+ BEQ L1\r
+L0:\r
+ LD @r8, r10\r
+ CALL:D @r10\r
+ ADD #4, r8\r
+ CMP r9, r8\r
+ BC L0\r
+L1:\r
+#endif\r
+\r
+start_main:\r
+;=========================================================================================\r
+; 7.14 call main routine\r
+;=========================================================================================\r
+ ClearRCwatchdog ; clear harware watchdog\r
+ LDI:8 #0, r4 ; Set the 1st parameter for main to 0.\r
+ CALL32:d _main, r12\r
+ LDI:8 #0, r5 ; Set the 2nd parameter for main to 0.\r
+#if CLIBINIT == ON\r
+ CALL32 _exit, r12\r
+ __exit:\r
+#endif\r
+\r
+#if CPLUSPLUS == ON\r
+ __abort:\r
+#endif\r
+\r
+;=========================================================================================\r
+; 7.15 Return from main function\r
+;=========================================================================================\r
+end: \r
+ BRA end \r
+ .end __start\r
--- /dev/null
+/* FR IO-MAP HEADER FILE */\r
+/* ===================== */\r
+/* CREATED BY IO-WIZARD V2.26 */\r
+/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */\r
+/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */\r
+/* ELIGIBILITY FOR ANY PURPOSES. */\r
+/* (C) Fujitsu Microelectronics Europe GmbH */\r
+/* */\r
+/* ************************************************************************* */\r
+/* Fujitsu Microelectronics Europe GmbH */\r
+/* Pittlerstrasse 47, 63225 Langen */\r
+/* Tel.: +49 (6103) 690-0, Fax -122 */\r
+/* */\r
+/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */\r
+/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */\r
+/* ELIGIBILITY FOR ANY PURPOSES */\r
+/* (C) Fujitsu Microelectronics Europe GmbH */\r
+/* ************************************************************************* */\r
+/* ---------------------------------------------------------------------- */\r
+/* Id: MB91465K.h,v 1.5 2007/01/04 11:04:48 meffen Exp */\r
+/* ---------------------------------------------------------------------- */\r
+/* Id: MB91465K.h,v 1.5 2007/01/04 11:04:48 meffen Exp */\r
+/* - removed LCD and Sound Controller */\r
+/* Id: MB91465K.h,v 1.4 2006/11/30 14:39:18 meffen Exp */\r
+/* - -added registers: ADER (32Bit access) */\r
+/* ADCS (16Bit access) */\r
+/* ADCR (16Bit access) */\r
+/* ADCT (16Bit access) */\r
+\r
+/* ASSEMBLER DEFINITIONS : */\r
+\r
+#ifdef __IO_DEFINE\r
+#define __IO_EXTERN\r
+#else\r
+#define __IO_EXTERN extern volatile\r
+#endif\r
+#ifdef __IO_DEFINE\r
+#pragma asm\r
+ .GLOBAL _pdr14, _pdr15, _pdr16, _pdr17, _pdr18, _pdr19\r
+ .GLOBAL _pdr20, _pdr21, _pdr22, _pdr24, _pdr26, _pdr27\r
+ .GLOBAL _pdr28, _pdr29, _eirr0, _enir0, _elvr0, _eirr1\r
+ .GLOBAL _enir1, _elvr1, _dicr, _hrcl, _rbsync, _scr00\r
+ .GLOBAL _smr00, _ssr00, _rdr00, _tdr00, _escr00, _eccr00\r
+ .GLOBAL _scr01, _smr01, _ssr01, _rdr01, _tdr01, _escr01\r
+ .GLOBAL _eccr01, _scr02, _smr02, _ssr02, _rdr02, _tdr02\r
+ .GLOBAL _escr02, _eccr02, _scr03, _smr03, _ssr03, _rdr03\r
+ .GLOBAL _tdr03, _escr03, _eccr03, _scr04, _smr04, _ssr04\r
+ .GLOBAL _rdr04, _tdr04, _escr04, _eccr04, _fsr04, _fcr04\r
+ .GLOBAL _bgr00, _bgr100, _bgr000, _bgr01, _bgr101, _bgr001\r
+ .GLOBAL _bgr02, _bgr102, _bgr002, _bgr03, _bgr103, _bgr003\r
+ .GLOBAL _bgr04, _bgr104, _bgr004, _ibcr0, _ibsr0, _itba0\r
+ .GLOBAL _itbah0, _itbal0, _itmk0, _itmkh0, _itmkl0, _ismk0\r
+ .GLOBAL _isba0, _idar0, _iccr0, _gcn10, _gcn20, _gcn11\r
+ .GLOBAL _gcn21, _gcn12, _gcn22, _ptmr00, _pcsr00, _pdut00\r
+ .GLOBAL _pcn00, _pcnh00, _pcnl00, _ptmr01, _pcsr01, _pdut01\r
+ .GLOBAL _pcn01, _pcnh01, _pcnl01, _ptmr02, _pcsr02, _pdut02\r
+ .GLOBAL _pcn02, _pcnh02, _pcnl02, _ptmr03, _pcsr03, _pdut03\r
+ .GLOBAL _pcn03, _pcnh03, _pcnl03, _ptmr04, _pcsr04, _pdut04\r
+ .GLOBAL _pcn04, _pcnh04, _pcnl04, _ptmr05, _pcsr05, _pdut05\r
+ .GLOBAL _pcn05, _pcnh05, _pcnl05, _ptmr06, _pcsr06, _pdut06\r
+ .GLOBAL _pcn06, _pcnh06, _pcnl06, _ptmr07, _pcsr07, _pdut07\r
+ .GLOBAL _pcn07, _pcnh07, _pcnl07, _ptmr08, _pcsr08, _pdut08\r
+ .GLOBAL _pcn08, _pcnh08, _pcnl08, _ptmr09, _pcsr09, _pdut09\r
+ .GLOBAL _pcn09, _pcnh09, _pcnl09, _ptmr10, _pcsr10, _pdut10\r
+ .GLOBAL _pcn10, _pcnh10, _pcnl10, _ptmr11, _pcsr11, _pdut11\r
+ .GLOBAL _pcn11, _pcnh11, _pcnl11, _ics01, _ics23, _ipcp0\r
+ .GLOBAL _ipcp1, _ipcp2, _ipcp3, _ocs01, _ocs23, _occp0\r
+ .GLOBAL _occp1, _occp2, _occp3, _aderh, _aderl, _ader\r
+ .GLOBAL _adcs1, _adcs0, _adcs, _adcr1, _adcr0, _adcr\r
+ .GLOBAL _adct1, _adct0, _adct, _adsch, _adech, _tmrlr0\r
+ .GLOBAL _tmr0, _tmcsr0, _tmcsrh0, _tmcsrl0, _tmrlr1, _tmr1\r
+ .GLOBAL _tmcsr1, _tmcsrh1, _tmcsrl1, _tmrlr2, _tmr2, _tmcsr2\r
+ .GLOBAL _tmcsrh2, _tmcsrl2, _tmrlr3, _tmr3, _tmcsr3, _tmcsrh3\r
+ .GLOBAL _tmcsrl3, _tmrlr4, _tmr4, _tmcsr4, _tmcsrh4, _tmcsrl4\r
+ .GLOBAL _tmrlr5, _tmr5, _tmcsr5, _tmcsrh5, _tmcsrl5, _tmrlr6\r
+ .GLOBAL _tmr6, _tmcsr6, _tmcsrh6, _tmcsrl6, _tmrlr7, _tmr7\r
+ .GLOBAL _tmcsr7, _tmcsrh7, _tmcsrl7, _tcdt0, _tccs0, _tcdt1\r
+ .GLOBAL _tccs1, _tcdt2, _tccs2, _tcdt3, _tccs3, _dmaca0\r
+ .GLOBAL _dmacb0, _dmaca1, _dmacb1, _dmaca2, _dmacb2, _dmaca3\r
+ .GLOBAL _dmacb3, _dmaca4, _dmacb4, _dmacr, _ics45, _ics67\r
+ .GLOBAL _ipcp4, _ipcp5, _ipcp6, _ipcp7, _ocs45, _ocs67\r
+ .GLOBAL _occp4, _occp5, _occp6, _occp7, _tcdt4, _tccs4\r
+ .GLOBAL _tcdt5, _tccs5, _tcdt6, _tccs6, _tcdt7, _tccs7\r
+ .GLOBAL _roms, _bsd0, _bsd1, _bsdc, _bsrr, _icr00\r
+ .GLOBAL _icr01, _icr02, _icr03, _icr04, _icr05, _icr06\r
+ .GLOBAL _icr07, _icr08, _icr09, _icr10, _icr11, _icr12\r
+ .GLOBAL _icr13, _icr14, _icr15, _icr16, _icr17, _icr18\r
+ .GLOBAL _icr19, _icr20, _icr21, _icr22, _icr23, _icr24\r
+ .GLOBAL _icr25, _icr26, _icr27, _icr28, _icr29, _icr30\r
+ .GLOBAL _icr31, _icr32, _icr33, _icr34, _icr35, _icr36\r
+ .GLOBAL _icr37, _icr38, _icr39, _icr40, _icr41, _icr42\r
+ .GLOBAL _icr43, _icr44, _icr45, _icr46, _icr47, _icr48\r
+ .GLOBAL _icr49, _icr50, _icr51, _icr52, _icr53, _icr54\r
+ .GLOBAL _icr55, _icr56, _icr57, _icr58, _icr59, _icr60\r
+ .GLOBAL _icr61, _icr62, _icr63, _rsrr, _stcr, _tbcr\r
+ .GLOBAL _ctbr, _clkr, _wpr, _divr0, _divr1, _plldivm\r
+ .GLOBAL _plldivn, _plldivg, _pllmulg, _pllctrl, _oscc1, _oscs1\r
+ .GLOBAL _oscc2, _oscs2, _porten, _wtcer, _wtcr, _wtbr\r
+ .GLOBAL _wthr, _wtmr, _wtsr, _csvtr, _csvcr, _cscfg\r
+ .GLOBAL _cmcfg, _cucr, _cutd, _cutr1, _cutr2, _cmpr\r
+ .GLOBAL _cmcr, _cmt1, _cmt2, _canpre, _canckd, _lvsel\r
+ .GLOBAL _lvdet, _hwwde, _hwwd, _oscrh, _oscrl, _wpcrh\r
+ .GLOBAL _wpcrl, _osccr, _regsel, _regctr, _modr, _pdrd14\r
+ .GLOBAL _pdrd15, _pdrd16, _pdrd17, _pdrd18, _pdrd19, _pdrd20\r
+ .GLOBAL _pdrd21, _pdrd22, _pdrd24, _pdrd26, _pdrd27, _pdrd28\r
+ .GLOBAL _pdrd29, _ddr14, _ddr15, _ddr16, _ddr17, _ddr18\r
+ .GLOBAL _ddr19, _ddr20, _ddr21, _ddr22, _ddr24, _ddr26\r
+ .GLOBAL _ddr27, _ddr28, _ddr29, _pfr14, _pfr15, _pfr16\r
+ .GLOBAL _pfr17, _pfr18, _pfr19, _pfr20, _pfr21, _pfr22\r
+ .GLOBAL _pfr24, _pfr26, _pfr27, _pfr28, _pfr29, _epfr14\r
+ .GLOBAL _epfr15, _epfr16, _epfr17, _epfr18, _epfr19, _epfr20\r
+ .GLOBAL _epfr21, _epfr22, _epfr24, _epfr26, _epfr27, _epfr29\r
+ .GLOBAL _podr14, _podr15, _podr16, _podr17, _podr18, _podr19\r
+ .GLOBAL _podr20, _podr21, _podr22, _podr24, _podr26, _podr27\r
+ .GLOBAL _podr28, _podr29, _pilr14, _pilr15, _pilr16, _pilr17\r
+ .GLOBAL _pilr18, _pilr19, _pilr20, _pilr21, _pilr22, _pilr24\r
+ .GLOBAL _pilr26, _pilr27, _pilr28, _pilr29, _epilr14, _epilr15\r
+ .GLOBAL _epilr16, _epilr17, _epilr18, _epilr19, _epilr20, _epilr21\r
+ .GLOBAL _epilr22, _epilr24, _epilr26, _epilr27, _epilr28, _epilr29\r
+ .GLOBAL _pper14, _pper15, _pper16, _pper17, _pper18, _pper19\r
+ .GLOBAL _pper20, _pper21, _pper22, _pper24, _pper26, _pper27\r
+ .GLOBAL _pper28, _pper29, _ppcr14, _ppcr15, _ppcr16, _ppcr17\r
+ .GLOBAL _ppcr18, _ppcr19, _ppcr20, _ppcr21, _ppcr22, _ppcr24\r
+ .GLOBAL _ppcr26, _ppcr27, _ppcr28, _ppcr29, _dmasa0, _dmada0\r
+ .GLOBAL _dmasa1, _dmada1, _dmasa2, _dmada2, _dmasa3, _dmada3\r
+ .GLOBAL _dmasa4, _dmada4, _fmcs, _fmcr, _fchcr, _fmwt\r
+ .GLOBAL _fmwt2, _fmps, _fmac, _fcha0, _fcha1, _fscr0\r
+ .GLOBAL _fscr1, _ctrlr4, _statr4, _errcnt4, _btr4, _intr4\r
+ .GLOBAL _testr4, _brper4, _brpe4, _if1creq4, _if1cmsk4, _if1msk124\r
+ .GLOBAL _if1msk24, _if1msk14, _if1arb124, _if1arb24, _if1arb14, _if1mctr4\r
+ .GLOBAL _if1dta124, _if1dta14, _if1dta24, _if1dtb124, _if1dtb14, _if1dtb24\r
+ .GLOBAL _if1dta_swp124, _if1dta_swp24, _if1dta_swp14, _if1dtb_swp124, _if1dtb_swp24, _if1dtb_swp14\r
+ .GLOBAL _if2creq4, _if2cmsk4, _if2msk124, _if2msk24, _if2msk14, _if2arb124\r
+ .GLOBAL _if2arb24, _if2arb14, _if2mctr4, _if2dta124, _if2dta14, _if2dta24\r
+ .GLOBAL _if2dtb124, _if2dtb14, _if2dtb24, _if2dta_swp124, _if2dta_swp24, _if2dta_swp14\r
+ .GLOBAL _if2dtb_swp124, _if2dtb_swp24, _if2dtb_swp14, _treqr124, _treqr24, _treqr14\r
+ .GLOBAL _treqr344, _newdt124, _newdt24, _newdt14, _intpnd124, _intpnd24\r
+ .GLOBAL _intpnd14, _msgval124, _msgval24, _msgval14, _bctrl, _bstat\r
+ .GLOBAL _biac, _boac, _birq, _bcr0, _bcr1, _bad0\r
+ .GLOBAL _bad1, _bad2, _bad3, _bad4, _bad5, _bad6\r
+ .GLOBAL _bad7, _fsv1, _bsv1, _fsv2, _bsv2\r
+\r
+_pdr14 .EQU 0x00000E\r
+PDR14 .EQU 0x00000E /* Port Data Register */\r
+_pdr15 .EQU 0x00000F\r
+PDR15 .EQU 0x00000F\r
+_pdr16 .EQU 0x000010\r
+PDR16 .EQU 0x000010\r
+_pdr17 .EQU 0x000011\r
+PDR17 .EQU 0x000011\r
+_pdr18 .EQU 0x000012\r
+PDR18 .EQU 0x000012\r
+_pdr19 .EQU 0x000013\r
+PDR19 .EQU 0x000013\r
+_pdr20 .EQU 0x000014\r
+PDR20 .EQU 0x000014\r
+_pdr21 .EQU 0x000015\r
+PDR21 .EQU 0x000015\r
+_pdr22 .EQU 0x000016\r
+PDR22 .EQU 0x000016\r
+_pdr24 .EQU 0x000018\r
+PDR24 .EQU 0x000018\r
+_pdr26 .EQU 0x00001A\r
+PDR26 .EQU 0x00001A\r
+_pdr27 .EQU 0x00001B\r
+PDR27 .EQU 0x00001B\r
+_pdr28 .EQU 0x00001C\r
+PDR28 .EQU 0x00001C\r
+_pdr29 .EQU 0x00001D\r
+PDR29 .EQU 0x00001D\r
+_eirr0 .EQU 0x000030\r
+EIRR0 .EQU 0x000030 /* External Interrupt 0-7 */\r
+_enir0 .EQU 0x000031\r
+ENIR0 .EQU 0x000031\r
+_elvr0 .EQU 0x000032\r
+ELVR0 .EQU 0x000032\r
+_eirr1 .EQU 0x000034\r
+EIRR1 .EQU 0x000034 /* External Interrupt 8-15 */\r
+_enir1 .EQU 0x000035\r
+ENIR1 .EQU 0x000035\r
+_elvr1 .EQU 0x000036\r
+ELVR1 .EQU 0x000036\r
+_dicr .EQU 0x000038\r
+DICR .EQU 0x000038 /* DLYI/I-unit */\r
+_hrcl .EQU 0x000039\r
+HRCL .EQU 0x000039\r
+_rbsync .EQU 0x00003A\r
+RBSYNC .EQU 0x00003A /* R-Bus Sync */\r
+_scr00 .EQU 0x000040\r
+SCR00 .EQU 0x000040 /* USART (LIN) 0 */\r
+_smr00 .EQU 0x000041\r
+SMR00 .EQU 0x000041\r
+_ssr00 .EQU 0x000042\r
+SSR00 .EQU 0x000042\r
+_rdr00 .EQU 0x000043\r
+RDR00 .EQU 0x000043\r
+_tdr00 .EQU 0x000043\r
+TDR00 .EQU 0x000043\r
+_escr00 .EQU 0x000044\r
+ESCR00 .EQU 0x000044\r
+_eccr00 .EQU 0x000045\r
+ECCR00 .EQU 0x000045\r
+_scr01 .EQU 0x000048\r
+SCR01 .EQU 0x000048 /* USART (LIN) 1 */\r
+_smr01 .EQU 0x000049\r
+SMR01 .EQU 0x000049\r
+_ssr01 .EQU 0x00004A\r
+SSR01 .EQU 0x00004A\r
+_rdr01 .EQU 0x00004B\r
+RDR01 .EQU 0x00004B\r
+_tdr01 .EQU 0x00004B\r
+TDR01 .EQU 0x00004B\r
+_escr01 .EQU 0x00004C\r
+ESCR01 .EQU 0x00004C\r
+_eccr01 .EQU 0x00004D\r
+ECCR01 .EQU 0x00004D\r
+_scr02 .EQU 0x000050\r
+SCR02 .EQU 0x000050 /* USART (LIN) 2 */\r
+_smr02 .EQU 0x000051\r
+SMR02 .EQU 0x000051\r
+_ssr02 .EQU 0x000052\r
+SSR02 .EQU 0x000052\r
+_rdr02 .EQU 0x000053\r
+RDR02 .EQU 0x000053\r
+_tdr02 .EQU 0x000053\r
+TDR02 .EQU 0x000053\r
+_escr02 .EQU 0x000054\r
+ESCR02 .EQU 0x000054\r
+_eccr02 .EQU 0x000055\r
+ECCR02 .EQU 0x000055\r
+_scr03 .EQU 0x000058\r
+SCR03 .EQU 0x000058 /* USART (LIN) 3 */\r
+_smr03 .EQU 0x000059\r
+SMR03 .EQU 0x000059\r
+_ssr03 .EQU 0x00005A\r
+SSR03 .EQU 0x00005A\r
+_rdr03 .EQU 0x00005B\r
+RDR03 .EQU 0x00005B\r
+_tdr03 .EQU 0x00005B\r
+TDR03 .EQU 0x00005B\r
+_escr03 .EQU 0x00005C\r
+ESCR03 .EQU 0x00005C\r
+_eccr03 .EQU 0x00005D\r
+ECCR03 .EQU 0x00005D\r
+_scr04 .EQU 0x000060\r
+SCR04 .EQU 0x000060 /* USART (LIN) 4 with FIFO */\r
+_smr04 .EQU 0x000061\r
+SMR04 .EQU 0x000061\r
+_ssr04 .EQU 0x000062\r
+SSR04 .EQU 0x000062\r
+_rdr04 .EQU 0x000063\r
+RDR04 .EQU 0x000063\r
+_tdr04 .EQU 0x000063\r
+TDR04 .EQU 0x000063\r
+_escr04 .EQU 0x000064\r
+ESCR04 .EQU 0x000064\r
+_eccr04 .EQU 0x000065\r
+ECCR04 .EQU 0x000065\r
+_fsr04 .EQU 0x000066\r
+FSR04 .EQU 0x000066\r
+_fcr04 .EQU 0x000067\r
+FCR04 .EQU 0x000067\r
+_bgr00 .EQU 0x000080\r
+BGR00 .EQU 0x000080 /* Bauderate Generator USART (LIN) 0-7 */\r
+_bgr100 .EQU 0x000080\r
+BGR100 .EQU 0x000080\r
+_bgr000 .EQU 0x000081\r
+BGR000 .EQU 0x000081\r
+_bgr01 .EQU 0x000082\r
+BGR01 .EQU 0x000082\r
+_bgr101 .EQU 0x000082\r
+BGR101 .EQU 0x000082\r
+_bgr001 .EQU 0x000083\r
+BGR001 .EQU 0x000083\r
+_bgr02 .EQU 0x000084\r
+BGR02 .EQU 0x000084\r
+_bgr102 .EQU 0x000084\r
+BGR102 .EQU 0x000084\r
+_bgr002 .EQU 0x000085\r
+BGR002 .EQU 0x000085\r
+_bgr03 .EQU 0x000086\r
+BGR03 .EQU 0x000086\r
+_bgr103 .EQU 0x000086\r
+BGR103 .EQU 0x000086\r
+_bgr003 .EQU 0x000087\r
+BGR003 .EQU 0x000087\r
+_bgr04 .EQU 0x000088\r
+BGR04 .EQU 0x000088\r
+_bgr104 .EQU 0x000088\r
+BGR104 .EQU 0x000088\r
+_bgr004 .EQU 0x000089\r
+BGR004 .EQU 0x000089\r
+_ibcr0 .EQU 0x0000D0\r
+IBCR0 .EQU 0x0000D0 /* I2C 0 */\r
+_ibsr0 .EQU 0x0000D1\r
+IBSR0 .EQU 0x0000D1\r
+_itba0 .EQU 0x0000D2\r
+ITBA0 .EQU 0x0000D2\r
+_itbah0 .EQU 0x0000D2\r
+ITBAH0 .EQU 0x0000D2\r
+_itbal0 .EQU 0x0000D3\r
+ITBAL0 .EQU 0x0000D3\r
+_itmk0 .EQU 0x0000D4\r
+ITMK0 .EQU 0x0000D4\r
+_itmkh0 .EQU 0x0000D4\r
+ITMKH0 .EQU 0x0000D4\r
+_itmkl0 .EQU 0x0000D5\r
+ITMKL0 .EQU 0x0000D5\r
+_ismk0 .EQU 0x0000D6\r
+ISMK0 .EQU 0x0000D6\r
+_isba0 .EQU 0x0000D7\r
+ISBA0 .EQU 0x0000D7\r
+_idar0 .EQU 0x0000D9\r
+IDAR0 .EQU 0x0000D9\r
+_iccr0 .EQU 0x0000DA\r
+ICCR0 .EQU 0x0000DA\r
+_gcn10 .EQU 0x000100\r
+GCN10 .EQU 0x000100 /* PPG Control 0-3 */\r
+_gcn20 .EQU 0x000103\r
+GCN20 .EQU 0x000103\r
+_gcn11 .EQU 0x000104\r
+GCN11 .EQU 0x000104 /* PPG Control 4-7 */\r
+_gcn21 .EQU 0x000107\r
+GCN21 .EQU 0x000107\r
+_gcn12 .EQU 0x000108\r
+GCN12 .EQU 0x000108 /* PPG Control 8-11 */\r
+_gcn22 .EQU 0x00010B\r
+GCN22 .EQU 0x00010B\r
+_ptmr00 .EQU 0x000110\r
+PTMR00 .EQU 0x000110 /* PPG 0 */\r
+_pcsr00 .EQU 0x000112\r
+PCSR00 .EQU 0x000112\r
+_pdut00 .EQU 0x000114\r
+PDUT00 .EQU 0x000114\r
+_pcn00 .EQU 0x000116\r
+PCN00 .EQU 0x000116\r
+_pcnh00 .EQU 0x000116\r
+PCNH00 .EQU 0x000116\r
+_pcnl00 .EQU 0x000117\r
+PCNL00 .EQU 0x000117\r
+_ptmr01 .EQU 0x000118\r
+PTMR01 .EQU 0x000118 /* PPG 1 */\r
+_pcsr01 .EQU 0x00011A\r
+PCSR01 .EQU 0x00011A\r
+_pdut01 .EQU 0x00011C\r
+PDUT01 .EQU 0x00011C\r
+_pcn01 .EQU 0x00011E\r
+PCN01 .EQU 0x00011E\r
+_pcnh01 .EQU 0x00011E\r
+PCNH01 .EQU 0x00011E\r
+_pcnl01 .EQU 0x00011F\r
+PCNL01 .EQU 0x00011F\r
+_ptmr02 .EQU 0x000120\r
+PTMR02 .EQU 0x000120 /* PPG 2 */\r
+_pcsr02 .EQU 0x000122\r
+PCSR02 .EQU 0x000122\r
+_pdut02 .EQU 0x000124\r
+PDUT02 .EQU 0x000124\r
+_pcn02 .EQU 0x000126\r
+PCN02 .EQU 0x000126\r
+_pcnh02 .EQU 0x000126\r
+PCNH02 .EQU 0x000126\r
+_pcnl02 .EQU 0x000127\r
+PCNL02 .EQU 0x000127\r
+_ptmr03 .EQU 0x000128\r
+PTMR03 .EQU 0x000128 /* PPG 3 */\r
+_pcsr03 .EQU 0x00012A\r
+PCSR03 .EQU 0x00012A\r
+_pdut03 .EQU 0x00012C\r
+PDUT03 .EQU 0x00012C\r
+_pcn03 .EQU 0x00012E\r
+PCN03 .EQU 0x00012E\r
+_pcnh03 .EQU 0x00012E\r
+PCNH03 .EQU 0x00012E\r
+_pcnl03 .EQU 0x00012F\r
+PCNL03 .EQU 0x00012F\r
+_ptmr04 .EQU 0x000130\r
+PTMR04 .EQU 0x000130 /* PPG 4 */\r
+_pcsr04 .EQU 0x000132\r
+PCSR04 .EQU 0x000132\r
+_pdut04 .EQU 0x000134\r
+PDUT04 .EQU 0x000134\r
+_pcn04 .EQU 0x000136\r
+PCN04 .EQU 0x000136\r
+_pcnh04 .EQU 0x000136\r
+PCNH04 .EQU 0x000136\r
+_pcnl04 .EQU 0x000137\r
+PCNL04 .EQU 0x000137\r
+_ptmr05 .EQU 0x000138\r
+PTMR05 .EQU 0x000138 /* PPG 5 */\r
+_pcsr05 .EQU 0x00013A\r
+PCSR05 .EQU 0x00013A\r
+_pdut05 .EQU 0x00013C\r
+PDUT05 .EQU 0x00013C\r
+_pcn05 .EQU 0x00013E\r
+PCN05 .EQU 0x00013E\r
+_pcnh05 .EQU 0x00013E\r
+PCNH05 .EQU 0x00013E\r
+_pcnl05 .EQU 0x00013F\r
+PCNL05 .EQU 0x00013F\r
+_ptmr06 .EQU 0x000140\r
+PTMR06 .EQU 0x000140 /* PPG 6 */\r
+_pcsr06 .EQU 0x000142\r
+PCSR06 .EQU 0x000142\r
+_pdut06 .EQU 0x000144\r
+PDUT06 .EQU 0x000144\r
+_pcn06 .EQU 0x000146\r
+PCN06 .EQU 0x000146\r
+_pcnh06 .EQU 0x000146\r
+PCNH06 .EQU 0x000146\r
+_pcnl06 .EQU 0x000147\r
+PCNL06 .EQU 0x000147\r
+_ptmr07 .EQU 0x000148\r
+PTMR07 .EQU 0x000148 /* PPG 7 */\r
+_pcsr07 .EQU 0x00014A\r
+PCSR07 .EQU 0x00014A\r
+_pdut07 .EQU 0x00014C\r
+PDUT07 .EQU 0x00014C\r
+_pcn07 .EQU 0x00014E\r
+PCN07 .EQU 0x00014E\r
+_pcnh07 .EQU 0x00014E\r
+PCNH07 .EQU 0x00014E\r
+_pcnl07 .EQU 0x00014F\r
+PCNL07 .EQU 0x00014F\r
+_ptmr08 .EQU 0x000150\r
+PTMR08 .EQU 0x000150 /* PPG 8 */\r
+_pcsr08 .EQU 0x000152\r
+PCSR08 .EQU 0x000152\r
+_pdut08 .EQU 0x000154\r
+PDUT08 .EQU 0x000154\r
+_pcn08 .EQU 0x000156\r
+PCN08 .EQU 0x000156\r
+_pcnh08 .EQU 0x000156\r
+PCNH08 .EQU 0x000156\r
+_pcnl08 .EQU 0x000157\r
+PCNL08 .EQU 0x000157\r
+_ptmr09 .EQU 0x000158\r
+PTMR09 .EQU 0x000158 /* PPG 9 */\r
+_pcsr09 .EQU 0x00015A\r
+PCSR09 .EQU 0x00015A\r
+_pdut09 .EQU 0x00015C\r
+PDUT09 .EQU 0x00015C\r
+_pcn09 .EQU 0x00015E\r
+PCN09 .EQU 0x00015E\r
+_pcnh09 .EQU 0x00015E\r
+PCNH09 .EQU 0x00015E\r
+_pcnl09 .EQU 0x00015F\r
+PCNL09 .EQU 0x00015F\r
+_ptmr10 .EQU 0x000160\r
+PTMR10 .EQU 0x000160 /* PPG 10 */\r
+_pcsr10 .EQU 0x000162\r
+PCSR10 .EQU 0x000162\r
+_pdut10 .EQU 0x000164\r
+PDUT10 .EQU 0x000164\r
+_pcn10 .EQU 0x000166\r
+PCN10 .EQU 0x000166\r
+_pcnh10 .EQU 0x000166\r
+PCNH10 .EQU 0x000166\r
+_pcnl10 .EQU 0x000167\r
+PCNL10 .EQU 0x000167\r
+_ptmr11 .EQU 0x000168\r
+PTMR11 .EQU 0x000168 /* PPG 11 */\r
+_pcsr11 .EQU 0x00016A\r
+PCSR11 .EQU 0x00016A\r
+_pdut11 .EQU 0x00016C\r
+PDUT11 .EQU 0x00016C\r
+_pcn11 .EQU 0x00016E\r
+PCN11 .EQU 0x00016E\r
+_pcnh11 .EQU 0x00016E\r
+PCNH11 .EQU 0x00016E\r
+_pcnl11 .EQU 0x00016F\r
+PCNL11 .EQU 0x00016F\r
+_ics01 .EQU 0x000181\r
+ICS01 .EQU 0x000181 /* Input Capture 0-3 */\r
+_ics23 .EQU 0x000183\r
+ICS23 .EQU 0x000183\r
+_ipcp0 .EQU 0x000184\r
+IPCP0 .EQU 0x000184\r
+_ipcp1 .EQU 0x000186\r
+IPCP1 .EQU 0x000186\r
+_ipcp2 .EQU 0x000188\r
+IPCP2 .EQU 0x000188\r
+_ipcp3 .EQU 0x00018A\r
+IPCP3 .EQU 0x00018A\r
+_ocs01 .EQU 0x00018C\r
+OCS01 .EQU 0x00018C /* Output Compare 0-3 */\r
+_ocs23 .EQU 0x00018E\r
+OCS23 .EQU 0x00018E\r
+_occp0 .EQU 0x000190\r
+OCCP0 .EQU 0x000190\r
+_occp1 .EQU 0x000192\r
+OCCP1 .EQU 0x000192\r
+_occp2 .EQU 0x000194\r
+OCCP2 .EQU 0x000194\r
+_occp3 .EQU 0x000196\r
+OCCP3 .EQU 0x000196\r
+_aderh .EQU 0x0001A0\r
+ADERH .EQU 0x0001A0 /* ADC */\r
+_aderl .EQU 0x0001A2\r
+ADERL .EQU 0x0001A2\r
+_ader .EQU 0x0001A0\r
+ADER .EQU 0x0001A0\r
+_adcs1 .EQU 0x0001A4\r
+ADCS1 .EQU 0x0001A4\r
+_adcs0 .EQU 0x0001A5\r
+ADCS0 .EQU 0x0001A5\r
+_adcs .EQU 0x0001A4\r
+ADCS .EQU 0x0001A4\r
+_adcr1 .EQU 0x0001A6\r
+ADCR1 .EQU 0x0001A6\r
+_adcr0 .EQU 0x0001A7\r
+ADCR0 .EQU 0x0001A7\r
+_adcr .EQU 0x0001A6\r
+ADCR .EQU 0x0001A6\r
+_adct1 .EQU 0x0001A8\r
+ADCT1 .EQU 0x0001A8\r
+_adct0 .EQU 0x0001A9\r
+ADCT0 .EQU 0x0001A9\r
+_adct .EQU 0x0001A8\r
+ADCT .EQU 0x0001A8\r
+_adsch .EQU 0x0001AA\r
+ADSCH .EQU 0x0001AA\r
+_adech .EQU 0x0001AB\r
+ADECH .EQU 0x0001AB\r
+_tmrlr0 .EQU 0x0001B0\r
+TMRLR0 .EQU 0x0001B0 /* Reload Timer 0 */\r
+_tmr0 .EQU 0x0001B2\r
+TMR0 .EQU 0x0001B2\r
+_tmcsr0 .EQU 0x0001B6\r
+TMCSR0 .EQU 0x0001B6\r
+_tmcsrh0 .EQU 0x0001B6\r
+TMCSRH0 .EQU 0x0001B6\r
+_tmcsrl0 .EQU 0x0001B7\r
+TMCSRL0 .EQU 0x0001B7\r
+_tmrlr1 .EQU 0x0001B8\r
+TMRLR1 .EQU 0x0001B8 /* Reload Timer 1 */\r
+_tmr1 .EQU 0x0001BA\r
+TMR1 .EQU 0x0001BA\r
+_tmcsr1 .EQU 0x0001BE\r
+TMCSR1 .EQU 0x0001BE\r
+_tmcsrh1 .EQU 0x0001BE\r
+TMCSRH1 .EQU 0x0001BE\r
+_tmcsrl1 .EQU 0x0001BF\r
+TMCSRL1 .EQU 0x0001BF\r
+_tmrlr2 .EQU 0x0001C0\r
+TMRLR2 .EQU 0x0001C0 /* Reload Timer 2 */\r
+_tmr2 .EQU 0x0001C2\r
+TMR2 .EQU 0x0001C2\r
+_tmcsr2 .EQU 0x0001C6\r
+TMCSR2 .EQU 0x0001C6\r
+_tmcsrh2 .EQU 0x0001C6\r
+TMCSRH2 .EQU 0x0001C6\r
+_tmcsrl2 .EQU 0x0001C7\r
+TMCSRL2 .EQU 0x0001C7\r
+_tmrlr3 .EQU 0x0001C8\r
+TMRLR3 .EQU 0x0001C8 /* Reload Timer 3 */\r
+_tmr3 .EQU 0x0001CA\r
+TMR3 .EQU 0x0001CA\r
+_tmcsr3 .EQU 0x0001CE\r
+TMCSR3 .EQU 0x0001CE\r
+_tmcsrh3 .EQU 0x0001CE\r
+TMCSRH3 .EQU 0x0001CE\r
+_tmcsrl3 .EQU 0x0001CF\r
+TMCSRL3 .EQU 0x0001CF\r
+_tmrlr4 .EQU 0x0001D0\r
+TMRLR4 .EQU 0x0001D0 /* Reload Timer 4 */\r
+_tmr4 .EQU 0x0001D2\r
+TMR4 .EQU 0x0001D2\r
+_tmcsr4 .EQU 0x0001D6\r
+TMCSR4 .EQU 0x0001D6\r
+_tmcsrh4 .EQU 0x0001D6\r
+TMCSRH4 .EQU 0x0001D6\r
+_tmcsrl4 .EQU 0x0001D7\r
+TMCSRL4 .EQU 0x0001D7\r
+_tmrlr5 .EQU 0x0001D8\r
+TMRLR5 .EQU 0x0001D8 /* Reload Timer 5 */\r
+_tmr5 .EQU 0x0001DA\r
+TMR5 .EQU 0x0001DA\r
+_tmcsr5 .EQU 0x0001DE\r
+TMCSR5 .EQU 0x0001DE\r
+_tmcsrh5 .EQU 0x0001DE\r
+TMCSRH5 .EQU 0x0001DE\r
+_tmcsrl5 .EQU 0x0001DF\r
+TMCSRL5 .EQU 0x0001DF\r
+_tmrlr6 .EQU 0x0001E0\r
+TMRLR6 .EQU 0x0001E0 /* Reload Timer 6 */\r
+_tmr6 .EQU 0x0001E2\r
+TMR6 .EQU 0x0001E2\r
+_tmcsr6 .EQU 0x0001E6\r
+TMCSR6 .EQU 0x0001E6\r
+_tmcsrh6 .EQU 0x0001E6\r
+TMCSRH6 .EQU 0x0001E6\r
+_tmcsrl6 .EQU 0x0001E7\r
+TMCSRL6 .EQU 0x0001E7\r
+_tmrlr7 .EQU 0x0001E8\r
+TMRLR7 .EQU 0x0001E8 /* Reload Timer 7 */\r
+_tmr7 .EQU 0x0001EA\r
+TMR7 .EQU 0x0001EA\r
+_tmcsr7 .EQU 0x0001EE\r
+TMCSR7 .EQU 0x0001EE\r
+_tmcsrh7 .EQU 0x0001EE\r
+TMCSRH7 .EQU 0x0001EE\r
+_tmcsrl7 .EQU 0x0001EF\r
+TMCSRL7 .EQU 0x0001EF\r
+_tcdt0 .EQU 0x0001F0\r
+TCDT0 .EQU 0x0001F0 /* Free Running Timer0 */\r
+_tccs0 .EQU 0x0001F3\r
+TCCS0 .EQU 0x0001F3\r
+_tcdt1 .EQU 0x0001F4\r
+TCDT1 .EQU 0x0001F4 /* Free Running Timer1 */\r
+_tccs1 .EQU 0x0001F7\r
+TCCS1 .EQU 0x0001F7\r
+_tcdt2 .EQU 0x0001F8\r
+TCDT2 .EQU 0x0001F8 /* Free Running Timer2 */\r
+_tccs2 .EQU 0x0001FB\r
+TCCS2 .EQU 0x0001FB\r
+_tcdt3 .EQU 0x0001FC\r
+TCDT3 .EQU 0x0001FC /* Free Running Timer3 */\r
+_tccs3 .EQU 0x0001FF\r
+TCCS3 .EQU 0x0001FF\r
+_dmaca0 .EQU 0x000200\r
+DMACA0 .EQU 0x000200 /* DMAC */\r
+_dmacb0 .EQU 0x000204\r
+DMACB0 .EQU 0x000204\r
+_dmaca1 .EQU 0x000208\r
+DMACA1 .EQU 0x000208\r
+_dmacb1 .EQU 0x00020C\r
+DMACB1 .EQU 0x00020C\r
+_dmaca2 .EQU 0x000210\r
+DMACA2 .EQU 0x000210\r
+_dmacb2 .EQU 0x000214\r
+DMACB2 .EQU 0x000214\r
+_dmaca3 .EQU 0x000218\r
+DMACA3 .EQU 0x000218\r
+_dmacb3 .EQU 0x00021C\r
+DMACB3 .EQU 0x00021C\r
+_dmaca4 .EQU 0x000220\r
+DMACA4 .EQU 0x000220\r
+_dmacb4 .EQU 0x000224\r
+DMACB4 .EQU 0x000224\r
+_dmacr .EQU 0x000240\r
+DMACR .EQU 0x000240\r
+_ics45 .EQU 0x0002D1\r
+ICS45 .EQU 0x0002D1 /* Input Capture 4-7 */\r
+_ics67 .EQU 0x0002D3\r
+ICS67 .EQU 0x0002D3\r
+_ipcp4 .EQU 0x0002D4\r
+IPCP4 .EQU 0x0002D4\r
+_ipcp5 .EQU 0x0002D6\r
+IPCP5 .EQU 0x0002D6\r
+_ipcp6 .EQU 0x0002D8\r
+IPCP6 .EQU 0x0002D8\r
+_ipcp7 .EQU 0x0002DA\r
+IPCP7 .EQU 0x0002DA\r
+_ocs45 .EQU 0x0002DC\r
+OCS45 .EQU 0x0002DC /* Output Compare 4-7 */\r
+_ocs67 .EQU 0x0002DE\r
+OCS67 .EQU 0x0002DE\r
+_occp4 .EQU 0x0002E0\r
+OCCP4 .EQU 0x0002E0\r
+_occp5 .EQU 0x0002E2\r
+OCCP5 .EQU 0x0002E2\r
+_occp6 .EQU 0x0002E4\r
+OCCP6 .EQU 0x0002E4\r
+_occp7 .EQU 0x0002E6\r
+OCCP7 .EQU 0x0002E6\r
+_tcdt4 .EQU 0x0002F0\r
+TCDT4 .EQU 0x0002F0 /* Free Running Timer4 */\r
+_tccs4 .EQU 0x0002F3\r
+TCCS4 .EQU 0x0002F3\r
+_tcdt5 .EQU 0x0002F4\r
+TCDT5 .EQU 0x0002F4 /* Free Running Timer5 */\r
+_tccs5 .EQU 0x0002F7\r
+TCCS5 .EQU 0x0002F7\r
+_tcdt6 .EQU 0x0002F8\r
+TCDT6 .EQU 0x0002F8 /* Free Running Timer6 */\r
+_tccs6 .EQU 0x0002FB\r
+TCCS6 .EQU 0x0002FB\r
+_tcdt7 .EQU 0x0002FC\r
+TCDT7 .EQU 0x0002FC /* Free Running Timer7 */\r
+_tccs7 .EQU 0x0002FF\r
+TCCS7 .EQU 0x0002FF\r
+_roms .EQU 0x000390\r
+ROMS .EQU 0x000390 /* ROM Select Register */\r
+_bsd0 .EQU 0x0003F0\r
+BSD0 .EQU 0x0003F0 /* Bit Search Module */\r
+_bsd1 .EQU 0x0003F4\r
+BSD1 .EQU 0x0003F4\r
+_bsdc .EQU 0x0003F8\r
+BSDC .EQU 0x0003F8\r
+_bsrr .EQU 0x0003FC\r
+BSRR .EQU 0x0003FC\r
+_icr00 .EQU 0x000440\r
+ICR00 .EQU 0x000440 /* Interrupt Control Unit */\r
+_icr01 .EQU 0x000441\r
+ICR01 .EQU 0x000441\r
+_icr02 .EQU 0x000442\r
+ICR02 .EQU 0x000442\r
+_icr03 .EQU 0x000443\r
+ICR03 .EQU 0x000443\r
+_icr04 .EQU 0x000444\r
+ICR04 .EQU 0x000444\r
+_icr05 .EQU 0x000445\r
+ICR05 .EQU 0x000445\r
+_icr06 .EQU 0x000446\r
+ICR06 .EQU 0x000446\r
+_icr07 .EQU 0x000447\r
+ICR07 .EQU 0x000447\r
+_icr08 .EQU 0x000448\r
+ICR08 .EQU 0x000448\r
+_icr09 .EQU 0x000449\r
+ICR09 .EQU 0x000449\r
+_icr10 .EQU 0x00044A\r
+ICR10 .EQU 0x00044A\r
+_icr11 .EQU 0x00044B\r
+ICR11 .EQU 0x00044B\r
+_icr12 .EQU 0x00044C\r
+ICR12 .EQU 0x00044C\r
+_icr13 .EQU 0x00044D\r
+ICR13 .EQU 0x00044D\r
+_icr14 .EQU 0x00044E\r
+ICR14 .EQU 0x00044E\r
+_icr15 .EQU 0x00044F\r
+ICR15 .EQU 0x00044F\r
+_icr16 .EQU 0x000450\r
+ICR16 .EQU 0x000450\r
+_icr17 .EQU 0x000451\r
+ICR17 .EQU 0x000451\r
+_icr18 .EQU 0x000452\r
+ICR18 .EQU 0x000452\r
+_icr19 .EQU 0x000453\r
+ICR19 .EQU 0x000453\r
+_icr20 .EQU 0x000454\r
+ICR20 .EQU 0x000454\r
+_icr21 .EQU 0x000455\r
+ICR21 .EQU 0x000455\r
+_icr22 .EQU 0x000456\r
+ICR22 .EQU 0x000456\r
+_icr23 .EQU 0x000457\r
+ICR23 .EQU 0x000457\r
+_icr24 .EQU 0x000458\r
+ICR24 .EQU 0x000458\r
+_icr25 .EQU 0x000459\r
+ICR25 .EQU 0x000459\r
+_icr26 .EQU 0x00045A\r
+ICR26 .EQU 0x00045A\r
+_icr27 .EQU 0x00045B\r
+ICR27 .EQU 0x00045B\r
+_icr28 .EQU 0x00045C\r
+ICR28 .EQU 0x00045C\r
+_icr29 .EQU 0x00045D\r
+ICR29 .EQU 0x00045D\r
+_icr30 .EQU 0x00045E\r
+ICR30 .EQU 0x00045E\r
+_icr31 .EQU 0x00045F\r
+ICR31 .EQU 0x00045F\r
+_icr32 .EQU 0x000460\r
+ICR32 .EQU 0x000460\r
+_icr33 .EQU 0x000461\r
+ICR33 .EQU 0x000461\r
+_icr34 .EQU 0x000462\r
+ICR34 .EQU 0x000462\r
+_icr35 .EQU 0x000463\r
+ICR35 .EQU 0x000463\r
+_icr36 .EQU 0x000464\r
+ICR36 .EQU 0x000464\r
+_icr37 .EQU 0x000465\r
+ICR37 .EQU 0x000465\r
+_icr38 .EQU 0x000466\r
+ICR38 .EQU 0x000466\r
+_icr39 .EQU 0x000467\r
+ICR39 .EQU 0x000467\r
+_icr40 .EQU 0x000468\r
+ICR40 .EQU 0x000468\r
+_icr41 .EQU 0x000469\r
+ICR41 .EQU 0x000469\r
+_icr42 .EQU 0x00046A\r
+ICR42 .EQU 0x00046A\r
+_icr43 .EQU 0x00046B\r
+ICR43 .EQU 0x00046B\r
+_icr44 .EQU 0x00046C\r
+ICR44 .EQU 0x00046C\r
+_icr45 .EQU 0x00046D\r
+ICR45 .EQU 0x00046D\r
+_icr46 .EQU 0x00046E\r
+ICR46 .EQU 0x00046E\r
+_icr47 .EQU 0x00046F\r
+ICR47 .EQU 0x00046F\r
+_icr48 .EQU 0x000470\r
+ICR48 .EQU 0x000470\r
+_icr49 .EQU 0x000471\r
+ICR49 .EQU 0x000471\r
+_icr50 .EQU 0x000472\r
+ICR50 .EQU 0x000472\r
+_icr51 .EQU 0x000473\r
+ICR51 .EQU 0x000473\r
+_icr52 .EQU 0x000474\r
+ICR52 .EQU 0x000474\r
+_icr53 .EQU 0x000475\r
+ICR53 .EQU 0x000475\r
+_icr54 .EQU 0x000476\r
+ICR54 .EQU 0x000476\r
+_icr55 .EQU 0x000477\r
+ICR55 .EQU 0x000477\r
+_icr56 .EQU 0x000478\r
+ICR56 .EQU 0x000478\r
+_icr57 .EQU 0x000479\r
+ICR57 .EQU 0x000479\r
+_icr58 .EQU 0x00047A\r
+ICR58 .EQU 0x00047A\r
+_icr59 .EQU 0x00047B\r
+ICR59 .EQU 0x00047B\r
+_icr60 .EQU 0x00047C\r
+ICR60 .EQU 0x00047C\r
+_icr61 .EQU 0x00047D\r
+ICR61 .EQU 0x00047D\r
+_icr62 .EQU 0x00047E\r
+ICR62 .EQU 0x00047E\r
+_icr63 .EQU 0x00047F\r
+ICR63 .EQU 0x00047F\r
+_rsrr .EQU 0x000480\r
+RSRR .EQU 0x000480 /* Clock Control Unit */\r
+_stcr .EQU 0x000481\r
+STCR .EQU 0x000481\r
+_tbcr .EQU 0x000482\r
+TBCR .EQU 0x000482\r
+_ctbr .EQU 0x000483\r
+CTBR .EQU 0x000483\r
+_clkr .EQU 0x000484\r
+CLKR .EQU 0x000484\r
+_wpr .EQU 0x000485\r
+WPR .EQU 0x000485\r
+_divr0 .EQU 0x000486\r
+DIVR0 .EQU 0x000486\r
+_divr1 .EQU 0x000487\r
+DIVR1 .EQU 0x000487\r
+_plldivm .EQU 0x00048C\r
+PLLDIVM .EQU 0x00048C /* PLL - Clock Gear Unit: */\r
+_plldivn .EQU 0x00048D\r
+PLLDIVN .EQU 0x00048D\r
+_plldivg .EQU 0x00048E\r
+PLLDIVG .EQU 0x00048E\r
+_pllmulg .EQU 0x00048F\r
+PLLMULG .EQU 0x00048F\r
+_pllctrl .EQU 0x000490\r
+PLLCTRL .EQU 0x000490\r
+_oscc1 .EQU 0x000494\r
+OSCC1 .EQU 0x000494 /* Main/Sub Oscillator Control */\r
+_oscs1 .EQU 0x000495\r
+OSCS1 .EQU 0x000495\r
+_oscc2 .EQU 0x000496\r
+OSCC2 .EQU 0x000496\r
+_oscs2 .EQU 0x000497\r
+OSCS2 .EQU 0x000497\r
+_porten .EQU 0x000498\r
+PORTEN .EQU 0x000498 /* Port Input Enable Control */\r
+_wtcer .EQU 0x0004A1\r
+WTCER .EQU 0x0004A1 /* Real Time Clock (Watch Timer) */\r
+_wtcr .EQU 0x0004A2\r
+WTCR .EQU 0x0004A2\r
+_wtbr .EQU 0x0004A4\r
+WTBR .EQU 0x0004A4\r
+_wthr .EQU 0x0004A8\r
+WTHR .EQU 0x0004A8\r
+_wtmr .EQU 0x0004A9\r
+WTMR .EQU 0x0004A9\r
+_wtsr .EQU 0x0004AA\r
+WTSR .EQU 0x0004AA\r
+_csvtr .EQU 0x0004AC\r
+CSVTR .EQU 0x0004AC /* Clock-Supervisor / Selecor / Monitor */\r
+_csvcr .EQU 0x0004AD\r
+CSVCR .EQU 0x0004AD\r
+_cscfg .EQU 0x0004AE\r
+CSCFG .EQU 0x0004AE\r
+_cmcfg .EQU 0x0004AF\r
+CMCFG .EQU 0x0004AF\r
+_cucr .EQU 0x0004B0\r
+CUCR .EQU 0x0004B0 /* Calibration Unit of Sub Oszillation */\r
+_cutd .EQU 0x0004B2\r
+CUTD .EQU 0x0004B2\r
+_cutr1 .EQU 0x0004B4\r
+CUTR1 .EQU 0x0004B4\r
+_cutr2 .EQU 0x0004B6\r
+CUTR2 .EQU 0x0004B6\r
+_cmpr .EQU 0x0004B8\r
+CMPR .EQU 0x0004B8 /* Clock Modulator */\r
+_cmcr .EQU 0x0004BB\r
+CMCR .EQU 0x0004BB\r
+_cmt1 .EQU 0x0004BC\r
+CMT1 .EQU 0x0004BC\r
+_cmt2 .EQU 0x0004BE\r
+CMT2 .EQU 0x0004BE\r
+_canpre .EQU 0x0004C0\r
+CANPRE .EQU 0x0004C0 /* CAN clock control */\r
+_canckd .EQU 0x0004C1\r
+CANCKD .EQU 0x0004C1\r
+_lvsel .EQU 0x0004C4\r
+LVSEL .EQU 0x0004C4 /* LV Detection / Hardware-Watchdog */\r
+_lvdet .EQU 0x0004C5\r
+LVDET .EQU 0x0004C5\r
+_hwwde .EQU 0x0004C6\r
+HWWDE .EQU 0x0004C6\r
+_hwwd .EQU 0x0004C7\r
+HWWD .EQU 0x0004C7\r
+_oscrh .EQU 0x0004C8\r
+OSCRH .EQU 0x0004C8 /* Main-/Sub-Oscillatio Stabilization Timer */\r
+_oscrl .EQU 0x0004C9\r
+OSCRL .EQU 0x0004C9\r
+_wpcrh .EQU 0x0004CA\r
+WPCRH .EQU 0x0004CA\r
+_wpcrl .EQU 0x0004CB\r
+WPCRL .EQU 0x0004CB\r
+_osccr .EQU 0x0004CC\r
+OSCCR .EQU 0x0004CC /* Main-/Sub-Oscillatio Standby Control */\r
+_regsel .EQU 0x0004CE\r
+REGSEL .EQU 0x0004CE\r
+_regctr .EQU 0x0004CF\r
+REGCTR .EQU 0x0004CF\r
+_modr .EQU 0x0007FD\r
+MODR .EQU 0x0007FD /* Mode Register */\r
+_pdrd14 .EQU 0x000D0E\r
+PDRD14 .EQU 0x000D0E /* R-bus Port Data Direct Read Register */\r
+_pdrd15 .EQU 0x000D0F\r
+PDRD15 .EQU 0x000D0F\r
+_pdrd16 .EQU 0x000D10\r
+PDRD16 .EQU 0x000D10\r
+_pdrd17 .EQU 0x000D11\r
+PDRD17 .EQU 0x000D11\r
+_pdrd18 .EQU 0x000D12\r
+PDRD18 .EQU 0x000D12\r
+_pdrd19 .EQU 0x000D13\r
+PDRD19 .EQU 0x000D13\r
+_pdrd20 .EQU 0x000D14\r
+PDRD20 .EQU 0x000D14\r
+_pdrd21 .EQU 0x000D15\r
+PDRD21 .EQU 0x000D15\r
+_pdrd22 .EQU 0x000D16\r
+PDRD22 .EQU 0x000D16\r
+_pdrd24 .EQU 0x000D18\r
+PDRD24 .EQU 0x000D18\r
+_pdrd26 .EQU 0x000D1A\r
+PDRD26 .EQU 0x000D1A\r
+_pdrd27 .EQU 0x000D1B\r
+PDRD27 .EQU 0x000D1B\r
+_pdrd28 .EQU 0x000D1C\r
+PDRD28 .EQU 0x000D1C\r
+_pdrd29 .EQU 0x000D1D\r
+PDRD29 .EQU 0x000D1D\r
+_ddr14 .EQU 0x000D4E\r
+DDR14 .EQU 0x000D4E /* R-bus Port Direction Register */\r
+_ddr15 .EQU 0x000D4F\r
+DDR15 .EQU 0x000D4F\r
+_ddr16 .EQU 0x000D50\r
+DDR16 .EQU 0x000D50\r
+_ddr17 .EQU 0x000D51\r
+DDR17 .EQU 0x000D51\r
+_ddr18 .EQU 0x000D52\r
+DDR18 .EQU 0x000D52\r
+_ddr19 .EQU 0x000D53\r
+DDR19 .EQU 0x000D53\r
+_ddr20 .EQU 0x000D54\r
+DDR20 .EQU 0x000D54\r
+_ddr21 .EQU 0x000D55\r
+DDR21 .EQU 0x000D55\r
+_ddr22 .EQU 0x000D56\r
+DDR22 .EQU 0x000D56\r
+_ddr24 .EQU 0x000D58\r
+DDR24 .EQU 0x000D58\r
+_ddr26 .EQU 0x000D5A\r
+DDR26 .EQU 0x000D5A\r
+_ddr27 .EQU 0x000D5B\r
+DDR27 .EQU 0x000D5B\r
+_ddr28 .EQU 0x000D5C\r
+DDR28 .EQU 0x000D5C\r
+_ddr29 .EQU 0x000D5D\r
+DDR29 .EQU 0x000D5D\r
+_pfr14 .EQU 0x000D8E\r
+PFR14 .EQU 0x000D8E /* R-bus Port Function Register */\r
+_pfr15 .EQU 0x000D8F\r
+PFR15 .EQU 0x000D8F\r
+_pfr16 .EQU 0x000D90\r
+PFR16 .EQU 0x000D90\r
+_pfr17 .EQU 0x000D91\r
+PFR17 .EQU 0x000D91\r
+_pfr18 .EQU 0x000D92\r
+PFR18 .EQU 0x000D92\r
+_pfr19 .EQU 0x000D93\r
+PFR19 .EQU 0x000D93\r
+_pfr20 .EQU 0x000D94\r
+PFR20 .EQU 0x000D94\r
+_pfr21 .EQU 0x000D95\r
+PFR21 .EQU 0x000D95\r
+_pfr22 .EQU 0x000D96\r
+PFR22 .EQU 0x000D96\r
+_pfr24 .EQU 0x000D98\r
+PFR24 .EQU 0x000D98\r
+_pfr26 .EQU 0x000D9A\r
+PFR26 .EQU 0x000D9A\r
+_pfr27 .EQU 0x000D9B\r
+PFR27 .EQU 0x000D9B\r
+_pfr28 .EQU 0x000D9C\r
+PFR28 .EQU 0x000D9C\r
+_pfr29 .EQU 0x000D9D\r
+PFR29 .EQU 0x000D9D\r
+_epfr14 .EQU 0x000DCE\r
+EPFR14 .EQU 0x000DCE /* R-bus Port Extra Function Register */\r
+_epfr15 .EQU 0x000DCF\r
+EPFR15 .EQU 0x000DCF\r
+_epfr16 .EQU 0x000DD0\r
+EPFR16 .EQU 0x000DD0\r
+_epfr17 .EQU 0x000DD1\r
+EPFR17 .EQU 0x000DD1\r
+_epfr18 .EQU 0x000DD2\r
+EPFR18 .EQU 0x000DD2\r
+_epfr19 .EQU 0x000DD3\r
+EPFR19 .EQU 0x000DD3\r
+_epfr20 .EQU 0x000DD4\r
+EPFR20 .EQU 0x000DD4\r
+_epfr21 .EQU 0x000DD5\r
+EPFR21 .EQU 0x000DD5\r
+_epfr22 .EQU 0x000DD6\r
+EPFR22 .EQU 0x000DD6\r
+_epfr24 .EQU 0x000DD8\r
+EPFR24 .EQU 0x000DD8\r
+_epfr26 .EQU 0x000DDA\r
+EPFR26 .EQU 0x000DDA\r
+_epfr27 .EQU 0x000DDB\r
+EPFR27 .EQU 0x000DDB\r
+_epfr29 .EQU 0x000DDD\r
+EPFR29 .EQU 0x000DDD\r
+_podr14 .EQU 0x000E0E\r
+PODR14 .EQU 0x000E0E /* R-bus Port Output Drive Select Register */\r
+_podr15 .EQU 0x000E0F\r
+PODR15 .EQU 0x000E0F\r
+_podr16 .EQU 0x000E10\r
+PODR16 .EQU 0x000E10\r
+_podr17 .EQU 0x000E11\r
+PODR17 .EQU 0x000E11\r
+_podr18 .EQU 0x000E12\r
+PODR18 .EQU 0x000E12\r
+_podr19 .EQU 0x000E13\r
+PODR19 .EQU 0x000E13\r
+_podr20 .EQU 0x000E14\r
+PODR20 .EQU 0x000E14\r
+_podr21 .EQU 0x000E15\r
+PODR21 .EQU 0x000E15\r
+_podr22 .EQU 0x000E16\r
+PODR22 .EQU 0x000E16\r
+_podr24 .EQU 0x000E18\r
+PODR24 .EQU 0x000E18\r
+_podr26 .EQU 0x000E1A\r
+PODR26 .EQU 0x000E1A\r
+_podr27 .EQU 0x000E1B\r
+PODR27 .EQU 0x000E1B\r
+_podr28 .EQU 0x000E1C\r
+PODR28 .EQU 0x000E1C\r
+_podr29 .EQU 0x000E1D\r
+PODR29 .EQU 0x000E1D\r
+_pilr14 .EQU 0x000E4E\r
+PILR14 .EQU 0x000E4E /* R-bus Port Input Level Select Register */\r
+_pilr15 .EQU 0x000E4F\r
+PILR15 .EQU 0x000E4F\r
+_pilr16 .EQU 0x000E50\r
+PILR16 .EQU 0x000E50\r
+_pilr17 .EQU 0x000E51\r
+PILR17 .EQU 0x000E51\r
+_pilr18 .EQU 0x000E52\r
+PILR18 .EQU 0x000E52\r
+_pilr19 .EQU 0x000E53\r
+PILR19 .EQU 0x000E53\r
+_pilr20 .EQU 0x000E54\r
+PILR20 .EQU 0x000E54\r
+_pilr21 .EQU 0x000E55\r
+PILR21 .EQU 0x000E55\r
+_pilr22 .EQU 0x000E56\r
+PILR22 .EQU 0x000E56\r
+_pilr24 .EQU 0x000E58\r
+PILR24 .EQU 0x000E58\r
+_pilr26 .EQU 0x000E5A\r
+PILR26 .EQU 0x000E5A\r
+_pilr27 .EQU 0x000E5B\r
+PILR27 .EQU 0x000E5B\r
+_pilr28 .EQU 0x000E5C\r
+PILR28 .EQU 0x000E5C\r
+_pilr29 .EQU 0x000E5D\r
+PILR29 .EQU 0x000E5D\r
+_epilr14 .EQU 0x000E8E\r
+EPILR14 .EQU 0x000E8E /* R-bus Port Extra Input Level Select Register */\r
+_epilr15 .EQU 0x000E8F\r
+EPILR15 .EQU 0x000E8F\r
+_epilr16 .EQU 0x000E90\r
+EPILR16 .EQU 0x000E90\r
+_epilr17 .EQU 0x000E91\r
+EPILR17 .EQU 0x000E91\r
+_epilr18 .EQU 0x000E92\r
+EPILR18 .EQU 0x000E92\r
+_epilr19 .EQU 0x000E93\r
+EPILR19 .EQU 0x000E93\r
+_epilr20 .EQU 0x000E94\r
+EPILR20 .EQU 0x000E94\r
+_epilr21 .EQU 0x000E95\r
+EPILR21 .EQU 0x000E95\r
+_epilr22 .EQU 0x000E96\r
+EPILR22 .EQU 0x000E96\r
+_epilr24 .EQU 0x000E98\r
+EPILR24 .EQU 0x000E98\r
+_epilr26 .EQU 0x000E9A\r
+EPILR26 .EQU 0x000E9A\r
+_epilr27 .EQU 0x000E9B\r
+EPILR27 .EQU 0x000E9B\r
+_epilr28 .EQU 0x000E9C\r
+EPILR28 .EQU 0x000E9C\r
+_epilr29 .EQU 0x000E9D\r
+EPILR29 .EQU 0x000E9D\r
+_pper14 .EQU 0x000ECE\r
+PPER14 .EQU 0x000ECE /* R-bus Port Pull-Up/Down Enable Register */\r
+_pper15 .EQU 0x000ECF\r
+PPER15 .EQU 0x000ECF\r
+_pper16 .EQU 0x000ED0\r
+PPER16 .EQU 0x000ED0\r
+_pper17 .EQU 0x000ED1\r
+PPER17 .EQU 0x000ED1\r
+_pper18 .EQU 0x000ED1\r
+PPER18 .EQU 0x000ED1\r
+_pper19 .EQU 0x000ED2\r
+PPER19 .EQU 0x000ED2\r
+_pper20 .EQU 0x000ED4\r
+PPER20 .EQU 0x000ED4\r
+_pper21 .EQU 0x000ED5\r
+PPER21 .EQU 0x000ED5\r
+_pper22 .EQU 0x000ED6\r
+PPER22 .EQU 0x000ED6\r
+_pper24 .EQU 0x000ED8\r
+PPER24 .EQU 0x000ED8\r
+_pper26 .EQU 0x000EDA\r
+PPER26 .EQU 0x000EDA\r
+_pper27 .EQU 0x000EDB\r
+PPER27 .EQU 0x000EDB\r
+_pper28 .EQU 0x000EDC\r
+PPER28 .EQU 0x000EDC\r
+_pper29 .EQU 0x000EDD\r
+PPER29 .EQU 0x000EDD\r
+_ppcr14 .EQU 0x000F0E\r
+PPCR14 .EQU 0x000F0E /* R-bus Port Pull-Up/Down Control Register */\r
+_ppcr15 .EQU 0x000F0F\r
+PPCR15 .EQU 0x000F0F\r
+_ppcr16 .EQU 0x000F10\r
+PPCR16 .EQU 0x000F10\r
+_ppcr17 .EQU 0x000F11\r
+PPCR17 .EQU 0x000F11\r
+_ppcr18 .EQU 0x000F12\r
+PPCR18 .EQU 0x000F12\r
+_ppcr19 .EQU 0x000F13\r
+PPCR19 .EQU 0x000F13\r
+_ppcr20 .EQU 0x000F14\r
+PPCR20 .EQU 0x000F14\r
+_ppcr21 .EQU 0x000F15\r
+PPCR21 .EQU 0x000F15\r
+_ppcr22 .EQU 0x000F16\r
+PPCR22 .EQU 0x000F16\r
+_ppcr24 .EQU 0x000F18\r
+PPCR24 .EQU 0x000F18\r
+_ppcr26 .EQU 0x000F1A\r
+PPCR26 .EQU 0x000F1A\r
+_ppcr27 .EQU 0x000F1B\r
+PPCR27 .EQU 0x000F1B\r
+_ppcr28 .EQU 0x000F1C\r
+PPCR28 .EQU 0x000F1C\r
+_ppcr29 .EQU 0x000F1D\r
+PPCR29 .EQU 0x000F1D\r
+_dmasa0 .EQU 0x001000\r
+DMASA0 .EQU 0x001000 /* DMAC */\r
+_dmada0 .EQU 0x001004\r
+DMADA0 .EQU 0x001004\r
+_dmasa1 .EQU 0x001008\r
+DMASA1 .EQU 0x001008\r
+_dmada1 .EQU 0x00100C\r
+DMADA1 .EQU 0x00100C\r
+_dmasa2 .EQU 0x001010\r
+DMASA2 .EQU 0x001010\r
+_dmada2 .EQU 0x001014\r
+DMADA2 .EQU 0x001014\r
+_dmasa3 .EQU 0x001018\r
+DMASA3 .EQU 0x001018\r
+_dmada3 .EQU 0x00101C\r
+DMADA3 .EQU 0x00101C\r
+_dmasa4 .EQU 0x001020\r
+DMASA4 .EQU 0x001020\r
+_dmada4 .EQU 0x001024\r
+DMADA4 .EQU 0x001024\r
+_fmcs .EQU 0x007000\r
+FMCS .EQU 0x007000 /* Flash Memory/I-Cache Control Register */\r
+_fmcr .EQU 0x007001\r
+FMCR .EQU 0x007001\r
+_fchcr .EQU 0x007002\r
+FCHCR .EQU 0x007002\r
+_fmwt .EQU 0x007004\r
+FMWT .EQU 0x007004\r
+_fmwt2 .EQU 0x007006\r
+FMWT2 .EQU 0x007006\r
+_fmps .EQU 0x007007\r
+FMPS .EQU 0x007007\r
+_fmac .EQU 0x007008\r
+FMAC .EQU 0x007008\r
+_fcha0 .EQU 0x00700C\r
+FCHA0 .EQU 0x00700C /* I_Cache Nonchachable area settings Register */\r
+_fcha1 .EQU 0x007010\r
+FCHA1 .EQU 0x007010\r
+_fscr0 .EQU 0x007100\r
+FSCR0 .EQU 0x007100 /* Flash Security Control Register */\r
+_fscr1 .EQU 0x007104\r
+FSCR1 .EQU 0x007104\r
+_ctrlr4 .EQU 0x00C400\r
+CTRLR4 .EQU 0x00C400 /* CAN 4 Control Register */\r
+_statr4 .EQU 0x00C402\r
+STATR4 .EQU 0x00C402\r
+_errcnt4 .EQU 0x00C404\r
+ERRCNT4 .EQU 0x00C404\r
+_btr4 .EQU 0x00C406\r
+BTR4 .EQU 0x00C406\r
+_intr4 .EQU 0x00C408\r
+INTR4 .EQU 0x00C408\r
+_testr4 .EQU 0x00C40A\r
+TESTR4 .EQU 0x00C40A\r
+_brper4 .EQU 0x00C40C\r
+BRPER4 .EQU 0x00C40C\r
+_brpe4 .EQU 0x00C40C\r
+BRPE4 .EQU 0x00C40C\r
+_if1creq4 .EQU 0x00C410\r
+IF1CREQ4 .EQU 0x00C410 /* CAN 4 IF 1 */\r
+_if1cmsk4 .EQU 0x00C412\r
+IF1CMSK4 .EQU 0x00C412\r
+_if1msk124 .EQU 0x00C414\r
+IF1MSK124 .EQU 0x00C414\r
+_if1msk24 .EQU 0x00C414\r
+IF1MSK24 .EQU 0x00C414\r
+_if1msk14 .EQU 0x00C416\r
+IF1MSK14 .EQU 0x00C416\r
+_if1arb124 .EQU 0x00C418\r
+IF1ARB124 .EQU 0x00C418\r
+_if1arb24 .EQU 0x00C418\r
+IF1ARB24 .EQU 0x00C418\r
+_if1arb14 .EQU 0x00C41A\r
+IF1ARB14 .EQU 0x00C41A\r
+_if1mctr4 .EQU 0x00C41C\r
+IF1MCTR4 .EQU 0x00C41C\r
+_if1dta124 .EQU 0x00C420\r
+IF1DTA124 .EQU 0x00C420\r
+_if1dta14 .EQU 0x00C420\r
+IF1DTA14 .EQU 0x00C420\r
+_if1dta24 .EQU 0x00C422\r
+IF1DTA24 .EQU 0x00C422\r
+_if1dtb124 .EQU 0x00C424\r
+IF1DTB124 .EQU 0x00C424\r
+_if1dtb14 .EQU 0x00C424\r
+IF1DTB14 .EQU 0x00C424\r
+_if1dtb24 .EQU 0x00C426\r
+IF1DTB24 .EQU 0x00C426\r
+_if1dta_swp124 .EQU 0x00C430\r
+IF1DTA_SWP124 .EQU 0x00C430\r
+_if1dta_swp24 .EQU 0x00C430\r
+IF1DTA_SWP24 .EQU 0x00C430\r
+_if1dta_swp14 .EQU 0x00C432\r
+IF1DTA_SWP14 .EQU 0x00C432\r
+_if1dtb_swp124 .EQU 0x00C434\r
+IF1DTB_SWP124 .EQU 0x00C434\r
+_if1dtb_swp24 .EQU 0x00C434\r
+IF1DTB_SWP24 .EQU 0x00C434\r
+_if1dtb_swp14 .EQU 0x00C436\r
+IF1DTB_SWP14 .EQU 0x00C436\r
+_if2creq4 .EQU 0x00C440\r
+IF2CREQ4 .EQU 0x00C440 /* CAN 4 IF 2 */\r
+_if2cmsk4 .EQU 0x00C442\r
+IF2CMSK4 .EQU 0x00C442\r
+_if2msk124 .EQU 0x00C444\r
+IF2MSK124 .EQU 0x00C444\r
+_if2msk24 .EQU 0x00C444\r
+IF2MSK24 .EQU 0x00C444\r
+_if2msk14 .EQU 0x00C446\r
+IF2MSK14 .EQU 0x00C446\r
+_if2arb124 .EQU 0x00C448\r
+IF2ARB124 .EQU 0x00C448\r
+_if2arb24 .EQU 0x00C448\r
+IF2ARB24 .EQU 0x00C448\r
+_if2arb14 .EQU 0x00C44A\r
+IF2ARB14 .EQU 0x00C44A\r
+_if2mctr4 .EQU 0x00C44C\r
+IF2MCTR4 .EQU 0x00C44C\r
+_if2dta124 .EQU 0x00C450\r
+IF2DTA124 .EQU 0x00C450\r
+_if2dta14 .EQU 0x00C450\r
+IF2DTA14 .EQU 0x00C450\r
+_if2dta24 .EQU 0x00C452\r
+IF2DTA24 .EQU 0x00C452\r
+_if2dtb124 .EQU 0x00C454\r
+IF2DTB124 .EQU 0x00C454\r
+_if2dtb14 .EQU 0x00C454\r
+IF2DTB14 .EQU 0x00C454\r
+_if2dtb24 .EQU 0x00C456\r
+IF2DTB24 .EQU 0x00C456\r
+_if2dta_swp124 .EQU 0x00C460\r
+IF2DTA_SWP124 .EQU 0x00C460\r
+_if2dta_swp24 .EQU 0x00C460\r
+IF2DTA_SWP24 .EQU 0x00C460\r
+_if2dta_swp14 .EQU 0x00C462\r
+IF2DTA_SWP14 .EQU 0x00C462\r
+_if2dtb_swp124 .EQU 0x00C464\r
+IF2DTB_SWP124 .EQU 0x00C464\r
+_if2dtb_swp24 .EQU 0x00C464\r
+IF2DTB_SWP24 .EQU 0x00C464\r
+_if2dtb_swp14 .EQU 0x00C466\r
+IF2DTB_SWP14 .EQU 0x00C466\r
+_treqr124 .EQU 0x00C480\r
+TREQR124 .EQU 0x00C480 /* CAN 4 Status Flags */\r
+_treqr24 .EQU 0x00C480\r
+TREQR24 .EQU 0x00C480\r
+_treqr14 .EQU 0x00C482\r
+TREQR14 .EQU 0x00C482\r
+_treqr344 .EQU 0x00C484\r
+TREQR344 .EQU 0x00C484\r
+_newdt124 .EQU 0x00C490\r
+NEWDT124 .EQU 0x00C490\r
+_newdt24 .EQU 0x00C490\r
+NEWDT24 .EQU 0x00C490\r
+_newdt14 .EQU 0x00C492\r
+NEWDT14 .EQU 0x00C492\r
+_intpnd124 .EQU 0x00C4A0\r
+INTPND124 .EQU 0x00C4A0\r
+_intpnd24 .EQU 0x00C4A0\r
+INTPND24 .EQU 0x00C4A0\r
+_intpnd14 .EQU 0x00C4A2\r
+INTPND14 .EQU 0x00C4A2\r
+_msgval124 .EQU 0x00C4B0\r
+MSGVAL124 .EQU 0x00C4B0\r
+_msgval24 .EQU 0x00C4B0\r
+MSGVAL24 .EQU 0x00C4B0\r
+_msgval14 .EQU 0x00C4B2\r
+MSGVAL14 .EQU 0x00C4B2\r
+_bctrl .EQU 0x00F000\r
+BCTRL .EQU 0x00F000 /* EDSU/MPU Registers */\r
+_bstat .EQU 0x00F004\r
+BSTAT .EQU 0x00F004\r
+_biac .EQU 0x00F008\r
+BIAC .EQU 0x00F008\r
+_boac .EQU 0x00F00C\r
+BOAC .EQU 0x00F00C\r
+_birq .EQU 0x00F010\r
+BIRQ .EQU 0x00F010\r
+_bcr0 .EQU 0x00F020\r
+BCR0 .EQU 0x00F020\r
+_bcr1 .EQU 0x00F024\r
+BCR1 .EQU 0x00F024\r
+_bad0 .EQU 0x00F080\r
+BAD0 .EQU 0x00F080\r
+_bad1 .EQU 0x00F084\r
+BAD1 .EQU 0x00F084\r
+_bad2 .EQU 0x00F088\r
+BAD2 .EQU 0x00F088\r
+_bad3 .EQU 0x00F08C\r
+BAD3 .EQU 0x00F08C\r
+_bad4 .EQU 0x00F090\r
+BAD4 .EQU 0x00F090\r
+_bad5 .EQU 0x00F094\r
+BAD5 .EQU 0x00F094\r
+_bad6 .EQU 0x00F098\r
+BAD6 .EQU 0x00F098\r
+_bad7 .EQU 0x00F09C\r
+BAD7 .EQU 0x00F09C\r
+_fsv1 .EQU 0x148000\r
+FSV1 .EQU 0x148000 /* FSV & BSV Registers */\r
+_bsv1 .EQU 0x148004\r
+BSV1 .EQU 0x148004\r
+_fsv2 .EQU 0x148008\r
+FSV2 .EQU 0x148008\r
+_bsv2 .EQU 0x14800C\r
+BSV2 .EQU 0x14800C\r
+#pragma endasm\r
+#else\r
+\r
+#ifndef _MB91XXX_H\r
+#define _MB91XXX_H\r
+\r
+#ifdef __FASM__ \r
+#pragma asm\r
+ .IMPORT _pdr14, _pdr15, _pdr16, _pdr17, _pdr18, _pdr19\r
+ .IMPORT _pdr20, _pdr21, _pdr22, _pdr24, _pdr26, _pdr27\r
+ .IMPORT _pdr28, _pdr29, _eirr0, _enir0, _elvr0, _eirr1\r
+ .IMPORT _enir1, _elvr1, _dicr, _hrcl, _rbsync, _scr00\r
+ .IMPORT _smr00, _ssr00, _rdr00, _tdr00, _escr00, _eccr00\r
+ .IMPORT _scr01, _smr01, _ssr01, _rdr01, _tdr01, _escr01\r
+ .IMPORT _eccr01, _scr02, _smr02, _ssr02, _rdr02, _tdr02\r
+ .IMPORT _escr02, _eccr02, _scr03, _smr03, _ssr03, _rdr03\r
+ .IMPORT _tdr03, _escr03, _eccr03, _scr04, _smr04, _ssr04\r
+ .IMPORT _rdr04, _tdr04, _escr04, _eccr04, _fsr04, _fcr04\r
+ .IMPORT _bgr00, _bgr100, _bgr000, _bgr01, _bgr101, _bgr001\r
+ .IMPORT _bgr02, _bgr102, _bgr002, _bgr03, _bgr103, _bgr003\r
+ .IMPORT _bgr04, _bgr104, _bgr004, _ibcr0, _ibsr0, _itba0\r
+ .IMPORT _itbah0, _itbal0, _itmk0, _itmkh0, _itmkl0, _ismk0\r
+ .IMPORT _isba0, _idar0, _iccr0, _gcn10, _gcn20, _gcn11\r
+ .IMPORT _gcn21, _gcn12, _gcn22, _ptmr00, _pcsr00, _pdut00\r
+ .IMPORT _pcn00, _pcnh00, _pcnl00, _ptmr01, _pcsr01, _pdut01\r
+ .IMPORT _pcn01, _pcnh01, _pcnl01, _ptmr02, _pcsr02, _pdut02\r
+ .IMPORT _pcn02, _pcnh02, _pcnl02, _ptmr03, _pcsr03, _pdut03\r
+ .IMPORT _pcn03, _pcnh03, _pcnl03, _ptmr04, _pcsr04, _pdut04\r
+ .IMPORT _pcn04, _pcnh04, _pcnl04, _ptmr05, _pcsr05, _pdut05\r
+ .IMPORT _pcn05, _pcnh05, _pcnl05, _ptmr06, _pcsr06, _pdut06\r
+ .IMPORT _pcn06, _pcnh06, _pcnl06, _ptmr07, _pcsr07, _pdut07\r
+ .IMPORT _pcn07, _pcnh07, _pcnl07, _ptmr08, _pcsr08, _pdut08\r
+ .IMPORT _pcn08, _pcnh08, _pcnl08, _ptmr09, _pcsr09, _pdut09\r
+ .IMPORT _pcn09, _pcnh09, _pcnl09, _ptmr10, _pcsr10, _pdut10\r
+ .IMPORT _pcn10, _pcnh10, _pcnl10, _ptmr11, _pcsr11, _pdut11\r
+ .IMPORT _pcn11, _pcnh11, _pcnl11, _ics01, _ics23, _ipcp0\r
+ .IMPORT _ipcp1, _ipcp2, _ipcp3, _ocs01, _ocs23, _occp0\r
+ .IMPORT _occp1, _occp2, _occp3, _aderh, _aderl, _ader\r
+ .IMPORT _adcs1, _adcs0, _adcs, _adcr1, _adcr0, _adcr\r
+ .IMPORT _adct1, _adct0, _adct, _adsch, _adech, _tmrlr0\r
+ .IMPORT _tmr0, _tmcsr0, _tmcsrh0, _tmcsrl0, _tmrlr1, _tmr1\r
+ .IMPORT _tmcsr1, _tmcsrh1, _tmcsrl1, _tmrlr2, _tmr2, _tmcsr2\r
+ .IMPORT _tmcsrh2, _tmcsrl2, _tmrlr3, _tmr3, _tmcsr3, _tmcsrh3\r
+ .IMPORT _tmcsrl3, _tmrlr4, _tmr4, _tmcsr4, _tmcsrh4, _tmcsrl4\r
+ .IMPORT _tmrlr5, _tmr5, _tmcsr5, _tmcsrh5, _tmcsrl5, _tmrlr6\r
+ .IMPORT _tmr6, _tmcsr6, _tmcsrh6, _tmcsrl6, _tmrlr7, _tmr7\r
+ .IMPORT _tmcsr7, _tmcsrh7, _tmcsrl7, _tcdt0, _tccs0, _tcdt1\r
+ .IMPORT _tccs1, _tcdt2, _tccs2, _tcdt3, _tccs3, _dmaca0\r
+ .IMPORT _dmacb0, _dmaca1, _dmacb1, _dmaca2, _dmacb2, _dmaca3\r
+ .IMPORT _dmacb3, _dmaca4, _dmacb4, _dmacr, _ics45, _ics67\r
+ .IMPORT _ipcp4, _ipcp5, _ipcp6, _ipcp7, _ocs45, _ocs67\r
+ .IMPORT _occp4, _occp5, _occp6, _occp7, _tcdt4, _tccs4\r
+ .IMPORT _tcdt5, _tccs5, _tcdt6, _tccs6, _tcdt7, _tccs7\r
+ .IMPORT _roms, _bsd0, _bsd1, _bsdc, _bsrr, _icr00\r
+ .IMPORT _icr01, _icr02, _icr03, _icr04, _icr05, _icr06\r
+ .IMPORT _icr07, _icr08, _icr09, _icr10, _icr11, _icr12\r
+ .IMPORT _icr13, _icr14, _icr15, _icr16, _icr17, _icr18\r
+ .IMPORT _icr19, _icr20, _icr21, _icr22, _icr23, _icr24\r
+ .IMPORT _icr25, _icr26, _icr27, _icr28, _icr29, _icr30\r
+ .IMPORT _icr31, _icr32, _icr33, _icr34, _icr35, _icr36\r
+ .IMPORT _icr37, _icr38, _icr39, _icr40, _icr41, _icr42\r
+ .IMPORT _icr43, _icr44, _icr45, _icr46, _icr47, _icr48\r
+ .IMPORT _icr49, _icr50, _icr51, _icr52, _icr53, _icr54\r
+ .IMPORT _icr55, _icr56, _icr57, _icr58, _icr59, _icr60\r
+ .IMPORT _icr61, _icr62, _icr63, _rsrr, _stcr, _tbcr\r
+ .IMPORT _ctbr, _clkr, _wpr, _divr0, _divr1, _plldivm\r
+ .IMPORT _plldivn, _plldivg, _pllmulg, _pllctrl, _oscc1, _oscs1\r
+ .IMPORT _oscc2, _oscs2, _porten, _wtcer, _wtcr, _wtbr\r
+ .IMPORT _wthr, _wtmr, _wtsr, _csvtr, _csvcr, _cscfg\r
+ .IMPORT _cmcfg, _cucr, _cutd, _cutr1, _cutr2, _cmpr\r
+ .IMPORT _cmcr, _cmt1, _cmt2, _canpre, _canckd, _lvsel\r
+ .IMPORT _lvdet, _hwwde, _hwwd, _oscrh, _oscrl, _wpcrh\r
+ .IMPORT _wpcrl, _osccr, _regsel, _regctr, _modr, _pdrd14\r
+ .IMPORT _pdrd15, _pdrd16, _pdrd17, _pdrd18, _pdrd19, _pdrd20\r
+ .IMPORT _pdrd21, _pdrd22, _pdrd24, _pdrd26, _pdrd27, _pdrd28\r
+ .IMPORT _pdrd29, _ddr14, _ddr15, _ddr16, _ddr17, _ddr18\r
+ .IMPORT _ddr19, _ddr20, _ddr21, _ddr22, _ddr24, _ddr26\r
+ .IMPORT _ddr27, _ddr28, _ddr29, _pfr14, _pfr15, _pfr16\r
+ .IMPORT _pfr17, _pfr18, _pfr19, _pfr20, _pfr21, _pfr22\r
+ .IMPORT _pfr24, _pfr26, _pfr27, _pfr28, _pfr29, _epfr14\r
+ .IMPORT _epfr15, _epfr16, _epfr17, _epfr18, _epfr19, _epfr20\r
+ .IMPORT _epfr21, _epfr22, _epfr24, _epfr26, _epfr27, _epfr29\r
+ .IMPORT _podr14, _podr15, _podr16, _podr17, _podr18, _podr19\r
+ .IMPORT _podr20, _podr21, _podr22, _podr24, _podr26, _podr27\r
+ .IMPORT _podr28, _podr29, _pilr14, _pilr15, _pilr16, _pilr17\r
+ .IMPORT _pilr18, _pilr19, _pilr20, _pilr21, _pilr22, _pilr24\r
+ .IMPORT _pilr26, _pilr27, _pilr28, _pilr29, _epilr14, _epilr15\r
+ .IMPORT _epilr16, _epilr17, _epilr18, _epilr19, _epilr20, _epilr21\r
+ .IMPORT _epilr22, _epilr24, _epilr26, _epilr27, _epilr28, _epilr29\r
+ .IMPORT _pper14, _pper15, _pper16, _pper17, _pper18, _pper19\r
+ .IMPORT _pper20, _pper21, _pper22, _pper24, _pper26, _pper27\r
+ .IMPORT _pper28, _pper29, _ppcr14, _ppcr15, _ppcr16, _ppcr17\r
+ .IMPORT _ppcr18, _ppcr19, _ppcr20, _ppcr21, _ppcr22, _ppcr24\r
+ .IMPORT _ppcr26, _ppcr27, _ppcr28, _ppcr29, _dmasa0, _dmada0\r
+ .IMPORT _dmasa1, _dmada1, _dmasa2, _dmada2, _dmasa3, _dmada3\r
+ .IMPORT _dmasa4, _dmada4, _fmcs, _fmcr, _fchcr, _fmwt\r
+ .IMPORT _fmwt2, _fmps, _fmac, _fcha0, _fcha1, _fscr0\r
+ .IMPORT _fscr1, _ctrlr4, _statr4, _errcnt4, _btr4, _intr4\r
+ .IMPORT _testr4, _brper4, _brpe4, _if1creq4, _if1cmsk4, _if1msk124\r
+ .IMPORT _if1msk24, _if1msk14, _if1arb124, _if1arb24, _if1arb14, _if1mctr4\r
+ .IMPORT _if1dta124, _if1dta14, _if1dta24, _if1dtb124, _if1dtb14, _if1dtb24\r
+ .IMPORT _if1dta_swp124, _if1dta_swp24, _if1dta_swp14, _if1dtb_swp124, _if1dtb_swp24, _if1dtb_swp14\r
+ .IMPORT _if2creq4, _if2cmsk4, _if2msk124, _if2msk24, _if2msk14, _if2arb124\r
+ .IMPORT _if2arb24, _if2arb14, _if2mctr4, _if2dta124, _if2dta14, _if2dta24\r
+ .IMPORT _if2dtb124, _if2dtb14, _if2dtb24, _if2dta_swp124, _if2dta_swp24, _if2dta_swp14\r
+ .IMPORT _if2dtb_swp124, _if2dtb_swp24, _if2dtb_swp14, _treqr124, _treqr24, _treqr14\r
+ .IMPORT _treqr344, _newdt124, _newdt24, _newdt14, _intpnd124, _intpnd24\r
+ .IMPORT _intpnd14, _msgval124, _msgval24, _msgval14, _bctrl, _bstat\r
+ .IMPORT _biac, _boac, _birq, _bcr0, _bcr1, _bad0\r
+ .IMPORT _bad1, _bad2, _bad3, _bad4, _bad5, _bad6\r
+ .IMPORT _bad7, _fsv1, _bsv1, _fsv2, _bsv2\r
+#pragma endasm\r
+#else /* __FASM__ */ \r
+/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */\r
+/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */\r
+/* ELIGIBILITY FOR ANY PURPOSES. */\r
+/* (C) Fujitsu Microelectronics Europe GmbH */\r
+/* */\r
+/* ************************************************************************* */\r
+/* Fujitsu Microelectronics Europe GmbH */\r
+/* Pittlerstrasse 47, 63225 Langen */\r
+/* Tel.: +49 (6103) 690-0, Fax -122 */\r
+/* */\r
+/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */\r
+/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */\r
+/* ELIGIBILITY FOR ANY PURPOSES */\r
+/* (C) Fujitsu Microelectronics Europe GmbH */\r
+/* ************************************************************************* */\r
+/* ---------------------------------------------------------------------- */\r
+/* Id: MB91465K.h,v 1.5 2007/01/04 11:04:48 meffen Exp */\r
+/* ---------------------------------------------------------------------- */\r
+/* Id: MB91465K.h,v 1.5 2007/01/04 11:04:48 meffen Exp */\r
+/* - removed LCD and Sound Controller */\r
+/* Id: MB91465K.iow,v 1.5 2006/11/30 14:39:18 meffen Exp */\r
+/* - format of comment lines adapted */\r
+/* BIT-STRUCTURE-DEFINITIONS */\r
+\r
+typedef unsigned char IO_BYTE;\r
+typedef unsigned short IO_WORD;\r
+typedef unsigned long IO_LWORD;\r
+typedef const unsigned short IO_WORD_READ;\r
+\r
+typedef union{ /* Port Data Register */\r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PDR14STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PDR15STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PDR16STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PDR17STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ }bit;\r
+ }PDR18STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PDR19STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PDR20STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PDR21STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PDR22STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PDR24STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PDR26STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PDR27STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PDR28STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PDR29STR;\r
+typedef union{ /* External Interrupt 0-7 */\r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _ER7 :1;\r
+ IO_BYTE _ER6 :1;\r
+ IO_BYTE _ER5 :1;\r
+ IO_BYTE _ER4 :1;\r
+ IO_BYTE _ER3 :1;\r
+ IO_BYTE _ER2 :1;\r
+ IO_BYTE _ER1 :1;\r
+ IO_BYTE _ER0 :1;\r
+ }bit;\r
+ }EIRR0STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _EN7 :1;\r
+ IO_BYTE _EN6 :1;\r
+ IO_BYTE _EN5 :1;\r
+ IO_BYTE _EN4 :1;\r
+ IO_BYTE _EN3 :1;\r
+ IO_BYTE _EN2 :1;\r
+ IO_BYTE _EN1 :1;\r
+ IO_BYTE _EN0 :1;\r
+ }bit;\r
+ }ENIR0STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _LB7 :1;\r
+ IO_WORD _LA7 :1;\r
+ IO_WORD _LB6 :1;\r
+ IO_WORD _LA6 :1;\r
+ IO_WORD _LB5 :1;\r
+ IO_WORD _LA5 :1;\r
+ IO_WORD _LB4 :1;\r
+ IO_WORD _LA4 :1;\r
+ IO_WORD _LB3 :1;\r
+ IO_WORD _LA3 :1;\r
+ IO_WORD _LB2 :1;\r
+ IO_WORD _LA2 :1;\r
+ IO_WORD _LB1 :1;\r
+ IO_WORD _LA1 :1;\r
+ IO_WORD _LB0 :1;\r
+ IO_WORD _LA0 :1;\r
+ }bit;\r
+ }ELVR0STR;\r
+typedef union{ /* External Interrupt 8-15 */\r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _ER15 :1;\r
+ IO_BYTE _ER14 :1;\r
+ IO_BYTE _ER13 :1;\r
+ IO_BYTE _ER12 :1;\r
+ IO_BYTE _ER11 :1;\r
+ IO_BYTE _ER10 :1;\r
+ IO_BYTE _ER9 :1;\r
+ IO_BYTE _ER8 :1;\r
+ }bit;\r
+ }EIRR1STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _EN15 :1;\r
+ IO_BYTE _EN14 :1;\r
+ IO_BYTE _EN13 :1;\r
+ IO_BYTE _EN12 :1;\r
+ IO_BYTE _EN11 :1;\r
+ IO_BYTE _EN10 :1;\r
+ IO_BYTE _EN9 :1;\r
+ IO_BYTE _EN8 :1;\r
+ }bit;\r
+ }ENIR1STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _LB15 :1;\r
+ IO_WORD _LA15 :1;\r
+ IO_WORD _LB14 :1;\r
+ IO_WORD _LA14 :1;\r
+ IO_WORD _LB13 :1;\r
+ IO_WORD _LA13 :1;\r
+ IO_WORD _LB12 :1;\r
+ IO_WORD _LA12 :1;\r
+ IO_WORD _LB11 :1;\r
+ IO_WORD _LA11 :1;\r
+ IO_WORD _LB10 :1;\r
+ IO_WORD _LA10 :1;\r
+ IO_WORD _LB9 :1;\r
+ IO_WORD _LA9 :1;\r
+ IO_WORD _LB8 :1;\r
+ IO_WORD _LA8 :1;\r
+ }bit;\r
+ }ELVR1STR;\r
+typedef union{ /* DLYI/I-unit */\r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _DLYI :1;\r
+ }bit;\r
+ }DICRSTR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _MHALTI :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _LVL4 :1;\r
+ IO_BYTE _LVL3 :1;\r
+ IO_BYTE _LVL2 :1;\r
+ IO_BYTE _LVL1 :1;\r
+ IO_BYTE _LVL0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _LVL :5;\r
+ }bitc;\r
+ }HRCLSTR;\r
+typedef union{ /* USART (LIN) 0 */\r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _PEN :1;\r
+ IO_BYTE _P :1;\r
+ IO_BYTE _SBL :1;\r
+ IO_BYTE _CL :1;\r
+ IO_BYTE _AD :1;\r
+ IO_BYTE _CRE :1;\r
+ IO_BYTE _RXE :1;\r
+ IO_BYTE _TXE :1;\r
+ }bit;\r
+ }SCR00STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _MD1 :1;\r
+ IO_BYTE _MD0 :1;\r
+ IO_BYTE _OTO :1;\r
+ IO_BYTE _EXT :1;\r
+ IO_BYTE _REST :1;\r
+ IO_BYTE _UPCL :1;\r
+ IO_BYTE _SCKE :1;\r
+ IO_BYTE _SOE :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE _MD :2;\r
+ }bitc;\r
+ }SMR00STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _PE :1;\r
+ IO_BYTE _ORE :1;\r
+ IO_BYTE _FRE :1;\r
+ IO_BYTE _RDRF :1;\r
+ IO_BYTE _TDRE :1;\r
+ IO_BYTE _BDS :1;\r
+ IO_BYTE _RIE :1;\r
+ IO_BYTE _TIE :1;\r
+ }bit;\r
+ }SSR00STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _LBIE :1;\r
+ IO_BYTE _LBD :1;\r
+ IO_BYTE _LBL1 :1;\r
+ IO_BYTE _LBL0 :1;\r
+ IO_BYTE _SOPE :1;\r
+ IO_BYTE _SIOP :1;\r
+ IO_BYTE _CCO :1;\r
+ IO_BYTE _SCES :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _LBL :2;\r
+ }bitc;\r
+ }ESCR00STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _INV :1;\r
+ IO_BYTE _LBR :1;\r
+ IO_BYTE _MS :1;\r
+ IO_BYTE _SCDE :1;\r
+ IO_BYTE _SSM :1;\r
+ IO_BYTE _BIE :1;\r
+ IO_BYTE _RBI :1;\r
+ IO_BYTE _TBI :1;\r
+ }bit;\r
+ }ECCR00STR;\r
+typedef union{ /* USART (LIN) 1 */\r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _PEN :1;\r
+ IO_BYTE _P :1;\r
+ IO_BYTE _SBL :1;\r
+ IO_BYTE _CL :1;\r
+ IO_BYTE _AD :1;\r
+ IO_BYTE _CRE :1;\r
+ IO_BYTE _RXE :1;\r
+ IO_BYTE _TXE :1;\r
+ }bit;\r
+ }SCR01STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _MD1 :1;\r
+ IO_BYTE _MD0 :1;\r
+ IO_BYTE _OTO :1;\r
+ IO_BYTE _EXT :1;\r
+ IO_BYTE _REST :1;\r
+ IO_BYTE _UPCL :1;\r
+ IO_BYTE _SCKE :1;\r
+ IO_BYTE _SOE :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE _MD :2;\r
+ }bitc;\r
+ }SMR01STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _PE :1;\r
+ IO_BYTE _ORE :1;\r
+ IO_BYTE _FRE :1;\r
+ IO_BYTE _RDRF :1;\r
+ IO_BYTE _TDRE :1;\r
+ IO_BYTE _BDS :1;\r
+ IO_BYTE _RIE :1;\r
+ IO_BYTE _TIE :1;\r
+ }bit;\r
+ }SSR01STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _LBIE :1;\r
+ IO_BYTE _LBD :1;\r
+ IO_BYTE _LBL1 :1;\r
+ IO_BYTE _LBL0 :1;\r
+ IO_BYTE _SOPE :1;\r
+ IO_BYTE _SIOP :1;\r
+ IO_BYTE _CCO :1;\r
+ IO_BYTE _SCES :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _LBL :2;\r
+ }bitc;\r
+ }ESCR01STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _INV :1;\r
+ IO_BYTE _LBR :1;\r
+ IO_BYTE _MS :1;\r
+ IO_BYTE _SCDE :1;\r
+ IO_BYTE _SSM :1;\r
+ IO_BYTE _BIE :1;\r
+ IO_BYTE _RBI :1;\r
+ IO_BYTE _TBI :1;\r
+ }bit;\r
+ }ECCR01STR;\r
+typedef union{ /* USART (LIN) 2 */\r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _PEN :1;\r
+ IO_BYTE _P :1;\r
+ IO_BYTE _SBL :1;\r
+ IO_BYTE _CL :1;\r
+ IO_BYTE _AD :1;\r
+ IO_BYTE _CRE :1;\r
+ IO_BYTE _RXE :1;\r
+ IO_BYTE _TXE :1;\r
+ }bit;\r
+ }SCR02STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _MD1 :1;\r
+ IO_BYTE _MD0 :1;\r
+ IO_BYTE _OTO :1;\r
+ IO_BYTE _EXT :1;\r
+ IO_BYTE _REST :1;\r
+ IO_BYTE _UPCL :1;\r
+ IO_BYTE _SCKE :1;\r
+ IO_BYTE _SOE :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE _MD :2;\r
+ }bitc;\r
+ }SMR02STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _PE :1;\r
+ IO_BYTE _ORE :1;\r
+ IO_BYTE _FRE :1;\r
+ IO_BYTE _RDRF :1;\r
+ IO_BYTE _TDRE :1;\r
+ IO_BYTE _BDS :1;\r
+ IO_BYTE _RIE :1;\r
+ IO_BYTE _TIE :1;\r
+ }bit;\r
+ }SSR02STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _LBIE :1;\r
+ IO_BYTE _LBD :1;\r
+ IO_BYTE _LBL1 :1;\r
+ IO_BYTE _LBL0 :1;\r
+ IO_BYTE _SOPE :1;\r
+ IO_BYTE _SIOP :1;\r
+ IO_BYTE _CCO :1;\r
+ IO_BYTE _SCES :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _LBL :2;\r
+ }bitc;\r
+ }ESCR02STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _INV :1;\r
+ IO_BYTE _LBR :1;\r
+ IO_BYTE _MS :1;\r
+ IO_BYTE _SCDE :1;\r
+ IO_BYTE _SSM :1;\r
+ IO_BYTE _BIE :1;\r
+ IO_BYTE _RBI :1;\r
+ IO_BYTE _TBI :1;\r
+ }bit;\r
+ }ECCR02STR;\r
+typedef union{ /* USART (LIN) 3 */\r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _PEN :1;\r
+ IO_BYTE _P :1;\r
+ IO_BYTE _SBL :1;\r
+ IO_BYTE _CL :1;\r
+ IO_BYTE _AD :1;\r
+ IO_BYTE _CRE :1;\r
+ IO_BYTE _RXE :1;\r
+ IO_BYTE _TXE :1;\r
+ }bit;\r
+ }SCR03STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _MD1 :1;\r
+ IO_BYTE _MD0 :1;\r
+ IO_BYTE _OTO :1;\r
+ IO_BYTE _EXT :1;\r
+ IO_BYTE _REST :1;\r
+ IO_BYTE _UPCL :1;\r
+ IO_BYTE _SCKE :1;\r
+ IO_BYTE _SOE :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE _MD :2;\r
+ }bitc;\r
+ }SMR03STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _PE :1;\r
+ IO_BYTE _ORE :1;\r
+ IO_BYTE _FRE :1;\r
+ IO_BYTE _RDRF :1;\r
+ IO_BYTE _TDRE :1;\r
+ IO_BYTE _BDS :1;\r
+ IO_BYTE _RIE :1;\r
+ IO_BYTE _TIE :1;\r
+ }bit;\r
+ }SSR03STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _LBIE :1;\r
+ IO_BYTE _LBD :1;\r
+ IO_BYTE _LBL1 :1;\r
+ IO_BYTE _LBL0 :1;\r
+ IO_BYTE _SOPE :1;\r
+ IO_BYTE _SIOP :1;\r
+ IO_BYTE _CCO :1;\r
+ IO_BYTE _SCES :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _LBL :2;\r
+ }bitc;\r
+ }ESCR03STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _INV :1;\r
+ IO_BYTE _LBR :1;\r
+ IO_BYTE _MS :1;\r
+ IO_BYTE _SCDE :1;\r
+ IO_BYTE _SSM :1;\r
+ IO_BYTE _BIE :1;\r
+ IO_BYTE _RBI :1;\r
+ IO_BYTE _TBI :1;\r
+ }bit;\r
+ }ECCR03STR;\r
+typedef union{ /* USART (LIN) 4 with FIFO */\r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _PEN :1;\r
+ IO_BYTE _P :1;\r
+ IO_BYTE _SBL :1;\r
+ IO_BYTE _CL :1;\r
+ IO_BYTE _AD :1;\r
+ IO_BYTE _CRE :1;\r
+ IO_BYTE _RXE :1;\r
+ IO_BYTE _TXE :1;\r
+ }bit;\r
+ }SCR04STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _MD1 :1;\r
+ IO_BYTE _MD0 :1;\r
+ IO_BYTE _OTO :1;\r
+ IO_BYTE _EXT :1;\r
+ IO_BYTE _REST :1;\r
+ IO_BYTE _UPCL :1;\r
+ IO_BYTE _SCKE :1;\r
+ IO_BYTE _SOE :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE _MD :2;\r
+ }bitc;\r
+ }SMR04STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _PE :1;\r
+ IO_BYTE _ORE :1;\r
+ IO_BYTE _FRE :1;\r
+ IO_BYTE _RDRF :1;\r
+ IO_BYTE _TDRE :1;\r
+ IO_BYTE _BDS :1;\r
+ IO_BYTE _RIE :1;\r
+ IO_BYTE _TIE :1;\r
+ }bit;\r
+ }SSR04STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _LBIE :1;\r
+ IO_BYTE _LBD :1;\r
+ IO_BYTE _LBL1 :1;\r
+ IO_BYTE _LBL0 :1;\r
+ IO_BYTE _SOPE :1;\r
+ IO_BYTE _SIOP :1;\r
+ IO_BYTE _CCO :1;\r
+ IO_BYTE _SCES :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _LBL :2;\r
+ }bitc;\r
+ }ESCR04STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _INV :1;\r
+ IO_BYTE _LBR :1;\r
+ IO_BYTE _MS :1;\r
+ IO_BYTE _SCDE :1;\r
+ IO_BYTE _SSM :1;\r
+ IO_BYTE _BIE :1;\r
+ IO_BYTE _RBI :1;\r
+ IO_BYTE _TBI :1;\r
+ }bit;\r
+ }ECCR04STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _RXL3 :1;\r
+ IO_BYTE _RXL2 :1;\r
+ IO_BYTE _RXL1 :1;\r
+ IO_BYTE _RXL0 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ERX :1;\r
+ IO_BYTE _ETX :1;\r
+ IO_BYTE _SVD :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE _RXL :4;\r
+ }bitc;\r
+ }FCR04STR;\r
+typedef union{ /* I2C 0 */\r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _BER :1;\r
+ IO_BYTE _BEIE :1;\r
+ IO_BYTE _SCC :1;\r
+ IO_BYTE _MSS :1;\r
+ IO_BYTE _ACK :1;\r
+ IO_BYTE _GCAA :1;\r
+ IO_BYTE _INTE :1;\r
+ IO_BYTE _INT :1;\r
+ }bit;\r
+ }IBCR0STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _BB :1;\r
+ IO_BYTE _RSC :1;\r
+ IO_BYTE _AL :1;\r
+ IO_BYTE _LRB :1;\r
+ IO_BYTE _TRX :1;\r
+ IO_BYTE _AAS :1;\r
+ IO_BYTE _GCA :1;\r
+ IO_BYTE _ADT :1;\r
+ }bit;\r
+ }IBSR0STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _TA9 :1;\r
+ IO_WORD _TA8 :1;\r
+ IO_WORD _TA7 :1;\r
+ IO_WORD _TA6 :1;\r
+ IO_WORD _TA5 :1;\r
+ IO_WORD _TA4 :1;\r
+ IO_WORD _TA3 :1;\r
+ IO_WORD _TA2 :1;\r
+ IO_WORD _TA1 :1;\r
+ IO_WORD _TA0 :1;\r
+ }bit;\r
+ }ITBA0STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _TA9 :1;\r
+ IO_BYTE _TA8 :1;\r
+ }bit;\r
+ }ITBAH0STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _TA7 :1;\r
+ IO_BYTE _TA6 :1;\r
+ IO_BYTE _TA5 :1;\r
+ IO_BYTE _TA4 :1;\r
+ IO_BYTE _TA3 :1;\r
+ IO_BYTE _TA2 :1;\r
+ IO_BYTE _TA1 :1;\r
+ IO_BYTE _TA0 :1;\r
+ }bit;\r
+ }ITBAL0STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _ENTB :1;\r
+ IO_WORD _RAL :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _TM9 :1;\r
+ IO_WORD _TM8 :1;\r
+ IO_WORD _TM7 :1;\r
+ IO_WORD _TM6 :1;\r
+ IO_WORD _TM5 :1;\r
+ IO_WORD _TM4 :1;\r
+ IO_WORD _TM3 :1;\r
+ IO_WORD _TM2 :1;\r
+ IO_WORD _TM1 :1;\r
+ IO_WORD _TM0 :1;\r
+ }bit;\r
+ }ITMK0STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _ENTB :1;\r
+ IO_BYTE _RAL :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _TM9 :1;\r
+ IO_BYTE _TM8 :1;\r
+ }bit;\r
+ }ITMKH0STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _TM7 :1;\r
+ IO_BYTE _TM6 :1;\r
+ IO_BYTE _TM5 :1;\r
+ IO_BYTE _TM4 :1;\r
+ IO_BYTE _TM3 :1;\r
+ IO_BYTE _TM2 :1;\r
+ IO_BYTE _TM1 :1;\r
+ IO_BYTE _TM0 :1;\r
+ }bit;\r
+ }ITMKL0STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _ENSB :1;\r
+ IO_BYTE _SM6 :1;\r
+ IO_BYTE _SM5 :1;\r
+ IO_BYTE _SM4 :1;\r
+ IO_BYTE _SM3 :1;\r
+ IO_BYTE _SM2 :1;\r
+ IO_BYTE _SM1 :1;\r
+ IO_BYTE _SM0 :1;\r
+ }bit;\r
+ }ISMK0STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE _SA6 :1;\r
+ IO_BYTE _SA5 :1;\r
+ IO_BYTE _SA4 :1;\r
+ IO_BYTE _SA3 :1;\r
+ IO_BYTE _SA2 :1;\r
+ IO_BYTE _SA1 :1;\r
+ IO_BYTE _SA0 :1;\r
+ }bit;\r
+ }ISBA0STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }IDAR0STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE _NSF :1;\r
+ IO_BYTE _EN :1;\r
+ IO_BYTE _CS4 :1;\r
+ IO_BYTE _CS3 :1;\r
+ IO_BYTE _CS2 :1;\r
+ IO_BYTE _CS1 :1;\r
+ IO_BYTE _CS0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CS :5;\r
+ }bitc;\r
+ }ICCR0STR;\r
+typedef union{ /* PPG Control 0-3 */\r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _TSEL33 :1;\r
+ IO_WORD _TSEL32 :1;\r
+ IO_WORD _TSEL31 :1;\r
+ IO_WORD _TSEL30 :1;\r
+ IO_WORD _TSEL23 :1;\r
+ IO_WORD _TSEL22 :1;\r
+ IO_WORD _TSEL21 :1;\r
+ IO_WORD _TSEL20 :1;\r
+ IO_WORD _TSEL13 :1;\r
+ IO_WORD _TSEL12 :1;\r
+ IO_WORD _TSEL11 :1;\r
+ IO_WORD _TSEL10 :1;\r
+ IO_WORD _TSEL03 :1;\r
+ IO_WORD _TSEL02 :1;\r
+ IO_WORD _TSEL01 :1;\r
+ IO_WORD _TSEL00 :1;\r
+ }bit;\r
+ }GCN10STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _EN3 :1;\r
+ IO_BYTE _EN2 :1;\r
+ IO_BYTE _EN1 :1;\r
+ IO_BYTE _EN0 :1;\r
+ }bit;\r
+ }GCN20STR;\r
+typedef union{ /* PPG Control 4-7 */\r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _TSEL33 :1;\r
+ IO_WORD _TSEL32 :1;\r
+ IO_WORD _TSEL31 :1;\r
+ IO_WORD _TSEL30 :1;\r
+ IO_WORD _TSEL23 :1;\r
+ IO_WORD _TSEL22 :1;\r
+ IO_WORD _TSEL21 :1;\r
+ IO_WORD _TSEL20 :1;\r
+ IO_WORD _TSEL13 :1;\r
+ IO_WORD _TSEL12 :1;\r
+ IO_WORD _TSEL11 :1;\r
+ IO_WORD _TSEL10 :1;\r
+ IO_WORD _TSEL03 :1;\r
+ IO_WORD _TSEL02 :1;\r
+ IO_WORD _TSEL01 :1;\r
+ IO_WORD _TSEL00 :1;\r
+ }bit;\r
+ }GCN11STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _EN3 :1;\r
+ IO_BYTE _EN2 :1;\r
+ IO_BYTE _EN1 :1;\r
+ IO_BYTE _EN0 :1;\r
+ }bit;\r
+ }GCN21STR;\r
+typedef union{ /* PPG Control 8-11 */\r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _TSEL33 :1;\r
+ IO_WORD _TSEL32 :1;\r
+ IO_WORD _TSEL31 :1;\r
+ IO_WORD _TSEL30 :1;\r
+ IO_WORD _TSEL23 :1;\r
+ IO_WORD _TSEL22 :1;\r
+ IO_WORD _TSEL21 :1;\r
+ IO_WORD _TSEL20 :1;\r
+ IO_WORD _TSEL13 :1;\r
+ IO_WORD _TSEL12 :1;\r
+ IO_WORD _TSEL11 :1;\r
+ IO_WORD _TSEL10 :1;\r
+ IO_WORD _TSEL03 :1;\r
+ IO_WORD _TSEL02 :1;\r
+ IO_WORD _TSEL01 :1;\r
+ IO_WORD _TSEL00 :1;\r
+ }bit;\r
+ }GCN12STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _EN3 :1;\r
+ IO_BYTE _EN2 :1;\r
+ IO_BYTE _EN1 :1;\r
+ IO_BYTE _EN0 :1;\r
+ }bit;\r
+ }GCN22STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _CNTE :1;\r
+ IO_WORD _STGR :1;\r
+ IO_WORD _MDSE :1;\r
+ IO_WORD _RTRG :1;\r
+ IO_WORD _CKS1 :1;\r
+ IO_WORD _CKS0 :1;\r
+ IO_WORD _PGMS :1;\r
+ IO_WORD :1;\r
+ IO_WORD _EGS1 :1;\r
+ IO_WORD _EGS0 :1;\r
+ IO_WORD _IREN :1;\r
+ IO_WORD _IRQF :1;\r
+ IO_WORD _IRS1 :1;\r
+ IO_WORD _IRS0 :1;\r
+ IO_WORD :1;\r
+ IO_WORD _OSEL :1;\r
+ }bit;\r
+ struct{\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CKS :2;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _EGS :2;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _IRS :2;\r
+ }bitc;\r
+ }PCN00STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _CNTE :1;\r
+ IO_BYTE _STGR :1;\r
+ IO_BYTE _MDSE :1;\r
+ IO_BYTE _RTRG :1;\r
+ IO_BYTE _CKS1 :1;\r
+ IO_BYTE _CKS0 :1;\r
+ IO_BYTE _PGMS :1;\r
+ IO_BYTE :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CKS :2;\r
+ }bitc;\r
+ }PCNH00STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _EGS1 :1;\r
+ IO_BYTE _EGS0 :1;\r
+ IO_BYTE _IREN :1;\r
+ IO_BYTE _IRQF :1;\r
+ IO_BYTE _IRS1 :1;\r
+ IO_BYTE _IRS0 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _OSEL :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE _EGS :2;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _IRS :2;\r
+ }bitc;\r
+ }PCNL00STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _CNTE :1;\r
+ IO_WORD _STGR :1;\r
+ IO_WORD _MDSE :1;\r
+ IO_WORD _RTRG :1;\r
+ IO_WORD _CKS1 :1;\r
+ IO_WORD _CKS0 :1;\r
+ IO_WORD _PGMS :1;\r
+ IO_WORD :1;\r
+ IO_WORD _EGS1 :1;\r
+ IO_WORD _EGS0 :1;\r
+ IO_WORD _IREN :1;\r
+ IO_WORD _IRQF :1;\r
+ IO_WORD _IRS1 :1;\r
+ IO_WORD _IRS0 :1;\r
+ IO_WORD :1;\r
+ IO_WORD _OSEL :1;\r
+ }bit;\r
+ struct{\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CKS :2;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _EGS :2;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _IRS :2;\r
+ }bitc;\r
+ }PCN01STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _CNTE :1;\r
+ IO_BYTE _STGR :1;\r
+ IO_BYTE _MDSE :1;\r
+ IO_BYTE _RTRG :1;\r
+ IO_BYTE _CKS1 :1;\r
+ IO_BYTE _CKS0 :1;\r
+ IO_BYTE _PGMS :1;\r
+ IO_BYTE :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CKS :2;\r
+ }bitc;\r
+ }PCNH01STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _EGS1 :1;\r
+ IO_BYTE _EGS0 :1;\r
+ IO_BYTE _IREN :1;\r
+ IO_BYTE _IRQF :1;\r
+ IO_BYTE _IRS1 :1;\r
+ IO_BYTE _IRS0 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _OSEL :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE _EGS :2;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _IRS :2;\r
+ }bitc;\r
+ }PCNL01STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _CNTE :1;\r
+ IO_WORD _STGR :1;\r
+ IO_WORD _MDSE :1;\r
+ IO_WORD _RTRG :1;\r
+ IO_WORD _CKS1 :1;\r
+ IO_WORD _CKS0 :1;\r
+ IO_WORD _PGMS :1;\r
+ IO_WORD :1;\r
+ IO_WORD _EGS1 :1;\r
+ IO_WORD _EGS0 :1;\r
+ IO_WORD _IREN :1;\r
+ IO_WORD _IRQF :1;\r
+ IO_WORD _IRS1 :1;\r
+ IO_WORD _IRS0 :1;\r
+ IO_WORD :1;\r
+ IO_WORD _OSEL :1;\r
+ }bit;\r
+ struct{\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CKS :2;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _EGS :2;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _IRS :2;\r
+ }bitc;\r
+ }PCN02STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _CNTE :1;\r
+ IO_BYTE _STGR :1;\r
+ IO_BYTE _MDSE :1;\r
+ IO_BYTE _RTRG :1;\r
+ IO_BYTE _CKS1 :1;\r
+ IO_BYTE _CKS0 :1;\r
+ IO_BYTE _PGMS :1;\r
+ IO_BYTE :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CKS :2;\r
+ }bitc;\r
+ }PCNH02STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _EGS1 :1;\r
+ IO_BYTE _EGS0 :1;\r
+ IO_BYTE _IREN :1;\r
+ IO_BYTE _IRQF :1;\r
+ IO_BYTE _IRS1 :1;\r
+ IO_BYTE _IRS0 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _OSEL :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE _EGS :2;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _IRS :2;\r
+ }bitc;\r
+ }PCNL02STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _CNTE :1;\r
+ IO_WORD _STGR :1;\r
+ IO_WORD _MDSE :1;\r
+ IO_WORD _RTRG :1;\r
+ IO_WORD _CKS1 :1;\r
+ IO_WORD _CKS0 :1;\r
+ IO_WORD _PGMS :1;\r
+ IO_WORD :1;\r
+ IO_WORD _EGS1 :1;\r
+ IO_WORD _EGS0 :1;\r
+ IO_WORD _IREN :1;\r
+ IO_WORD _IRQF :1;\r
+ IO_WORD _IRS1 :1;\r
+ IO_WORD _IRS0 :1;\r
+ IO_WORD :1;\r
+ IO_WORD _OSEL :1;\r
+ }bit;\r
+ struct{\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CKS :2;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _EGS :2;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _IRS :2;\r
+ }bitc;\r
+ }PCN03STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _CNTE :1;\r
+ IO_BYTE _STGR :1;\r
+ IO_BYTE _MDSE :1;\r
+ IO_BYTE _RTRG :1;\r
+ IO_BYTE _CKS1 :1;\r
+ IO_BYTE _CKS0 :1;\r
+ IO_BYTE _PGMS :1;\r
+ IO_BYTE :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CKS :2;\r
+ }bitc;\r
+ }PCNH03STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _EGS1 :1;\r
+ IO_BYTE _EGS0 :1;\r
+ IO_BYTE _IREN :1;\r
+ IO_BYTE _IRQF :1;\r
+ IO_BYTE _IRS1 :1;\r
+ IO_BYTE _IRS0 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _OSEL :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE _EGS :2;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _IRS :2;\r
+ }bitc;\r
+ }PCNL03STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _CNTE :1;\r
+ IO_WORD _STGR :1;\r
+ IO_WORD _MDSE :1;\r
+ IO_WORD _RTRG :1;\r
+ IO_WORD _CKS1 :1;\r
+ IO_WORD _CKS0 :1;\r
+ IO_WORD _PGMS :1;\r
+ IO_WORD :1;\r
+ IO_WORD _EGS1 :1;\r
+ IO_WORD _EGS0 :1;\r
+ IO_WORD _IREN :1;\r
+ IO_WORD _IRQF :1;\r
+ IO_WORD _IRS1 :1;\r
+ IO_WORD _IRS0 :1;\r
+ IO_WORD :1;\r
+ IO_WORD _OSEL :1;\r
+ }bit;\r
+ struct{\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CKS :2;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _EGS :2;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _IRS :2;\r
+ }bitc;\r
+ }PCN04STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _CNTE :1;\r
+ IO_BYTE _STGR :1;\r
+ IO_BYTE _MDSE :1;\r
+ IO_BYTE _RTRG :1;\r
+ IO_BYTE _CKS1 :1;\r
+ IO_BYTE _CKS0 :1;\r
+ IO_BYTE _PGMS :1;\r
+ IO_BYTE :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CKS :2;\r
+ }bitc;\r
+ }PCNH04STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _EGS1 :1;\r
+ IO_BYTE _EGS0 :1;\r
+ IO_BYTE _IREN :1;\r
+ IO_BYTE _IRQF :1;\r
+ IO_BYTE _IRS1 :1;\r
+ IO_BYTE _IRS0 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _OSEL :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE _EGS :2;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _IRS :2;\r
+ }bitc;\r
+ }PCNL04STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _CNTE :1;\r
+ IO_WORD _STGR :1;\r
+ IO_WORD _MDSE :1;\r
+ IO_WORD _RTRG :1;\r
+ IO_WORD _CKS1 :1;\r
+ IO_WORD _CKS0 :1;\r
+ IO_WORD _PGMS :1;\r
+ IO_WORD :1;\r
+ IO_WORD _EGS1 :1;\r
+ IO_WORD _EGS0 :1;\r
+ IO_WORD _IREN :1;\r
+ IO_WORD _IRQF :1;\r
+ IO_WORD _IRS1 :1;\r
+ IO_WORD _IRS0 :1;\r
+ IO_WORD :1;\r
+ IO_WORD _OSEL :1;\r
+ }bit;\r
+ struct{\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CKS :2;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _EGS :2;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _IRS :2;\r
+ }bitc;\r
+ }PCN05STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _CNTE :1;\r
+ IO_BYTE _STGR :1;\r
+ IO_BYTE _MDSE :1;\r
+ IO_BYTE _RTRG :1;\r
+ IO_BYTE _CKS1 :1;\r
+ IO_BYTE _CKS0 :1;\r
+ IO_BYTE _PGMS :1;\r
+ IO_BYTE :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CKS :2;\r
+ }bitc;\r
+ }PCNH05STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _EGS1 :1;\r
+ IO_BYTE _EGS0 :1;\r
+ IO_BYTE _IREN :1;\r
+ IO_BYTE _IRQF :1;\r
+ IO_BYTE _IRS1 :1;\r
+ IO_BYTE _IRS0 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _OSEL :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE _EGS :2;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _IRS :2;\r
+ }bitc;\r
+ }PCNL05STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _CNTE :1;\r
+ IO_WORD _STGR :1;\r
+ IO_WORD _MDSE :1;\r
+ IO_WORD _RTRG :1;\r
+ IO_WORD _CKS1 :1;\r
+ IO_WORD _CKS0 :1;\r
+ IO_WORD _PGMS :1;\r
+ IO_WORD :1;\r
+ IO_WORD _EGS1 :1;\r
+ IO_WORD _EGS0 :1;\r
+ IO_WORD _IREN :1;\r
+ IO_WORD _IRQF :1;\r
+ IO_WORD _IRS1 :1;\r
+ IO_WORD _IRS0 :1;\r
+ IO_WORD :1;\r
+ IO_WORD _OSEL :1;\r
+ }bit;\r
+ struct{\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CKS :2;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _EGS :2;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _IRS :2;\r
+ }bitc;\r
+ }PCN06STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _CNTE :1;\r
+ IO_BYTE _STGR :1;\r
+ IO_BYTE _MDSE :1;\r
+ IO_BYTE _RTRG :1;\r
+ IO_BYTE _CKS1 :1;\r
+ IO_BYTE _CKS0 :1;\r
+ IO_BYTE _PGMS :1;\r
+ IO_BYTE :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CKS :2;\r
+ }bitc;\r
+ }PCNH06STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _EGS1 :1;\r
+ IO_BYTE _EGS0 :1;\r
+ IO_BYTE _IREN :1;\r
+ IO_BYTE _IRQF :1;\r
+ IO_BYTE _IRS1 :1;\r
+ IO_BYTE _IRS0 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _OSEL :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE _EGS :2;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _IRS :2;\r
+ }bitc;\r
+ }PCNL06STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _CNTE :1;\r
+ IO_WORD _STGR :1;\r
+ IO_WORD _MDSE :1;\r
+ IO_WORD _RTRG :1;\r
+ IO_WORD _CKS1 :1;\r
+ IO_WORD _CKS0 :1;\r
+ IO_WORD _PGMS :1;\r
+ IO_WORD :1;\r
+ IO_WORD _EGS1 :1;\r
+ IO_WORD _EGS0 :1;\r
+ IO_WORD _IREN :1;\r
+ IO_WORD _IRQF :1;\r
+ IO_WORD _IRS1 :1;\r
+ IO_WORD _IRS0 :1;\r
+ IO_WORD :1;\r
+ IO_WORD _OSEL :1;\r
+ }bit;\r
+ struct{\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CKS :2;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _EGS :2;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _IRS :2;\r
+ }bitc;\r
+ }PCN07STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _CNTE :1;\r
+ IO_BYTE _STGR :1;\r
+ IO_BYTE _MDSE :1;\r
+ IO_BYTE _RTRG :1;\r
+ IO_BYTE _CKS1 :1;\r
+ IO_BYTE _CKS0 :1;\r
+ IO_BYTE _PGMS :1;\r
+ IO_BYTE :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CKS :2;\r
+ }bitc;\r
+ }PCNH07STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _EGS1 :1;\r
+ IO_BYTE _EGS0 :1;\r
+ IO_BYTE _IREN :1;\r
+ IO_BYTE _IRQF :1;\r
+ IO_BYTE _IRS1 :1;\r
+ IO_BYTE _IRS0 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _OSEL :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE _EGS :2;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _IRS :2;\r
+ }bitc;\r
+ }PCNL07STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _CNTE :1;\r
+ IO_WORD _STGR :1;\r
+ IO_WORD _MDSE :1;\r
+ IO_WORD _RTRG :1;\r
+ IO_WORD _CKS1 :1;\r
+ IO_WORD _CKS0 :1;\r
+ IO_WORD _PGMS :1;\r
+ IO_WORD :1;\r
+ IO_WORD _EGS1 :1;\r
+ IO_WORD _EGS0 :1;\r
+ IO_WORD _IREN :1;\r
+ IO_WORD _IRQF :1;\r
+ IO_WORD _IRS1 :1;\r
+ IO_WORD _IRS0 :1;\r
+ IO_WORD :1;\r
+ IO_WORD _OSEL :1;\r
+ }bit;\r
+ struct{\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CKS :2;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _EGS :2;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _IRS :2;\r
+ }bitc;\r
+ }PCN08STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _CNTE :1;\r
+ IO_BYTE _STGR :1;\r
+ IO_BYTE _MDSE :1;\r
+ IO_BYTE _RTRG :1;\r
+ IO_BYTE _CKS1 :1;\r
+ IO_BYTE _CKS0 :1;\r
+ IO_BYTE _PGMS :1;\r
+ IO_BYTE :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CKS :2;\r
+ }bitc;\r
+ }PCNH08STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _EGS1 :1;\r
+ IO_BYTE _EGS0 :1;\r
+ IO_BYTE _IREN :1;\r
+ IO_BYTE _IRQF :1;\r
+ IO_BYTE _IRS1 :1;\r
+ IO_BYTE _IRS0 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _OSEL :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE _EGS :2;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _IRS :2;\r
+ }bitc;\r
+ }PCNL08STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _CNTE :1;\r
+ IO_WORD _STGR :1;\r
+ IO_WORD _MDSE :1;\r
+ IO_WORD _RTRG :1;\r
+ IO_WORD _CKS1 :1;\r
+ IO_WORD _CKS0 :1;\r
+ IO_WORD _PGMS :1;\r
+ IO_WORD :1;\r
+ IO_WORD _EGS1 :1;\r
+ IO_WORD _EGS0 :1;\r
+ IO_WORD _IREN :1;\r
+ IO_WORD _IRQF :1;\r
+ IO_WORD _IRS1 :1;\r
+ IO_WORD _IRS0 :1;\r
+ IO_WORD :1;\r
+ IO_WORD _OSEL :1;\r
+ }bit;\r
+ struct{\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CKS :2;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _EGS :2;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _IRS :2;\r
+ }bitc;\r
+ }PCN09STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _CNTE :1;\r
+ IO_BYTE _STGR :1;\r
+ IO_BYTE _MDSE :1;\r
+ IO_BYTE _RTRG :1;\r
+ IO_BYTE _CKS1 :1;\r
+ IO_BYTE _CKS0 :1;\r
+ IO_BYTE _PGMS :1;\r
+ IO_BYTE :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CKS :2;\r
+ }bitc;\r
+ }PCNH09STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _EGS1 :1;\r
+ IO_BYTE _EGS0 :1;\r
+ IO_BYTE _IREN :1;\r
+ IO_BYTE _IRQF :1;\r
+ IO_BYTE _IRS1 :1;\r
+ IO_BYTE _IRS0 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _OSEL :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE _EGS :2;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _IRS :2;\r
+ }bitc;\r
+ }PCNL09STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _CNTE :1;\r
+ IO_WORD _STGR :1;\r
+ IO_WORD _MDSE :1;\r
+ IO_WORD _RTRG :1;\r
+ IO_WORD _CKS1 :1;\r
+ IO_WORD _CKS0 :1;\r
+ IO_WORD _PGMS :1;\r
+ IO_WORD :1;\r
+ IO_WORD _EGS1 :1;\r
+ IO_WORD _EGS0 :1;\r
+ IO_WORD _IREN :1;\r
+ IO_WORD _IRQF :1;\r
+ IO_WORD _IRS1 :1;\r
+ IO_WORD _IRS0 :1;\r
+ IO_WORD :1;\r
+ IO_WORD _OSEL :1;\r
+ }bit;\r
+ struct{\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CKS :2;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _EGS :2;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _IRS :2;\r
+ }bitc;\r
+ }PCN10STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _CNTE :1;\r
+ IO_BYTE _STGR :1;\r
+ IO_BYTE _MDSE :1;\r
+ IO_BYTE _RTRG :1;\r
+ IO_BYTE _CKS1 :1;\r
+ IO_BYTE _CKS0 :1;\r
+ IO_BYTE _PGMS :1;\r
+ IO_BYTE :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CKS :2;\r
+ }bitc;\r
+ }PCNH10STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _EGS1 :1;\r
+ IO_BYTE _EGS0 :1;\r
+ IO_BYTE _IREN :1;\r
+ IO_BYTE _IRQF :1;\r
+ IO_BYTE _IRS1 :1;\r
+ IO_BYTE _IRS0 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _OSEL :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE _EGS :2;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _IRS :2;\r
+ }bitc;\r
+ }PCNL10STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _CNTE :1;\r
+ IO_WORD _STGR :1;\r
+ IO_WORD _MDSE :1;\r
+ IO_WORD _RTRG :1;\r
+ IO_WORD _CKS1 :1;\r
+ IO_WORD _CKS0 :1;\r
+ IO_WORD _PGMS :1;\r
+ IO_WORD :1;\r
+ IO_WORD _EGS1 :1;\r
+ IO_WORD _EGS0 :1;\r
+ IO_WORD _IREN :1;\r
+ IO_WORD _IRQF :1;\r
+ IO_WORD _IRS1 :1;\r
+ IO_WORD _IRS0 :1;\r
+ IO_WORD :1;\r
+ IO_WORD _OSEL :1;\r
+ }bit;\r
+ struct{\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CKS :2;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _EGS :2;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _IRS :2;\r
+ }bitc;\r
+ }PCN11STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _CNTE :1;\r
+ IO_BYTE _STGR :1;\r
+ IO_BYTE _MDSE :1;\r
+ IO_BYTE _RTRG :1;\r
+ IO_BYTE _CKS1 :1;\r
+ IO_BYTE _CKS0 :1;\r
+ IO_BYTE _PGMS :1;\r
+ IO_BYTE :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CKS :2;\r
+ }bitc;\r
+ }PCNH11STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _EGS1 :1;\r
+ IO_BYTE _EGS0 :1;\r
+ IO_BYTE _IREN :1;\r
+ IO_BYTE _IRQF :1;\r
+ IO_BYTE _IRS1 :1;\r
+ IO_BYTE _IRS0 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _OSEL :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE _EGS :2;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _IRS :2;\r
+ }bitc;\r
+ }PCNL11STR;\r
+typedef union{ /* Input Capture 0-3 */\r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _ICP1 :1;\r
+ IO_BYTE _ICP0 :1;\r
+ IO_BYTE _ICE1 :1;\r
+ IO_BYTE _ICE0 :1;\r
+ IO_BYTE _EG11 :1;\r
+ IO_BYTE _EG10 :1;\r
+ IO_BYTE _EG01 :1;\r
+ IO_BYTE _EG00 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _EG1 :2;\r
+ IO_BYTE _EG0 :2;\r
+ }bitc;\r
+ }ICS01STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _ICP3 :1;\r
+ IO_BYTE _ICP2 :1;\r
+ IO_BYTE _ICE3 :1;\r
+ IO_BYTE _ICE2 :1;\r
+ IO_BYTE _EG31 :1;\r
+ IO_BYTE _EG30 :1;\r
+ IO_BYTE _EG21 :1;\r
+ IO_BYTE _EG20 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _EG3 :2;\r
+ IO_BYTE _EG2 :2;\r
+ }bitc;\r
+ }ICS23STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _CP15 :1;\r
+ IO_WORD _CP14 :1;\r
+ IO_WORD _CP13 :1;\r
+ IO_WORD _CP12 :1;\r
+ IO_WORD _CP11 :1;\r
+ IO_WORD _CP10 :1;\r
+ IO_WORD _CP9 :1;\r
+ IO_WORD _CP8 :1;\r
+ IO_WORD _CP7 :1;\r
+ IO_WORD _CP6 :1;\r
+ IO_WORD _CP5 :1;\r
+ IO_WORD _CP4 :1;\r
+ IO_WORD _CP3 :1;\r
+ IO_WORD _CP2 :1;\r
+ IO_WORD _CP1 :1;\r
+ IO_WORD _CP0 :1;\r
+ }bit;\r
+ }IPCP0STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _CP15 :1;\r
+ IO_WORD _CP14 :1;\r
+ IO_WORD _CP13 :1;\r
+ IO_WORD _CP12 :1;\r
+ IO_WORD _CP11 :1;\r
+ IO_WORD _CP10 :1;\r
+ IO_WORD _CP9 :1;\r
+ IO_WORD _CP8 :1;\r
+ IO_WORD _CP7 :1;\r
+ IO_WORD _CP6 :1;\r
+ IO_WORD _CP5 :1;\r
+ IO_WORD _CP4 :1;\r
+ IO_WORD _CP3 :1;\r
+ IO_WORD _CP2 :1;\r
+ IO_WORD _CP1 :1;\r
+ IO_WORD _CP0 :1;\r
+ }bit;\r
+ }IPCP1STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _CP15 :1;\r
+ IO_WORD _CP14 :1;\r
+ IO_WORD _CP13 :1;\r
+ IO_WORD _CP12 :1;\r
+ IO_WORD _CP11 :1;\r
+ IO_WORD _CP10 :1;\r
+ IO_WORD _CP9 :1;\r
+ IO_WORD _CP8 :1;\r
+ IO_WORD _CP7 :1;\r
+ IO_WORD _CP6 :1;\r
+ IO_WORD _CP5 :1;\r
+ IO_WORD _CP4 :1;\r
+ IO_WORD _CP3 :1;\r
+ IO_WORD _CP2 :1;\r
+ IO_WORD _CP1 :1;\r
+ IO_WORD _CP0 :1;\r
+ }bit;\r
+ }IPCP2STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _CP15 :1;\r
+ IO_WORD _CP14 :1;\r
+ IO_WORD _CP13 :1;\r
+ IO_WORD _CP12 :1;\r
+ IO_WORD _CP11 :1;\r
+ IO_WORD _CP10 :1;\r
+ IO_WORD _CP9 :1;\r
+ IO_WORD _CP8 :1;\r
+ IO_WORD _CP7 :1;\r
+ IO_WORD _CP6 :1;\r
+ IO_WORD _CP5 :1;\r
+ IO_WORD _CP4 :1;\r
+ IO_WORD _CP3 :1;\r
+ IO_WORD _CP2 :1;\r
+ IO_WORD _CP1 :1;\r
+ IO_WORD _CP0 :1;\r
+ }bit;\r
+ }IPCP3STR;\r
+typedef union{ /* Output Compare 0-3 */\r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CMOD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _OTD1 :1;\r
+ IO_WORD _OTD0 :1;\r
+ IO_WORD _ICP1 :1;\r
+ IO_WORD _ICP0 :1;\r
+ IO_WORD _ICE1 :1;\r
+ IO_WORD _ICE0 :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CST1 :1;\r
+ IO_WORD _CST0 :1;\r
+ }bit;\r
+ }OCS01STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CMOD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _OTD3 :1;\r
+ IO_WORD _OTD2 :1;\r
+ IO_WORD _ICP3 :1;\r
+ IO_WORD _ICP2 :1;\r
+ IO_WORD _ICE3 :1;\r
+ IO_WORD _ICE2 :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CST3 :1;\r
+ IO_WORD _CST2 :1;\r
+ }bit;\r
+ }OCS23STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _C15 :1;\r
+ IO_WORD _C14 :1;\r
+ IO_WORD _C13 :1;\r
+ IO_WORD _C12 :1;\r
+ IO_WORD _C11 :1;\r
+ IO_WORD _C10 :1;\r
+ IO_WORD _C9 :1;\r
+ IO_WORD _C8 :1;\r
+ IO_WORD _C7 :1;\r
+ IO_WORD _C6 :1;\r
+ IO_WORD _C5 :1;\r
+ IO_WORD _C4 :1;\r
+ IO_WORD _C3 :1;\r
+ IO_WORD _C2 :1;\r
+ IO_WORD _C1 :1;\r
+ IO_WORD _C0 :1;\r
+ }bit;\r
+ }OCCP0STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _C15 :1;\r
+ IO_WORD _C14 :1;\r
+ IO_WORD _C13 :1;\r
+ IO_WORD _C12 :1;\r
+ IO_WORD _C11 :1;\r
+ IO_WORD _C10 :1;\r
+ IO_WORD _C9 :1;\r
+ IO_WORD _C8 :1;\r
+ IO_WORD _C7 :1;\r
+ IO_WORD _C6 :1;\r
+ IO_WORD _C5 :1;\r
+ IO_WORD _C4 :1;\r
+ IO_WORD _C3 :1;\r
+ IO_WORD _C2 :1;\r
+ IO_WORD _C1 :1;\r
+ IO_WORD _C0 :1;\r
+ }bit;\r
+ }OCCP1STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _C15 :1;\r
+ IO_WORD _C14 :1;\r
+ IO_WORD _C13 :1;\r
+ IO_WORD _C12 :1;\r
+ IO_WORD _C11 :1;\r
+ IO_WORD _C10 :1;\r
+ IO_WORD _C9 :1;\r
+ IO_WORD _C8 :1;\r
+ IO_WORD _C7 :1;\r
+ IO_WORD _C6 :1;\r
+ IO_WORD _C5 :1;\r
+ IO_WORD _C4 :1;\r
+ IO_WORD _C3 :1;\r
+ IO_WORD _C2 :1;\r
+ IO_WORD _C1 :1;\r
+ IO_WORD _C0 :1;\r
+ }bit;\r
+ }OCCP2STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _C15 :1;\r
+ IO_WORD _C14 :1;\r
+ IO_WORD _C13 :1;\r
+ IO_WORD _C12 :1;\r
+ IO_WORD _C11 :1;\r
+ IO_WORD _C10 :1;\r
+ IO_WORD _C9 :1;\r
+ IO_WORD _C8 :1;\r
+ IO_WORD _C7 :1;\r
+ IO_WORD _C6 :1;\r
+ IO_WORD _C5 :1;\r
+ IO_WORD _C4 :1;\r
+ IO_WORD _C3 :1;\r
+ IO_WORD _C2 :1;\r
+ IO_WORD _C1 :1;\r
+ IO_WORD _C0 :1;\r
+ }bit;\r
+ }OCCP3STR;\r
+typedef union{ /* ADC */\r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _ADE31 :1;\r
+ IO_WORD _ADE30 :1;\r
+ IO_WORD _ADE29 :1;\r
+ IO_WORD _ADE28 :1;\r
+ IO_WORD _ADE27 :1;\r
+ IO_WORD _ADE26 :1;\r
+ IO_WORD _ADE25 :1;\r
+ IO_WORD _ADE24 :1;\r
+ IO_WORD _ADE23 :1;\r
+ IO_WORD _ADE22 :1;\r
+ IO_WORD _ADE21 :1;\r
+ IO_WORD _ADE20 :1;\r
+ IO_WORD _ADE19 :1;\r
+ IO_WORD _ADE18 :1;\r
+ IO_WORD _ADE17 :1;\r
+ IO_WORD _ADE16 :1;\r
+ }bit;\r
+ }ADERHSTR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _ADE15 :1;\r
+ IO_WORD _ADE14 :1;\r
+ IO_WORD _ADE13 :1;\r
+ IO_WORD _ADE12 :1;\r
+ IO_WORD _ADE11 :1;\r
+ IO_WORD _ADE10 :1;\r
+ IO_WORD _ADE9 :1;\r
+ IO_WORD _ADE8 :1;\r
+ IO_WORD _ADE7 :1;\r
+ IO_WORD _ADE6 :1;\r
+ IO_WORD _ADE5 :1;\r
+ IO_WORD _ADE4 :1;\r
+ IO_WORD _ADE3 :1;\r
+ IO_WORD _ADE2 :1;\r
+ IO_WORD _ADE1 :1;\r
+ IO_WORD _ADE0 :1;\r
+ }bit;\r
+ }ADERLSTR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _BUSY :1;\r
+ IO_BYTE _INT :1;\r
+ IO_BYTE _INTE :1;\r
+ IO_BYTE _PAUS :1;\r
+ IO_BYTE _STS1 :1;\r
+ IO_BYTE _STS0 :1;\r
+ IO_BYTE _STRT :1;\r
+ IO_BYTE :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _STS :2;\r
+ }bitc;\r
+ }ADCS1STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _MD1 :1;\r
+ IO_BYTE _MD0 :1;\r
+ IO_BYTE _S10 :1;\r
+ IO_BYTE _ACH4 :1;\r
+ IO_BYTE _ACH3 :1;\r
+ IO_BYTE _ACH2 :1;\r
+ IO_BYTE _ACH1 :1;\r
+ IO_BYTE _ACH0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE _MD :2;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ACH :5;\r
+ }bitc;\r
+ }ADCS0STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D9 :1;\r
+ IO_BYTE _D8 :1;\r
+ }bit;\r
+ }ADCR1STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }ADCR0STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _CT5 :1;\r
+ IO_BYTE _CT4 :1;\r
+ IO_BYTE _CT3 :1;\r
+ IO_BYTE _CT2 :1;\r
+ IO_BYTE _CT1 :1;\r
+ IO_BYTE _CT0 :1;\r
+ IO_BYTE _ST9 :1;\r
+ IO_BYTE _ST8 :1;\r
+ }bit;\r
+ }ADCT1STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _ST7 :1;\r
+ IO_BYTE _ST6 :1;\r
+ IO_BYTE _ST5 :1;\r
+ IO_BYTE _ST4 :1;\r
+ IO_BYTE _ST3 :1;\r
+ IO_BYTE _ST2 :1;\r
+ IO_BYTE _ST1 :1;\r
+ IO_BYTE _ST0 :1;\r
+ }bit;\r
+ }ADCT0STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ANS4 :1;\r
+ IO_BYTE _ANS3 :1;\r
+ IO_BYTE _ANS2 :1;\r
+ IO_BYTE _ANS1 :1;\r
+ IO_BYTE _ASN0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ANS :5;\r
+ }bitc;\r
+ }ADSCHSTR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ANE4 :1;\r
+ IO_BYTE _ANE3 :1;\r
+ IO_BYTE _ANE2 :1;\r
+ IO_BYTE _ANE1 :1;\r
+ IO_BYTE _ANE0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ANE :5;\r
+ }bitc;\r
+ }ADECHSTR;\r
+typedef union{ /* Reload Timer 0 */\r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _D15 :1;\r
+ IO_WORD _D14 :1;\r
+ IO_WORD _D13 :1;\r
+ IO_WORD _D12 :1;\r
+ IO_WORD _D11 :1;\r
+ IO_WORD _D10 :1;\r
+ IO_WORD _D9 :1;\r
+ IO_WORD _D8 :1;\r
+ IO_WORD _D7 :1;\r
+ IO_WORD _D6 :1;\r
+ IO_WORD _D5 :1;\r
+ IO_WORD _D4 :1;\r
+ IO_WORD _D3 :1;\r
+ IO_WORD _D2 :1;\r
+ IO_WORD _D1 :1;\r
+ IO_WORD _D0 :1;\r
+ }bit;\r
+ }TMRLR0STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _D15 :1;\r
+ IO_WORD _D14 :1;\r
+ IO_WORD _D13 :1;\r
+ IO_WORD _D12 :1;\r
+ IO_WORD _D11 :1;\r
+ IO_WORD _D10 :1;\r
+ IO_WORD _D9 :1;\r
+ IO_WORD _D8 :1;\r
+ IO_WORD _D7 :1;\r
+ IO_WORD _D6 :1;\r
+ IO_WORD _D5 :1;\r
+ IO_WORD _D4 :1;\r
+ IO_WORD _D3 :1;\r
+ IO_WORD _D2 :1;\r
+ IO_WORD _D1 :1;\r
+ IO_WORD _D0 :1;\r
+ }bit;\r
+ }TMR0STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CSL2 :1;\r
+ IO_WORD _CSL1 :1;\r
+ IO_WORD _CSL0 :1;\r
+ IO_WORD _MOD2 :1;\r
+ IO_WORD _MOD1 :1;\r
+ IO_WORD _MOD0 :1;\r
+ IO_WORD :1;\r
+ IO_WORD _OULT :1;\r
+ IO_WORD _RELD :1;\r
+ IO_WORD _INTE :1;\r
+ IO_WORD _UF :1;\r
+ IO_WORD _CNTE :1;\r
+ IO_WORD _TRG :1;\r
+ }bit;\r
+ struct{\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CSL :3;\r
+ IO_WORD _MOD :3;\r
+ }bitc;\r
+ }TMCSR0STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CSL2 :1;\r
+ IO_BYTE _CSL1 :1;\r
+ IO_BYTE _CSL0 :1;\r
+ IO_BYTE _MOD2 :1;\r
+ IO_BYTE _MOD1 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :3;\r
+ IO_BYTE _CSL :3;\r
+ }bitc;\r
+ }TMCSRH0STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _MOD0 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _OULT :1;\r
+ IO_BYTE _RELD :1;\r
+ IO_BYTE _INTE :1;\r
+ IO_BYTE _UF :1;\r
+ IO_BYTE _CNTE :1;\r
+ IO_BYTE _TRG :1;\r
+ }bit;\r
+ }TMCSRL0STR;\r
+typedef union{ /* Reload Timer 1 */\r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _D15 :1;\r
+ IO_WORD _D14 :1;\r
+ IO_WORD _D13 :1;\r
+ IO_WORD _D12 :1;\r
+ IO_WORD _D11 :1;\r
+ IO_WORD _D10 :1;\r
+ IO_WORD _D9 :1;\r
+ IO_WORD _D8 :1;\r
+ IO_WORD _D7 :1;\r
+ IO_WORD _D6 :1;\r
+ IO_WORD _D5 :1;\r
+ IO_WORD _D4 :1;\r
+ IO_WORD _D3 :1;\r
+ IO_WORD _D2 :1;\r
+ IO_WORD _D1 :1;\r
+ IO_WORD _D0 :1;\r
+ }bit;\r
+ }TMRLR1STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _D15 :1;\r
+ IO_WORD _D14 :1;\r
+ IO_WORD _D13 :1;\r
+ IO_WORD _D12 :1;\r
+ IO_WORD _D11 :1;\r
+ IO_WORD _D10 :1;\r
+ IO_WORD _D9 :1;\r
+ IO_WORD _D8 :1;\r
+ IO_WORD _D7 :1;\r
+ IO_WORD _D6 :1;\r
+ IO_WORD _D5 :1;\r
+ IO_WORD _D4 :1;\r
+ IO_WORD _D3 :1;\r
+ IO_WORD _D2 :1;\r
+ IO_WORD _D1 :1;\r
+ IO_WORD _D0 :1;\r
+ }bit;\r
+ }TMR1STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CSL2 :1;\r
+ IO_WORD _CSL1 :1;\r
+ IO_WORD _CSL0 :1;\r
+ IO_WORD _MOD2 :1;\r
+ IO_WORD _MOD1 :1;\r
+ IO_WORD _MOD0 :1;\r
+ IO_WORD :1;\r
+ IO_WORD _OULT :1;\r
+ IO_WORD _RELD :1;\r
+ IO_WORD _INTE :1;\r
+ IO_WORD _UF :1;\r
+ IO_WORD _CNTE :1;\r
+ IO_WORD _TRG :1;\r
+ }bit;\r
+ struct{\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CSL :3;\r
+ IO_WORD _MOD :3;\r
+ }bitc;\r
+ }TMCSR1STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CSL2 :1;\r
+ IO_BYTE _CSL1 :1;\r
+ IO_BYTE _CSL0 :1;\r
+ IO_BYTE _MOD2 :1;\r
+ IO_BYTE _MOD1 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :3;\r
+ IO_BYTE _CSL :3;\r
+ }bitc;\r
+ }TMCSRH1STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _MOD0 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _OULT :1;\r
+ IO_BYTE _RELD :1;\r
+ IO_BYTE _INTE :1;\r
+ IO_BYTE _UF :1;\r
+ IO_BYTE _CNTE :1;\r
+ IO_BYTE _TRG :1;\r
+ }bit;\r
+ }TMCSRL1STR;\r
+typedef union{ /* Reload Timer 2 */\r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _D15 :1;\r
+ IO_WORD _D14 :1;\r
+ IO_WORD _D13 :1;\r
+ IO_WORD _D12 :1;\r
+ IO_WORD _D11 :1;\r
+ IO_WORD _D10 :1;\r
+ IO_WORD _D9 :1;\r
+ IO_WORD _D8 :1;\r
+ IO_WORD _D7 :1;\r
+ IO_WORD _D6 :1;\r
+ IO_WORD _D5 :1;\r
+ IO_WORD _D4 :1;\r
+ IO_WORD _D3 :1;\r
+ IO_WORD _D2 :1;\r
+ IO_WORD _D1 :1;\r
+ IO_WORD _D0 :1;\r
+ }bit;\r
+ }TMRLR2STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _D15 :1;\r
+ IO_WORD _D14 :1;\r
+ IO_WORD _D13 :1;\r
+ IO_WORD _D12 :1;\r
+ IO_WORD _D11 :1;\r
+ IO_WORD _D10 :1;\r
+ IO_WORD _D9 :1;\r
+ IO_WORD _D8 :1;\r
+ IO_WORD _D7 :1;\r
+ IO_WORD _D6 :1;\r
+ IO_WORD _D5 :1;\r
+ IO_WORD _D4 :1;\r
+ IO_WORD _D3 :1;\r
+ IO_WORD _D2 :1;\r
+ IO_WORD _D1 :1;\r
+ IO_WORD _D0 :1;\r
+ }bit;\r
+ }TMR2STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CSL2 :1;\r
+ IO_WORD _CSL1 :1;\r
+ IO_WORD _CSL0 :1;\r
+ IO_WORD _MOD2 :1;\r
+ IO_WORD _MOD1 :1;\r
+ IO_WORD _MOD0 :1;\r
+ IO_WORD :1;\r
+ IO_WORD _OULT :1;\r
+ IO_WORD _RELD :1;\r
+ IO_WORD _INTE :1;\r
+ IO_WORD _UF :1;\r
+ IO_WORD _CNTE :1;\r
+ IO_WORD _TRG :1;\r
+ }bit;\r
+ struct{\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CSL :3;\r
+ IO_WORD _MOD :3;\r
+ }bitc;\r
+ }TMCSR2STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CSL2 :1;\r
+ IO_BYTE _CSL1 :1;\r
+ IO_BYTE _CSL0 :1;\r
+ IO_BYTE _MOD2 :1;\r
+ IO_BYTE _MOD1 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :3;\r
+ IO_BYTE _CSL :3;\r
+ }bitc;\r
+ }TMCSRH2STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _MOD0 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _OULT :1;\r
+ IO_BYTE _RELD :1;\r
+ IO_BYTE _INTE :1;\r
+ IO_BYTE _UF :1;\r
+ IO_BYTE _CNTE :1;\r
+ IO_BYTE _TRG :1;\r
+ }bit;\r
+ }TMCSRL2STR;\r
+typedef union{ /* Reload Timer 3 */\r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _D15 :1;\r
+ IO_WORD _D14 :1;\r
+ IO_WORD _D13 :1;\r
+ IO_WORD _D12 :1;\r
+ IO_WORD _D11 :1;\r
+ IO_WORD _D10 :1;\r
+ IO_WORD _D9 :1;\r
+ IO_WORD _D8 :1;\r
+ IO_WORD _D7 :1;\r
+ IO_WORD _D6 :1;\r
+ IO_WORD _D5 :1;\r
+ IO_WORD _D4 :1;\r
+ IO_WORD _D3 :1;\r
+ IO_WORD _D2 :1;\r
+ IO_WORD _D1 :1;\r
+ IO_WORD _D0 :1;\r
+ }bit;\r
+ }TMRLR3STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _D15 :1;\r
+ IO_WORD _D14 :1;\r
+ IO_WORD _D13 :1;\r
+ IO_WORD _D12 :1;\r
+ IO_WORD _D11 :1;\r
+ IO_WORD _D10 :1;\r
+ IO_WORD _D9 :1;\r
+ IO_WORD _D8 :1;\r
+ IO_WORD _D7 :1;\r
+ IO_WORD _D6 :1;\r
+ IO_WORD _D5 :1;\r
+ IO_WORD _D4 :1;\r
+ IO_WORD _D3 :1;\r
+ IO_WORD _D2 :1;\r
+ IO_WORD _D1 :1;\r
+ IO_WORD _D0 :1;\r
+ }bit;\r
+ }TMR3STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CSL2 :1;\r
+ IO_WORD _CSL1 :1;\r
+ IO_WORD _CSL0 :1;\r
+ IO_WORD _MOD2 :1;\r
+ IO_WORD _MOD1 :1;\r
+ IO_WORD _MOD0 :1;\r
+ IO_WORD :1;\r
+ IO_WORD _OULT :1;\r
+ IO_WORD _RELD :1;\r
+ IO_WORD _INTE :1;\r
+ IO_WORD _UF :1;\r
+ IO_WORD _CNTE :1;\r
+ IO_WORD _TRG :1;\r
+ }bit;\r
+ struct{\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CSL :3;\r
+ IO_WORD _MOD :3;\r
+ }bitc;\r
+ }TMCSR3STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CSL2 :1;\r
+ IO_BYTE _CSL1 :1;\r
+ IO_BYTE _CSL0 :1;\r
+ IO_BYTE _MOD2 :1;\r
+ IO_BYTE _MOD1 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :3;\r
+ IO_BYTE _CSL :3;\r
+ }bitc;\r
+ }TMCSRH3STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _MOD0 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _OULT :1;\r
+ IO_BYTE _RELD :1;\r
+ IO_BYTE _INTE :1;\r
+ IO_BYTE _UF :1;\r
+ IO_BYTE _CNTE :1;\r
+ IO_BYTE _TRG :1;\r
+ }bit;\r
+ }TMCSRL3STR;\r
+typedef union{ /* Reload Timer 4 */\r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _D15 :1;\r
+ IO_WORD _D14 :1;\r
+ IO_WORD _D13 :1;\r
+ IO_WORD _D12 :1;\r
+ IO_WORD _D11 :1;\r
+ IO_WORD _D10 :1;\r
+ IO_WORD _D9 :1;\r
+ IO_WORD _D8 :1;\r
+ IO_WORD _D7 :1;\r
+ IO_WORD _D6 :1;\r
+ IO_WORD _D5 :1;\r
+ IO_WORD _D4 :1;\r
+ IO_WORD _D3 :1;\r
+ IO_WORD _D2 :1;\r
+ IO_WORD _D1 :1;\r
+ IO_WORD _D0 :1;\r
+ }bit;\r
+ }TMRLR4STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _D15 :1;\r
+ IO_WORD _D14 :1;\r
+ IO_WORD _D13 :1;\r
+ IO_WORD _D12 :1;\r
+ IO_WORD _D11 :1;\r
+ IO_WORD _D10 :1;\r
+ IO_WORD _D9 :1;\r
+ IO_WORD _D8 :1;\r
+ IO_WORD _D7 :1;\r
+ IO_WORD _D6 :1;\r
+ IO_WORD _D5 :1;\r
+ IO_WORD _D4 :1;\r
+ IO_WORD _D3 :1;\r
+ IO_WORD _D2 :1;\r
+ IO_WORD _D1 :1;\r
+ IO_WORD _D0 :1;\r
+ }bit;\r
+ }TMR4STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CSL2 :1;\r
+ IO_WORD _CSL1 :1;\r
+ IO_WORD _CSL0 :1;\r
+ IO_WORD _MOD2 :1;\r
+ IO_WORD _MOD1 :1;\r
+ IO_WORD _MOD0 :1;\r
+ IO_WORD :1;\r
+ IO_WORD _OULT :1;\r
+ IO_WORD _RELD :1;\r
+ IO_WORD _INTE :1;\r
+ IO_WORD _UF :1;\r
+ IO_WORD _CNTE :1;\r
+ IO_WORD _TRG :1;\r
+ }bit;\r
+ struct{\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CSL :3;\r
+ IO_WORD _MOD :3;\r
+ }bitc;\r
+ }TMCSR4STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CSL2 :1;\r
+ IO_BYTE _CSL1 :1;\r
+ IO_BYTE _CSL0 :1;\r
+ IO_BYTE _MOD2 :1;\r
+ IO_BYTE _MOD1 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :3;\r
+ IO_BYTE _CSL :3;\r
+ }bitc;\r
+ }TMCSRH4STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _MOD0 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _OULT :1;\r
+ IO_BYTE _RELD :1;\r
+ IO_BYTE _INTE :1;\r
+ IO_BYTE _UF :1;\r
+ IO_BYTE _CNTE :1;\r
+ IO_BYTE _TRG :1;\r
+ }bit;\r
+ }TMCSRL4STR;\r
+typedef union{ /* Reload Timer 5 */\r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _D15 :1;\r
+ IO_WORD _D14 :1;\r
+ IO_WORD _D13 :1;\r
+ IO_WORD _D12 :1;\r
+ IO_WORD _D11 :1;\r
+ IO_WORD _D10 :1;\r
+ IO_WORD _D9 :1;\r
+ IO_WORD _D8 :1;\r
+ IO_WORD _D7 :1;\r
+ IO_WORD _D6 :1;\r
+ IO_WORD _D5 :1;\r
+ IO_WORD _D4 :1;\r
+ IO_WORD _D3 :1;\r
+ IO_WORD _D2 :1;\r
+ IO_WORD _D1 :1;\r
+ IO_WORD _D0 :1;\r
+ }bit;\r
+ }TMRLR5STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _D15 :1;\r
+ IO_WORD _D14 :1;\r
+ IO_WORD _D13 :1;\r
+ IO_WORD _D12 :1;\r
+ IO_WORD _D11 :1;\r
+ IO_WORD _D10 :1;\r
+ IO_WORD _D9 :1;\r
+ IO_WORD _D8 :1;\r
+ IO_WORD _D7 :1;\r
+ IO_WORD _D6 :1;\r
+ IO_WORD _D5 :1;\r
+ IO_WORD _D4 :1;\r
+ IO_WORD _D3 :1;\r
+ IO_WORD _D2 :1;\r
+ IO_WORD _D1 :1;\r
+ IO_WORD _D0 :1;\r
+ }bit;\r
+ }TMR5STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CSL2 :1;\r
+ IO_WORD _CSL1 :1;\r
+ IO_WORD _CSL0 :1;\r
+ IO_WORD _MOD2 :1;\r
+ IO_WORD _MOD1 :1;\r
+ IO_WORD _MOD0 :1;\r
+ IO_WORD :1;\r
+ IO_WORD _OULT :1;\r
+ IO_WORD _RELD :1;\r
+ IO_WORD _INTE :1;\r
+ IO_WORD _UF :1;\r
+ IO_WORD _CNTE :1;\r
+ IO_WORD _TRG :1;\r
+ }bit;\r
+ struct{\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CSL :3;\r
+ IO_WORD _MOD :3;\r
+ }bitc;\r
+ }TMCSR5STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CSL2 :1;\r
+ IO_BYTE _CSL1 :1;\r
+ IO_BYTE _CSL0 :1;\r
+ IO_BYTE _MOD2 :1;\r
+ IO_BYTE _MOD1 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :3;\r
+ IO_BYTE _CSL :3;\r
+ }bitc;\r
+ }TMCSRH5STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _MOD0 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _OULT :1;\r
+ IO_BYTE _RELD :1;\r
+ IO_BYTE _INTE :1;\r
+ IO_BYTE _UF :1;\r
+ IO_BYTE _CNTE :1;\r
+ IO_BYTE _TRG :1;\r
+ }bit;\r
+ }TMCSRL5STR;\r
+typedef union{ /* Reload Timer 6 */\r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _D15 :1;\r
+ IO_WORD _D14 :1;\r
+ IO_WORD _D13 :1;\r
+ IO_WORD _D12 :1;\r
+ IO_WORD _D11 :1;\r
+ IO_WORD _D10 :1;\r
+ IO_WORD _D9 :1;\r
+ IO_WORD _D8 :1;\r
+ IO_WORD _D7 :1;\r
+ IO_WORD _D6 :1;\r
+ IO_WORD _D5 :1;\r
+ IO_WORD _D4 :1;\r
+ IO_WORD _D3 :1;\r
+ IO_WORD _D2 :1;\r
+ IO_WORD _D1 :1;\r
+ IO_WORD _D0 :1;\r
+ }bit;\r
+ }TMRLR6STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _D15 :1;\r
+ IO_WORD _D14 :1;\r
+ IO_WORD _D13 :1;\r
+ IO_WORD _D12 :1;\r
+ IO_WORD _D11 :1;\r
+ IO_WORD _D10 :1;\r
+ IO_WORD _D9 :1;\r
+ IO_WORD _D8 :1;\r
+ IO_WORD _D7 :1;\r
+ IO_WORD _D6 :1;\r
+ IO_WORD _D5 :1;\r
+ IO_WORD _D4 :1;\r
+ IO_WORD _D3 :1;\r
+ IO_WORD _D2 :1;\r
+ IO_WORD _D1 :1;\r
+ IO_WORD _D0 :1;\r
+ }bit;\r
+ }TMR6STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CSL2 :1;\r
+ IO_WORD _CSL1 :1;\r
+ IO_WORD _CSL0 :1;\r
+ IO_WORD _MOD2 :1;\r
+ IO_WORD _MOD1 :1;\r
+ IO_WORD _MOD0 :1;\r
+ IO_WORD :1;\r
+ IO_WORD _OULT :1;\r
+ IO_WORD _RELD :1;\r
+ IO_WORD _INTE :1;\r
+ IO_WORD _UF :1;\r
+ IO_WORD _CNTE :1;\r
+ IO_WORD _TRG :1;\r
+ }bit;\r
+ struct{\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CSL :3;\r
+ IO_WORD _MOD :3;\r
+ }bitc;\r
+ }TMCSR6STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CSL2 :1;\r
+ IO_BYTE _CSL1 :1;\r
+ IO_BYTE _CSL0 :1;\r
+ IO_BYTE _MOD2 :1;\r
+ IO_BYTE _MOD1 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :3;\r
+ IO_BYTE _CSL :3;\r
+ }bitc;\r
+ }TMCSRH6STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _MOD0 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _OULT :1;\r
+ IO_BYTE _RELD :1;\r
+ IO_BYTE _INTE :1;\r
+ IO_BYTE _UF :1;\r
+ IO_BYTE _CNTE :1;\r
+ IO_BYTE _TRG :1;\r
+ }bit;\r
+ }TMCSRL6STR;\r
+typedef union{ /* Reload Timer 7 */\r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _D15 :1;\r
+ IO_WORD _D14 :1;\r
+ IO_WORD _D13 :1;\r
+ IO_WORD _D12 :1;\r
+ IO_WORD _D11 :1;\r
+ IO_WORD _D10 :1;\r
+ IO_WORD _D9 :1;\r
+ IO_WORD _D8 :1;\r
+ IO_WORD _D7 :1;\r
+ IO_WORD _D6 :1;\r
+ IO_WORD _D5 :1;\r
+ IO_WORD _D4 :1;\r
+ IO_WORD _D3 :1;\r
+ IO_WORD _D2 :1;\r
+ IO_WORD _D1 :1;\r
+ IO_WORD _D0 :1;\r
+ }bit;\r
+ }TMRLR7STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _D15 :1;\r
+ IO_WORD _D14 :1;\r
+ IO_WORD _D13 :1;\r
+ IO_WORD _D12 :1;\r
+ IO_WORD _D11 :1;\r
+ IO_WORD _D10 :1;\r
+ IO_WORD _D9 :1;\r
+ IO_WORD _D8 :1;\r
+ IO_WORD _D7 :1;\r
+ IO_WORD _D6 :1;\r
+ IO_WORD _D5 :1;\r
+ IO_WORD _D4 :1;\r
+ IO_WORD _D3 :1;\r
+ IO_WORD _D2 :1;\r
+ IO_WORD _D1 :1;\r
+ IO_WORD _D0 :1;\r
+ }bit;\r
+ }TMR7STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CSL2 :1;\r
+ IO_WORD _CSL1 :1;\r
+ IO_WORD _CSL0 :1;\r
+ IO_WORD _MOD2 :1;\r
+ IO_WORD _MOD1 :1;\r
+ IO_WORD _MOD0 :1;\r
+ IO_WORD :1;\r
+ IO_WORD _OULT :1;\r
+ IO_WORD _RELD :1;\r
+ IO_WORD _INTE :1;\r
+ IO_WORD _UF :1;\r
+ IO_WORD _CNTE :1;\r
+ IO_WORD _TRG :1;\r
+ }bit;\r
+ struct{\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CSL :3;\r
+ IO_WORD _MOD :3;\r
+ }bitc;\r
+ }TMCSR7STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CSL2 :1;\r
+ IO_BYTE _CSL1 :1;\r
+ IO_BYTE _CSL0 :1;\r
+ IO_BYTE _MOD2 :1;\r
+ IO_BYTE _MOD1 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :3;\r
+ IO_BYTE _CSL :3;\r
+ }bitc;\r
+ }TMCSRH7STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _MOD0 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _OULT :1;\r
+ IO_BYTE _RELD :1;\r
+ IO_BYTE _INTE :1;\r
+ IO_BYTE _UF :1;\r
+ IO_BYTE _CNTE :1;\r
+ IO_BYTE _TRG :1;\r
+ }bit;\r
+ }TMCSRL7STR;\r
+typedef union{ /* Free Running Timer0 */\r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _T15 :1;\r
+ IO_WORD _T14 :1;\r
+ IO_WORD _T13 :1;\r
+ IO_WORD _T12 :1;\r
+ IO_WORD _T11 :1;\r
+ IO_WORD _T10 :1;\r
+ IO_WORD _T9 :1;\r
+ IO_WORD _T8 :1;\r
+ IO_WORD _T7 :1;\r
+ IO_WORD _T6 :1;\r
+ IO_WORD _T5 :1;\r
+ IO_WORD _T4 :1;\r
+ IO_WORD _T3 :1;\r
+ IO_WORD _T2 :1;\r
+ IO_WORD _T1 :1;\r
+ IO_WORD _T0 :1;\r
+ }bit;\r
+ }TCDT0STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _ECLK :1;\r
+ IO_BYTE _IVF :1;\r
+ IO_BYTE _IVFE :1;\r
+ IO_BYTE _STOP :1;\r
+ IO_BYTE _MODE :1;\r
+ IO_BYTE _CLR :1;\r
+ IO_BYTE _CLK1 :1;\r
+ IO_BYTE _CLK0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CLK :2;\r
+ }bitc;\r
+ }TCCS0STR;\r
+typedef union{ /* Free Running Timer1 */\r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _T15 :1;\r
+ IO_WORD _T14 :1;\r
+ IO_WORD _T13 :1;\r
+ IO_WORD _T12 :1;\r
+ IO_WORD _T11 :1;\r
+ IO_WORD _T10 :1;\r
+ IO_WORD _T9 :1;\r
+ IO_WORD _T8 :1;\r
+ IO_WORD _T7 :1;\r
+ IO_WORD _T6 :1;\r
+ IO_WORD _T5 :1;\r
+ IO_WORD _T4 :1;\r
+ IO_WORD _T3 :1;\r
+ IO_WORD _T2 :1;\r
+ IO_WORD _T1 :1;\r
+ IO_WORD _T0 :1;\r
+ }bit;\r
+ }TCDT1STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _ECLK :1;\r
+ IO_BYTE _IVF :1;\r
+ IO_BYTE _IVFE :1;\r
+ IO_BYTE _STOP :1;\r
+ IO_BYTE _MODE :1;\r
+ IO_BYTE _CLR :1;\r
+ IO_BYTE _CLK1 :1;\r
+ IO_BYTE _CLK0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CLK :2;\r
+ }bitc;\r
+ }TCCS1STR;\r
+typedef union{ /* Free Running Timer2 */\r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _T15 :1;\r
+ IO_WORD _T14 :1;\r
+ IO_WORD _T13 :1;\r
+ IO_WORD _T12 :1;\r
+ IO_WORD _T11 :1;\r
+ IO_WORD _T10 :1;\r
+ IO_WORD _T9 :1;\r
+ IO_WORD _T8 :1;\r
+ IO_WORD _T7 :1;\r
+ IO_WORD _T6 :1;\r
+ IO_WORD _T5 :1;\r
+ IO_WORD _T4 :1;\r
+ IO_WORD _T3 :1;\r
+ IO_WORD _T2 :1;\r
+ IO_WORD _T1 :1;\r
+ IO_WORD _T0 :1;\r
+ }bit;\r
+ }TCDT2STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _ECLK :1;\r
+ IO_BYTE _IVF :1;\r
+ IO_BYTE _IVFE :1;\r
+ IO_BYTE _STOP :1;\r
+ IO_BYTE _MODE :1;\r
+ IO_BYTE _CLR :1;\r
+ IO_BYTE _CLK1 :1;\r
+ IO_BYTE _CLK0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CLK :2;\r
+ }bitc;\r
+ }TCCS2STR;\r
+typedef union{ /* Free Running Timer3 */\r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _T15 :1;\r
+ IO_WORD _T14 :1;\r
+ IO_WORD _T13 :1;\r
+ IO_WORD _T12 :1;\r
+ IO_WORD _T11 :1;\r
+ IO_WORD _T10 :1;\r
+ IO_WORD _T9 :1;\r
+ IO_WORD _T8 :1;\r
+ IO_WORD _T7 :1;\r
+ IO_WORD _T6 :1;\r
+ IO_WORD _T5 :1;\r
+ IO_WORD _T4 :1;\r
+ IO_WORD _T3 :1;\r
+ IO_WORD _T2 :1;\r
+ IO_WORD _T1 :1;\r
+ IO_WORD _T0 :1;\r
+ }bit;\r
+ }TCDT3STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _ECLK :1;\r
+ IO_BYTE _IVF :1;\r
+ IO_BYTE _IVFE :1;\r
+ IO_BYTE _STOP :1;\r
+ IO_BYTE _MODE :1;\r
+ IO_BYTE _CLR :1;\r
+ IO_BYTE _CLK1 :1;\r
+ IO_BYTE _CLK0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CLK :2;\r
+ }bitc;\r
+ }TCCS3STR;\r
+typedef union{ /* DMAC */\r
+ IO_LWORD lword;\r
+ struct{ \r
+ IO_LWORD _DENB :1;\r
+ IO_LWORD _PAUS :1;\r
+ IO_LWORD _STRG :1;\r
+ IO_LWORD _IS4 :1;\r
+ IO_LWORD _IS3 :1;\r
+ IO_LWORD _IS2 :1;\r
+ IO_LWORD _IS1 :1;\r
+ IO_LWORD _IS0 :1;\r
+ IO_LWORD _EIS3 :1;\r
+ IO_LWORD _EIS2 :1;\r
+ IO_LWORD _EIS1 :1;\r
+ IO_LWORD _EIS0 :1;\r
+ IO_LWORD _BLK3 :1;\r
+ IO_LWORD _BLK2 :1;\r
+ IO_LWORD _BLK1 :1;\r
+ IO_LWORD _BLK0 :1;\r
+ IO_LWORD _DTCF :1;\r
+ IO_LWORD _DTCE :1;\r
+ IO_LWORD _DTCD :1;\r
+ IO_LWORD _DTCC :1;\r
+ IO_LWORD _DTCB :1;\r
+ IO_LWORD _DTCA :1;\r
+ IO_LWORD _DTC9 :1;\r
+ IO_LWORD _DTC8 :1;\r
+ IO_LWORD _DTC7 :1;\r
+ IO_LWORD _DTC6 :1;\r
+ IO_LWORD _DTC5 :1;\r
+ IO_LWORD _DTC4 :1;\r
+ IO_LWORD _DTC3 :1;\r
+ IO_LWORD _DTC2 :1;\r
+ IO_LWORD _DTC1 :1;\r
+ IO_LWORD _DTC0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD _IS :5;\r
+ IO_LWORD _EIS :4;\r
+ IO_LWORD _BLK :4;\r
+ IO_LWORD _DTC :16;\r
+ }bitc;\r
+ }DMACA0STR;\r
+typedef union{ \r
+ IO_LWORD lword;\r
+ struct{ \r
+ IO_LWORD _TYPE1 :1;\r
+ IO_LWORD _TYPE0 :1;\r
+ IO_LWORD _MOD1 :1;\r
+ IO_LWORD _MOD0 :1;\r
+ IO_LWORD _WS1 :1;\r
+ IO_LWORD _WS0 :1;\r
+ IO_LWORD _SADM :1;\r
+ IO_LWORD _DADM :1;\r
+ IO_LWORD _DTCR :1;\r
+ IO_LWORD _SADR :1;\r
+ IO_LWORD _DADR :1;\r
+ IO_LWORD _ERIE :1;\r
+ IO_LWORD _EDIE :1;\r
+ IO_LWORD _DSS2 :1;\r
+ IO_LWORD _DSS1 :1;\r
+ IO_LWORD _DSS0 :1;\r
+ IO_LWORD _SASZ7 :1;\r
+ IO_LWORD _SASZ6 :1;\r
+ IO_LWORD _SASZ5 :1;\r
+ IO_LWORD _SASZ4 :1;\r
+ IO_LWORD _SASZ3 :1;\r
+ IO_LWORD _SASZ2 :1;\r
+ IO_LWORD _SASZ1 :1;\r
+ IO_LWORD _SASZ0 :1;\r
+ IO_LWORD _DASZ7 :1;\r
+ IO_LWORD _DASZ6 :1;\r
+ IO_LWORD _DASZ5 :1;\r
+ IO_LWORD _DASZ4 :1;\r
+ IO_LWORD _DASZ3 :1;\r
+ IO_LWORD _DASZ2 :1;\r
+ IO_LWORD _DASZ1 :1;\r
+ IO_LWORD _DASZ0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_LWORD _TYPE :2;\r
+ IO_LWORD _MOD :2;\r
+ IO_LWORD _WS :2;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD _DSS :3;\r
+ IO_LWORD _SASZ :8;\r
+ IO_LWORD _DASZ :8;\r
+ }bitc;\r
+ }DMACB0STR;\r
+typedef union{ \r
+ IO_LWORD lword;\r
+ struct{ \r
+ IO_LWORD _DENB :1;\r
+ IO_LWORD _PAUS :1;\r
+ IO_LWORD _STRG :1;\r
+ IO_LWORD _IS4 :1;\r
+ IO_LWORD _IS3 :1;\r
+ IO_LWORD _IS2 :1;\r
+ IO_LWORD _IS1 :1;\r
+ IO_LWORD _IS0 :1;\r
+ IO_LWORD _EIS3 :1;\r
+ IO_LWORD _EIS2 :1;\r
+ IO_LWORD _EIS1 :1;\r
+ IO_LWORD _EIS0 :1;\r
+ IO_LWORD _BLK3 :1;\r
+ IO_LWORD _BLK2 :1;\r
+ IO_LWORD _BLK1 :1;\r
+ IO_LWORD _BLK0 :1;\r
+ IO_LWORD _DTCF :1;\r
+ IO_LWORD _DTCE :1;\r
+ IO_LWORD _DTCD :1;\r
+ IO_LWORD _DTCC :1;\r
+ IO_LWORD _DTCB :1;\r
+ IO_LWORD _DTCA :1;\r
+ IO_LWORD _DTC9 :1;\r
+ IO_LWORD _DTC8 :1;\r
+ IO_LWORD _DTC7 :1;\r
+ IO_LWORD _DTC6 :1;\r
+ IO_LWORD _DTC5 :1;\r
+ IO_LWORD _DTC4 :1;\r
+ IO_LWORD _DTC3 :1;\r
+ IO_LWORD _DTC2 :1;\r
+ IO_LWORD _DTC1 :1;\r
+ IO_LWORD _DTC0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD _IS :5;\r
+ IO_LWORD _EIS :4;\r
+ IO_LWORD _BLK :4;\r
+ IO_LWORD _DTC :16;\r
+ }bitc;\r
+ }DMACA1STR;\r
+typedef union{ \r
+ IO_LWORD lword;\r
+ struct{ \r
+ IO_LWORD _TYPE1 :1;\r
+ IO_LWORD _TYPE0 :1;\r
+ IO_LWORD _MOD1 :1;\r
+ IO_LWORD _MOD0 :1;\r
+ IO_LWORD _WS1 :1;\r
+ IO_LWORD _WS0 :1;\r
+ IO_LWORD _SADM :1;\r
+ IO_LWORD _DADM :1;\r
+ IO_LWORD _DTCR :1;\r
+ IO_LWORD _SADR :1;\r
+ IO_LWORD _DADR :1;\r
+ IO_LWORD _ERIE :1;\r
+ IO_LWORD _EDIE :1;\r
+ IO_LWORD _DSS2 :1;\r
+ IO_LWORD _DSS1 :1;\r
+ IO_LWORD _DSS0 :1;\r
+ IO_LWORD _SASZ7 :1;\r
+ IO_LWORD _SASZ6 :1;\r
+ IO_LWORD _SASZ5 :1;\r
+ IO_LWORD _SASZ4 :1;\r
+ IO_LWORD _SASZ3 :1;\r
+ IO_LWORD _SASZ2 :1;\r
+ IO_LWORD _SASZ1 :1;\r
+ IO_LWORD _SASZ0 :1;\r
+ IO_LWORD _DASZ7 :1;\r
+ IO_LWORD _DASZ6 :1;\r
+ IO_LWORD _DASZ5 :1;\r
+ IO_LWORD _DASZ4 :1;\r
+ IO_LWORD _DASZ3 :1;\r
+ IO_LWORD _DASZ2 :1;\r
+ IO_LWORD _DASZ1 :1;\r
+ IO_LWORD _DASZ0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_LWORD _TYPE :2;\r
+ IO_LWORD _MOD :2;\r
+ IO_LWORD _WS :2;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD _DSS :3;\r
+ IO_LWORD _SASZ :8;\r
+ IO_LWORD _DASZ :8;\r
+ }bitc;\r
+ }DMACB1STR;\r
+typedef union{ \r
+ IO_LWORD lword;\r
+ struct{ \r
+ IO_LWORD _DENB :1;\r
+ IO_LWORD _PAUS :1;\r
+ IO_LWORD _STRG :1;\r
+ IO_LWORD _IS4 :1;\r
+ IO_LWORD _IS3 :1;\r
+ IO_LWORD _IS2 :1;\r
+ IO_LWORD _IS1 :1;\r
+ IO_LWORD _IS0 :1;\r
+ IO_LWORD _EIS3 :1;\r
+ IO_LWORD _EIS2 :1;\r
+ IO_LWORD _EIS1 :1;\r
+ IO_LWORD _EIS0 :1;\r
+ IO_LWORD _BLK3 :1;\r
+ IO_LWORD _BLK2 :1;\r
+ IO_LWORD _BLK1 :1;\r
+ IO_LWORD _BLK0 :1;\r
+ IO_LWORD _DTCF :1;\r
+ IO_LWORD _DTCE :1;\r
+ IO_LWORD _DTCD :1;\r
+ IO_LWORD _DTCC :1;\r
+ IO_LWORD _DTCB :1;\r
+ IO_LWORD _DTCA :1;\r
+ IO_LWORD _DTC9 :1;\r
+ IO_LWORD _DTC8 :1;\r
+ IO_LWORD _DTC7 :1;\r
+ IO_LWORD _DTC6 :1;\r
+ IO_LWORD _DTC5 :1;\r
+ IO_LWORD _DTC4 :1;\r
+ IO_LWORD _DTC3 :1;\r
+ IO_LWORD _DTC2 :1;\r
+ IO_LWORD _DTC1 :1;\r
+ IO_LWORD _DTC0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD _IS :5;\r
+ IO_LWORD _EIS :4;\r
+ IO_LWORD _BLK :4;\r
+ IO_LWORD _DTC :16;\r
+ }bitc;\r
+ }DMACA2STR;\r
+typedef union{ \r
+ IO_LWORD lword;\r
+ struct{ \r
+ IO_LWORD _TYPE1 :1;\r
+ IO_LWORD _TYPE0 :1;\r
+ IO_LWORD _MOD1 :1;\r
+ IO_LWORD _MOD0 :1;\r
+ IO_LWORD _WS1 :1;\r
+ IO_LWORD _WS0 :1;\r
+ IO_LWORD _SADM :1;\r
+ IO_LWORD _DADM :1;\r
+ IO_LWORD _DTCR :1;\r
+ IO_LWORD _SADR :1;\r
+ IO_LWORD _DADR :1;\r
+ IO_LWORD _ERIE :1;\r
+ IO_LWORD _EDIE :1;\r
+ IO_LWORD _DSS2 :1;\r
+ IO_LWORD _DSS1 :1;\r
+ IO_LWORD _DSS0 :1;\r
+ IO_LWORD _SASZ7 :1;\r
+ IO_LWORD _SASZ6 :1;\r
+ IO_LWORD _SASZ5 :1;\r
+ IO_LWORD _SASZ4 :1;\r
+ IO_LWORD _SASZ3 :1;\r
+ IO_LWORD _SASZ2 :1;\r
+ IO_LWORD _SASZ1 :1;\r
+ IO_LWORD _SASZ0 :1;\r
+ IO_LWORD _DASZ7 :1;\r
+ IO_LWORD _DASZ6 :1;\r
+ IO_LWORD _DASZ5 :1;\r
+ IO_LWORD _DASZ4 :1;\r
+ IO_LWORD _DASZ3 :1;\r
+ IO_LWORD _DASZ2 :1;\r
+ IO_LWORD _DASZ1 :1;\r
+ IO_LWORD _DASZ0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_LWORD _TYPE :2;\r
+ IO_LWORD _MOD :2;\r
+ IO_LWORD _WS :2;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD _DSS :3;\r
+ IO_LWORD _SASZ :8;\r
+ IO_LWORD _DASZ :8;\r
+ }bitc;\r
+ }DMACB2STR;\r
+typedef union{ \r
+ IO_LWORD lword;\r
+ struct{ \r
+ IO_LWORD _DENB :1;\r
+ IO_LWORD _PAUS :1;\r
+ IO_LWORD _STRG :1;\r
+ IO_LWORD _IS4 :1;\r
+ IO_LWORD _IS3 :1;\r
+ IO_LWORD _IS2 :1;\r
+ IO_LWORD _IS1 :1;\r
+ IO_LWORD _IS0 :1;\r
+ IO_LWORD _EIS3 :1;\r
+ IO_LWORD _EIS2 :1;\r
+ IO_LWORD _EIS1 :1;\r
+ IO_LWORD _EIS0 :1;\r
+ IO_LWORD _BLK3 :1;\r
+ IO_LWORD _BLK2 :1;\r
+ IO_LWORD _BLK1 :1;\r
+ IO_LWORD _BLK0 :1;\r
+ IO_LWORD _DTCF :1;\r
+ IO_LWORD _DTCE :1;\r
+ IO_LWORD _DTCD :1;\r
+ IO_LWORD _DTCC :1;\r
+ IO_LWORD _DTCB :1;\r
+ IO_LWORD _DTCA :1;\r
+ IO_LWORD _DTC9 :1;\r
+ IO_LWORD _DTC8 :1;\r
+ IO_LWORD _DTC7 :1;\r
+ IO_LWORD _DTC6 :1;\r
+ IO_LWORD _DTC5 :1;\r
+ IO_LWORD _DTC4 :1;\r
+ IO_LWORD _DTC3 :1;\r
+ IO_LWORD _DTC2 :1;\r
+ IO_LWORD _DTC1 :1;\r
+ IO_LWORD _DTC0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD _IS :5;\r
+ IO_LWORD _EIS :4;\r
+ IO_LWORD _BLK :4;\r
+ IO_LWORD _DTC :16;\r
+ }bitc;\r
+ }DMACA3STR;\r
+typedef union{ \r
+ IO_LWORD lword;\r
+ struct{ \r
+ IO_LWORD _TYPE1 :1;\r
+ IO_LWORD _TYPE0 :1;\r
+ IO_LWORD _MOD1 :1;\r
+ IO_LWORD _MOD0 :1;\r
+ IO_LWORD _WS1 :1;\r
+ IO_LWORD _WS0 :1;\r
+ IO_LWORD _SADM :1;\r
+ IO_LWORD _DADM :1;\r
+ IO_LWORD _DTCR :1;\r
+ IO_LWORD _SADR :1;\r
+ IO_LWORD _DADR :1;\r
+ IO_LWORD _ERIE :1;\r
+ IO_LWORD _EDIE :1;\r
+ IO_LWORD _DSS2 :1;\r
+ IO_LWORD _DSS1 :1;\r
+ IO_LWORD _DSS0 :1;\r
+ IO_LWORD _SASZ7 :1;\r
+ IO_LWORD _SASZ6 :1;\r
+ IO_LWORD _SASZ5 :1;\r
+ IO_LWORD _SASZ4 :1;\r
+ IO_LWORD _SASZ3 :1;\r
+ IO_LWORD _SASZ2 :1;\r
+ IO_LWORD _SASZ1 :1;\r
+ IO_LWORD _SASZ0 :1;\r
+ IO_LWORD _DASZ7 :1;\r
+ IO_LWORD _DASZ6 :1;\r
+ IO_LWORD _DASZ5 :1;\r
+ IO_LWORD _DASZ4 :1;\r
+ IO_LWORD _DASZ3 :1;\r
+ IO_LWORD _DASZ2 :1;\r
+ IO_LWORD _DASZ1 :1;\r
+ IO_LWORD _DASZ0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_LWORD _TYPE :2;\r
+ IO_LWORD _MOD :2;\r
+ IO_LWORD _WS :2;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD _DSS :3;\r
+ IO_LWORD _SASZ :8;\r
+ IO_LWORD _DASZ :8;\r
+ }bitc;\r
+ }DMACB3STR;\r
+typedef union{ \r
+ IO_LWORD lword;\r
+ struct{ \r
+ IO_LWORD _DENB :1;\r
+ IO_LWORD _PAUS :1;\r
+ IO_LWORD _STRG :1;\r
+ IO_LWORD _IS4 :1;\r
+ IO_LWORD _IS3 :1;\r
+ IO_LWORD _IS2 :1;\r
+ IO_LWORD _IS1 :1;\r
+ IO_LWORD _IS0 :1;\r
+ IO_LWORD _EIS3 :1;\r
+ IO_LWORD _EIS2 :1;\r
+ IO_LWORD _EIS1 :1;\r
+ IO_LWORD _EIS0 :1;\r
+ IO_LWORD _BLK3 :1;\r
+ IO_LWORD _BLK2 :1;\r
+ IO_LWORD _BLK1 :1;\r
+ IO_LWORD _BLK0 :1;\r
+ IO_LWORD _DTCF :1;\r
+ IO_LWORD _DTCE :1;\r
+ IO_LWORD _DTCD :1;\r
+ IO_LWORD _DTCC :1;\r
+ IO_LWORD _DTCB :1;\r
+ IO_LWORD _DTCA :1;\r
+ IO_LWORD _DTC9 :1;\r
+ IO_LWORD _DTC8 :1;\r
+ IO_LWORD _DTC7 :1;\r
+ IO_LWORD _DTC6 :1;\r
+ IO_LWORD _DTC5 :1;\r
+ IO_LWORD _DTC4 :1;\r
+ IO_LWORD _DTC3 :1;\r
+ IO_LWORD _DTC2 :1;\r
+ IO_LWORD _DTC1 :1;\r
+ IO_LWORD _DTC0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD _IS :5;\r
+ IO_LWORD _EIS :4;\r
+ IO_LWORD _BLK :4;\r
+ IO_LWORD _DTC :16;\r
+ }bitc;\r
+ }DMACA4STR;\r
+typedef union{ \r
+ IO_LWORD lword;\r
+ struct{ \r
+ IO_LWORD _TYPE1 :1;\r
+ IO_LWORD _TYPE0 :1;\r
+ IO_LWORD _MOD1 :1;\r
+ IO_LWORD _MOD0 :1;\r
+ IO_LWORD _WS1 :1;\r
+ IO_LWORD _WS0 :1;\r
+ IO_LWORD _SADM :1;\r
+ IO_LWORD _DADM :1;\r
+ IO_LWORD _DTCR :1;\r
+ IO_LWORD _SADR :1;\r
+ IO_LWORD _DADR :1;\r
+ IO_LWORD _ERIE :1;\r
+ IO_LWORD _EDIE :1;\r
+ IO_LWORD _DSS2 :1;\r
+ IO_LWORD _DSS1 :1;\r
+ IO_LWORD _DSS0 :1;\r
+ IO_LWORD _SASZ7 :1;\r
+ IO_LWORD _SASZ6 :1;\r
+ IO_LWORD _SASZ5 :1;\r
+ IO_LWORD _SASZ4 :1;\r
+ IO_LWORD _SASZ3 :1;\r
+ IO_LWORD _SASZ2 :1;\r
+ IO_LWORD _SASZ1 :1;\r
+ IO_LWORD _SASZ0 :1;\r
+ IO_LWORD _DASZ7 :1;\r
+ IO_LWORD _DASZ6 :1;\r
+ IO_LWORD _DASZ5 :1;\r
+ IO_LWORD _DASZ4 :1;\r
+ IO_LWORD _DASZ3 :1;\r
+ IO_LWORD _DASZ2 :1;\r
+ IO_LWORD _DASZ1 :1;\r
+ IO_LWORD _DASZ0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_LWORD _TYPE :2;\r
+ IO_LWORD _MOD :2;\r
+ IO_LWORD _WS :2;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD _DSS :3;\r
+ IO_LWORD _SASZ :8;\r
+ IO_LWORD _DASZ :8;\r
+ }bitc;\r
+ }DMACB4STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _DMAE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _PM01 :1;\r
+ IO_BYTE _DMAH3 :1;\r
+ IO_BYTE _DMAH2 :1;\r
+ IO_BYTE _DMAH1 :1;\r
+ IO_BYTE _DMAH0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _DMAH :4;\r
+ }bitc;\r
+ }DMACRSTR;\r
+typedef union{ /* Input Capture 4-7 */\r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _ICP5 :1;\r
+ IO_BYTE _ICP4 :1;\r
+ IO_BYTE _ICE5 :1;\r
+ IO_BYTE _ICE4 :1;\r
+ IO_BYTE _EG51 :1;\r
+ IO_BYTE _EG50 :1;\r
+ IO_BYTE _EG41 :1;\r
+ IO_BYTE _EG40 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _EG5 :2;\r
+ IO_BYTE _EG4 :2;\r
+ }bitc;\r
+ }ICS45STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _ICP7 :1;\r
+ IO_BYTE _ICP6 :1;\r
+ IO_BYTE _ICE7 :1;\r
+ IO_BYTE _ICE6 :1;\r
+ IO_BYTE _EG71 :1;\r
+ IO_BYTE _EG70 :1;\r
+ IO_BYTE _EG61 :1;\r
+ IO_BYTE _EG60 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _EG7 :2;\r
+ IO_BYTE _EG6 :2;\r
+ }bitc;\r
+ }ICS67STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _CP15 :1;\r
+ IO_WORD _CP14 :1;\r
+ IO_WORD _CP13 :1;\r
+ IO_WORD _CP12 :1;\r
+ IO_WORD _CP11 :1;\r
+ IO_WORD _CP10 :1;\r
+ IO_WORD _CP9 :1;\r
+ IO_WORD _CP8 :1;\r
+ IO_WORD _CP7 :1;\r
+ IO_WORD _CP6 :1;\r
+ IO_WORD _CP5 :1;\r
+ IO_WORD _CP4 :1;\r
+ IO_WORD _CP3 :1;\r
+ IO_WORD _CP2 :1;\r
+ IO_WORD _CP1 :1;\r
+ IO_WORD _CP0 :1;\r
+ }bit;\r
+ }IPCP4STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _CP15 :1;\r
+ IO_WORD _CP14 :1;\r
+ IO_WORD _CP13 :1;\r
+ IO_WORD _CP12 :1;\r
+ IO_WORD _CP11 :1;\r
+ IO_WORD _CP10 :1;\r
+ IO_WORD _CP9 :1;\r
+ IO_WORD _CP8 :1;\r
+ IO_WORD _CP7 :1;\r
+ IO_WORD _CP6 :1;\r
+ IO_WORD _CP5 :1;\r
+ IO_WORD _CP4 :1;\r
+ IO_WORD _CP3 :1;\r
+ IO_WORD _CP2 :1;\r
+ IO_WORD _CP1 :1;\r
+ IO_WORD _CP0 :1;\r
+ }bit;\r
+ }IPCP5STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _CP15 :1;\r
+ IO_WORD _CP14 :1;\r
+ IO_WORD _CP13 :1;\r
+ IO_WORD _CP12 :1;\r
+ IO_WORD _CP11 :1;\r
+ IO_WORD _CP10 :1;\r
+ IO_WORD _CP9 :1;\r
+ IO_WORD _CP8 :1;\r
+ IO_WORD _CP7 :1;\r
+ IO_WORD _CP6 :1;\r
+ IO_WORD _CP5 :1;\r
+ IO_WORD _CP4 :1;\r
+ IO_WORD _CP3 :1;\r
+ IO_WORD _CP2 :1;\r
+ IO_WORD _CP1 :1;\r
+ IO_WORD _CP0 :1;\r
+ }bit;\r
+ }IPCP6STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _CP15 :1;\r
+ IO_WORD _CP14 :1;\r
+ IO_WORD _CP13 :1;\r
+ IO_WORD _CP12 :1;\r
+ IO_WORD _CP11 :1;\r
+ IO_WORD _CP10 :1;\r
+ IO_WORD _CP9 :1;\r
+ IO_WORD _CP8 :1;\r
+ IO_WORD _CP7 :1;\r
+ IO_WORD _CP6 :1;\r
+ IO_WORD _CP5 :1;\r
+ IO_WORD _CP4 :1;\r
+ IO_WORD _CP3 :1;\r
+ IO_WORD _CP2 :1;\r
+ IO_WORD _CP1 :1;\r
+ IO_WORD _CP0 :1;\r
+ }bit;\r
+ }IPCP7STR;\r
+typedef union{ /* Output Compare 4-7 */\r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CMOD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _OTD5 :1;\r
+ IO_WORD _OTD4 :1;\r
+ IO_WORD _ICP5 :1;\r
+ IO_WORD _ICP4 :1;\r
+ IO_WORD _ICE5 :1;\r
+ IO_WORD _ICE4 :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CST5 :1;\r
+ IO_WORD _CST4 :1;\r
+ }bit;\r
+ }OCS45STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CMOD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _OTD7 :1;\r
+ IO_WORD _OTD6 :1;\r
+ IO_WORD _ICP7 :1;\r
+ IO_WORD _ICP6 :1;\r
+ IO_WORD _ICE7 :1;\r
+ IO_WORD _ICE6 :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _CST7 :1;\r
+ IO_WORD _CST6 :1;\r
+ }bit;\r
+ }OCS67STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _C15 :1;\r
+ IO_WORD _C14 :1;\r
+ IO_WORD _C13 :1;\r
+ IO_WORD _C12 :1;\r
+ IO_WORD _C11 :1;\r
+ IO_WORD _C10 :1;\r
+ IO_WORD _C9 :1;\r
+ IO_WORD _C8 :1;\r
+ IO_WORD _C7 :1;\r
+ IO_WORD _C6 :1;\r
+ IO_WORD _C5 :1;\r
+ IO_WORD _C4 :1;\r
+ IO_WORD _C3 :1;\r
+ IO_WORD _C2 :1;\r
+ IO_WORD _C1 :1;\r
+ IO_WORD _C0 :1;\r
+ }bit;\r
+ }OCCP4STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _C15 :1;\r
+ IO_WORD _C14 :1;\r
+ IO_WORD _C13 :1;\r
+ IO_WORD _C12 :1;\r
+ IO_WORD _C11 :1;\r
+ IO_WORD _C10 :1;\r
+ IO_WORD _C9 :1;\r
+ IO_WORD _C8 :1;\r
+ IO_WORD _C7 :1;\r
+ IO_WORD _C6 :1;\r
+ IO_WORD _C5 :1;\r
+ IO_WORD _C4 :1;\r
+ IO_WORD _C3 :1;\r
+ IO_WORD _C2 :1;\r
+ IO_WORD _C1 :1;\r
+ IO_WORD _C0 :1;\r
+ }bit;\r
+ }OCCP5STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _C15 :1;\r
+ IO_WORD _C14 :1;\r
+ IO_WORD _C13 :1;\r
+ IO_WORD _C12 :1;\r
+ IO_WORD _C11 :1;\r
+ IO_WORD _C10 :1;\r
+ IO_WORD _C9 :1;\r
+ IO_WORD _C8 :1;\r
+ IO_WORD _C7 :1;\r
+ IO_WORD _C6 :1;\r
+ IO_WORD _C5 :1;\r
+ IO_WORD _C4 :1;\r
+ IO_WORD _C3 :1;\r
+ IO_WORD _C2 :1;\r
+ IO_WORD _C1 :1;\r
+ IO_WORD _C0 :1;\r
+ }bit;\r
+ }OCCP6STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _C15 :1;\r
+ IO_WORD _C14 :1;\r
+ IO_WORD _C13 :1;\r
+ IO_WORD _C12 :1;\r
+ IO_WORD _C11 :1;\r
+ IO_WORD _C10 :1;\r
+ IO_WORD _C9 :1;\r
+ IO_WORD _C8 :1;\r
+ IO_WORD _C7 :1;\r
+ IO_WORD _C6 :1;\r
+ IO_WORD _C5 :1;\r
+ IO_WORD _C4 :1;\r
+ IO_WORD _C3 :1;\r
+ IO_WORD _C2 :1;\r
+ IO_WORD _C1 :1;\r
+ IO_WORD _C0 :1;\r
+ }bit;\r
+ }OCCP7STR;\r
+typedef union{ /* Free Running Timer4 */\r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _T15 :1;\r
+ IO_WORD _T14 :1;\r
+ IO_WORD _T13 :1;\r
+ IO_WORD _T12 :1;\r
+ IO_WORD _T11 :1;\r
+ IO_WORD _T10 :1;\r
+ IO_WORD _T9 :1;\r
+ IO_WORD _T8 :1;\r
+ IO_WORD _T7 :1;\r
+ IO_WORD _T6 :1;\r
+ IO_WORD _T5 :1;\r
+ IO_WORD _T4 :1;\r
+ IO_WORD _T3 :1;\r
+ IO_WORD _T2 :1;\r
+ IO_WORD _T1 :1;\r
+ IO_WORD _T0 :1;\r
+ }bit;\r
+ }TCDT4STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _ECLK :1;\r
+ IO_BYTE _IVF :1;\r
+ IO_BYTE _IVFE :1;\r
+ IO_BYTE _STOP :1;\r
+ IO_BYTE _MODE :1;\r
+ IO_BYTE _CLR :1;\r
+ IO_BYTE _CLK1 :1;\r
+ IO_BYTE _CLK0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CLK :2;\r
+ }bitc;\r
+ }TCCS4STR;\r
+typedef union{ /* Free Running Timer5 */\r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _T15 :1;\r
+ IO_WORD _T14 :1;\r
+ IO_WORD _T13 :1;\r
+ IO_WORD _T12 :1;\r
+ IO_WORD _T11 :1;\r
+ IO_WORD _T10 :1;\r
+ IO_WORD _T9 :1;\r
+ IO_WORD _T8 :1;\r
+ IO_WORD _T7 :1;\r
+ IO_WORD _T6 :1;\r
+ IO_WORD _T5 :1;\r
+ IO_WORD _T4 :1;\r
+ IO_WORD _T3 :1;\r
+ IO_WORD _T2 :1;\r
+ IO_WORD _T1 :1;\r
+ IO_WORD _T0 :1;\r
+ }bit;\r
+ }TCDT5STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _ECLK :1;\r
+ IO_BYTE _IVF :1;\r
+ IO_BYTE _IVFE :1;\r
+ IO_BYTE _STOP :1;\r
+ IO_BYTE _MODE :1;\r
+ IO_BYTE _CLR :1;\r
+ IO_BYTE _CLK1 :1;\r
+ IO_BYTE _CLK0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CLK :2;\r
+ }bitc;\r
+ }TCCS5STR;\r
+typedef union{ /* Free Running Timer6 */\r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _T15 :1;\r
+ IO_WORD _T14 :1;\r
+ IO_WORD _T13 :1;\r
+ IO_WORD _T12 :1;\r
+ IO_WORD _T11 :1;\r
+ IO_WORD _T10 :1;\r
+ IO_WORD _T9 :1;\r
+ IO_WORD _T8 :1;\r
+ IO_WORD _T7 :1;\r
+ IO_WORD _T6 :1;\r
+ IO_WORD _T5 :1;\r
+ IO_WORD _T4 :1;\r
+ IO_WORD _T3 :1;\r
+ IO_WORD _T2 :1;\r
+ IO_WORD _T1 :1;\r
+ IO_WORD _T0 :1;\r
+ }bit;\r
+ }TCDT6STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _ECLK :1;\r
+ IO_BYTE _IVF :1;\r
+ IO_BYTE _IVFE :1;\r
+ IO_BYTE _STOP :1;\r
+ IO_BYTE _MODE :1;\r
+ IO_BYTE _CLR :1;\r
+ IO_BYTE _CLK1 :1;\r
+ IO_BYTE _CLK0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CLK :2;\r
+ }bitc;\r
+ }TCCS6STR;\r
+typedef union{ /* Free Running Timer7 */\r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _T15 :1;\r
+ IO_WORD _T14 :1;\r
+ IO_WORD _T13 :1;\r
+ IO_WORD _T12 :1;\r
+ IO_WORD _T11 :1;\r
+ IO_WORD _T10 :1;\r
+ IO_WORD _T9 :1;\r
+ IO_WORD _T8 :1;\r
+ IO_WORD _T7 :1;\r
+ IO_WORD _T6 :1;\r
+ IO_WORD _T5 :1;\r
+ IO_WORD _T4 :1;\r
+ IO_WORD _T3 :1;\r
+ IO_WORD _T2 :1;\r
+ IO_WORD _T1 :1;\r
+ IO_WORD _T0 :1;\r
+ }bit;\r
+ }TCDT7STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _ECLK :1;\r
+ IO_BYTE _IVF :1;\r
+ IO_BYTE _IVFE :1;\r
+ IO_BYTE _STOP :1;\r
+ IO_BYTE _MODE :1;\r
+ IO_BYTE _CLR :1;\r
+ IO_BYTE _CLK1 :1;\r
+ IO_BYTE _CLK0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CLK :2;\r
+ }bitc;\r
+ }TCCS7STR;\r
+typedef union{ /* ROM Select Register */\r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _D15 :1;\r
+ IO_WORD _D14 :1;\r
+ IO_WORD _D13 :1;\r
+ IO_WORD _D12 :1;\r
+ IO_WORD _D11 :1;\r
+ IO_WORD _D10 :1;\r
+ IO_WORD _D9 :1;\r
+ IO_WORD _D8 :1;\r
+ IO_WORD _D7 :1;\r
+ IO_WORD _D6 :1;\r
+ IO_WORD _D5 :1;\r
+ IO_WORD _D4 :1;\r
+ IO_WORD _D3 :1;\r
+ IO_WORD _D2 :1;\r
+ IO_WORD _D1 :1;\r
+ IO_WORD _D0 :1;\r
+ }bit;\r
+ }ROMSSTR;\r
+typedef union{ /* Interrupt Control Unit */\r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR00STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR01STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR02STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR03STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR04STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR05STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR06STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR07STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR08STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR09STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR10STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR11STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR12STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR13STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR14STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR15STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR16STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR17STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR18STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR19STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR20STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR21STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR22STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR23STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR24STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR25STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR26STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR27STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR28STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR29STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR30STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR31STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR32STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR33STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR34STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR35STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR36STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR37STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR38STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR39STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR40STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR41STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR42STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR43STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR44STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR45STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR46STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR47STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR48STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR49STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR50STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR51STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR52STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR53STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR54STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR55STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR56STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR57STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR58STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR59STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR60STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR61STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR62STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ICR4 :1;\r
+ IO_BYTE _ICR3 :1;\r
+ IO_BYTE _ICR2 :1;\r
+ IO_BYTE _ICR1 :1;\r
+ IO_BYTE _ICR0 :1;\r
+ }bit;\r
+ }ICR63STR;\r
+typedef union{ /* Clock Control Unit */\r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _INIT :1;\r
+ IO_BYTE _HSTB :1;\r
+ IO_BYTE _WDOG :1;\r
+ IO_BYTE _ERST :1;\r
+ IO_BYTE _SRST :1;\r
+ IO_BYTE _LINIT :1;\r
+ IO_BYTE _WT1 :1;\r
+ IO_BYTE _WT0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _WT :2;\r
+ }bitc;\r
+ }RSRRSTR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _STOP :1;\r
+ IO_BYTE _SLEEP :1;\r
+ IO_BYTE _HIZ :1;\r
+ IO_BYTE _SRST :1;\r
+ IO_BYTE _OS1 :1;\r
+ IO_BYTE _OS0 :1;\r
+ IO_BYTE _OSCD2 :1;\r
+ IO_BYTE _OSCD1 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _OS :2;\r
+ IO_BYTE _OSCD :2;\r
+ }bitc;\r
+ }STCRSTR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _TBIF :1;\r
+ IO_BYTE _TBIE :1;\r
+ IO_BYTE _TBC2 :1;\r
+ IO_BYTE _TBC1 :1;\r
+ IO_BYTE _TBC0 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _SYNCR :1;\r
+ IO_BYTE _SYNCS :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _TBC :3;\r
+ }bitc;\r
+ }TBCRSTR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }CTBRSTR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _SCKEN :1;\r
+ IO_BYTE _PLL1EN :1;\r
+ IO_BYTE _CLKS1 :1;\r
+ IO_BYTE _CLKS0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CLKS :2;\r
+ }bitc;\r
+ }CLKRSTR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }WPRSTR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _B3 :1;\r
+ IO_BYTE _B2 :1;\r
+ IO_BYTE _B1 :1;\r
+ IO_BYTE _B0 :1;\r
+ IO_BYTE _P3 :1;\r
+ IO_BYTE _P2 :1;\r
+ IO_BYTE _P1 :1;\r
+ IO_BYTE _P0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE _B :4;\r
+ IO_BYTE _P :4;\r
+ }bitc;\r
+ }DIVR0STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _T3 :1;\r
+ IO_BYTE _T2 :1;\r
+ IO_BYTE _T1 :1;\r
+ IO_BYTE _T0 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE _T :4;\r
+ }bitc;\r
+ }DIVR1STR;\r
+typedef union{ /* PLL - Clock Gear Unit: */\r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _DVM3 :1;\r
+ IO_BYTE _DVM2 :1;\r
+ IO_BYTE _DVM1 :1;\r
+ IO_BYTE _DVM0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _DVM :4;\r
+ }bitc;\r
+ }PLLDIVMSTR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _DVN5 :1;\r
+ IO_BYTE _DVN4 :1;\r
+ IO_BYTE _DVN3 :1;\r
+ IO_BYTE _DVN2 :1;\r
+ IO_BYTE _DVN1 :1;\r
+ IO_BYTE _DVN0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _DVN :6;\r
+ }bitc;\r
+ }PLLDIVNSTR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _DVG3 :1;\r
+ IO_BYTE _DVG2 :1;\r
+ IO_BYTE _DVG1 :1;\r
+ IO_BYTE _DVG0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _DVG :4;\r
+ }bitc;\r
+ }PLLDIVGSTR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _MLG7 :1;\r
+ IO_BYTE _MLG6 :1;\r
+ IO_BYTE _MLG5 :1;\r
+ IO_BYTE _MLG4 :1;\r
+ IO_BYTE _MLG3 :1;\r
+ IO_BYTE _MLG2 :1;\r
+ IO_BYTE _MLG1 :1;\r
+ IO_BYTE _MLG0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE _MLG :8;\r
+ }bitc;\r
+ }PLLMULGSTR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _IEDN :1;\r
+ IO_BYTE _GRDN :1;\r
+ IO_BYTE _IEUP :1;\r
+ IO_BYTE _GRUP :1;\r
+ }bit;\r
+ }PLLCTRLSTR;\r
+typedef union{ /* Main/Sub Oscillator Control */\r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _FCI :1;\r
+ IO_BYTE _RFBEN :1;\r
+ IO_BYTE _OSCR :1;\r
+ }bit;\r
+ }OSCC1STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _OSCS7 :1;\r
+ IO_BYTE _OSCS6 :1;\r
+ IO_BYTE _OSCS5 :1;\r
+ IO_BYTE _OSCS4 :1;\r
+ IO_BYTE _OSCS3 :1;\r
+ IO_BYTE _OSCS2 :1;\r
+ IO_BYTE _OSCS1 :1;\r
+ IO_BYTE _OSCS0 :1;\r
+ }bit;\r
+ }OSCS1STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _FCI :1;\r
+ IO_BYTE _RFBEN :1;\r
+ IO_BYTE _OSCR :1;\r
+ }bit;\r
+ }OSCC2STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _OSCS7 :1;\r
+ IO_BYTE _OSCS6 :1;\r
+ IO_BYTE _OSCS5 :1;\r
+ IO_BYTE _OSCS4 :1;\r
+ IO_BYTE _OSCS3 :1;\r
+ IO_BYTE _OSCS2 :1;\r
+ IO_BYTE _OSCS1 :1;\r
+ IO_BYTE _OSCS0 :1;\r
+ }bit;\r
+ }OSCS2STR;\r
+typedef union{ /* Port Input Enable Control */\r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CPORTEN :1;\r
+ IO_BYTE _GPORTEN :1;\r
+ }bit;\r
+ }PORTENSTR;\r
+typedef union{ /* Real Time Clock (Watch Timer) */\r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _INTE4 :1;\r
+ IO_BYTE _INT4 :1;\r
+ }bit;\r
+ }WTCERSTR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _INTE3 :1;\r
+ IO_WORD _INT3 :1;\r
+ IO_WORD _INTE2 :1;\r
+ IO_WORD _INT2 :1;\r
+ IO_WORD _INTE1 :1;\r
+ IO_WORD _INT1 :1;\r
+ IO_WORD _INTE0 :1;\r
+ IO_WORD _INT0 :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _RUN :1;\r
+ IO_WORD _UPDT :1;\r
+ IO_WORD :1;\r
+ IO_WORD _ST :1;\r
+ }bit;\r
+ }WTCRSTR;\r
+typedef union{ \r
+ IO_LWORD lword;\r
+ struct{ \r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD _D20 :1;\r
+ IO_LWORD _D19 :1;\r
+ IO_LWORD _D18 :1;\r
+ IO_LWORD _D17 :1;\r
+ IO_LWORD _D16 :1;\r
+ IO_LWORD _D15 :1;\r
+ IO_LWORD _D14 :1;\r
+ IO_LWORD _D13 :1;\r
+ IO_LWORD _D12 :1;\r
+ IO_LWORD _D11 :1;\r
+ IO_LWORD _D10 :1;\r
+ IO_LWORD _D9 :1;\r
+ IO_LWORD _D8 :1;\r
+ IO_LWORD _D7 :1;\r
+ IO_LWORD _D6 :1;\r
+ IO_LWORD _D5 :1;\r
+ IO_LWORD _D4 :1;\r
+ IO_LWORD _D3 :1;\r
+ IO_LWORD _D2 :1;\r
+ IO_LWORD _D1 :1;\r
+ IO_LWORD _D0 :1;\r
+ }bit;\r
+ }WTBRSTR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _H4 :1;\r
+ IO_BYTE _H3 :1;\r
+ IO_BYTE _H2 :1;\r
+ IO_BYTE _H1 :1;\r
+ IO_BYTE _H0 :1;\r
+ }bit;\r
+ }WTHRSTR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _M5 :1;\r
+ IO_BYTE _M4 :1;\r
+ IO_BYTE _M3 :1;\r
+ IO_BYTE _M2 :1;\r
+ IO_BYTE _M1 :1;\r
+ IO_BYTE _M0 :1;\r
+ }bit;\r
+ }WTMRSTR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _S5 :1;\r
+ IO_BYTE _S4 :1;\r
+ IO_BYTE _S3 :1;\r
+ IO_BYTE _S2 :1;\r
+ IO_BYTE _S1 :1;\r
+ IO_BYTE _S0 :1;\r
+ }bit;\r
+ }WTSRSTR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _SCKS :1;\r
+ IO_BYTE _MM :1;\r
+ IO_BYTE _SM :1;\r
+ IO_BYTE _RCE :1;\r
+ IO_BYTE _MSVE :1;\r
+ IO_BYTE _SSVE :1;\r
+ IO_BYTE _SRST :1;\r
+ IO_BYTE _OUTE :1;\r
+ }bit;\r
+ }CSVCRSTR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _EDSUEN :1;\r
+ IO_BYTE _PLLLOCK :1;\r
+ IO_BYTE _RCSEL :1;\r
+ IO_BYTE _MONCKI :1;\r
+ IO_BYTE _CSC3 :1;\r
+ IO_BYTE _CSC2 :1;\r
+ IO_BYTE _CSC1 :1;\r
+ IO_BYTE _CSC0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :4;\r
+ IO_BYTE _CSC :4;\r
+ }bitc;\r
+ }CSCFGSTR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _CMPRE3 :1;\r
+ IO_BYTE _CMPRE2 :1;\r
+ IO_BYTE _CMPRE1 :1;\r
+ IO_BYTE _CMPRE0 :1;\r
+ IO_BYTE _CMSEL3 :1;\r
+ IO_BYTE _CMSEL2 :1;\r
+ IO_BYTE _CMSEL1 :1;\r
+ IO_BYTE _CMSEL0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE _CMPRE :4;\r
+ IO_BYTE _CMSEL :4;\r
+ }bitc;\r
+ }CMCFGSTR;\r
+typedef union{ /* Calibration Unit of Sub Oszillation */\r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _STRT :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _INT :1;\r
+ IO_WORD _INTEN :1;\r
+ }bit;\r
+ }CUCRSTR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _TDD15 :1;\r
+ IO_WORD _TDD14 :1;\r
+ IO_WORD _TDD13 :1;\r
+ IO_WORD _TDD12 :1;\r
+ IO_WORD _TDD11 :1;\r
+ IO_WORD _TDD10 :1;\r
+ IO_WORD _TDD9 :1;\r
+ IO_WORD _TDD8 :1;\r
+ IO_WORD _TDD7 :1;\r
+ IO_WORD _TDD6 :1;\r
+ IO_WORD _TDD5 :1;\r
+ IO_WORD _TDD4 :1;\r
+ IO_WORD _TDD3 :1;\r
+ IO_WORD _TDD2 :1;\r
+ IO_WORD _TDD1 :1;\r
+ IO_WORD _TDD0 :1;\r
+ }bit;\r
+ }CUTDSTR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _TDR23 :1;\r
+ IO_WORD _TDR22 :1;\r
+ IO_WORD _TDR21 :1;\r
+ IO_WORD _TDR20 :1;\r
+ IO_WORD _TDR19 :1;\r
+ IO_WORD _TDR18 :1;\r
+ IO_WORD _TDR17 :1;\r
+ IO_WORD _TDR16 :1;\r
+ }bit;\r
+ }CUTR1STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _TDR15 :1;\r
+ IO_WORD _TDR14 :1;\r
+ IO_WORD _TDR13 :1;\r
+ IO_WORD _TDR12 :1;\r
+ IO_WORD _TDR11 :1;\r
+ IO_WORD _TDR10 :1;\r
+ IO_WORD _TDR9 :1;\r
+ IO_WORD _TDR8 :1;\r
+ IO_WORD _TDR7 :1;\r
+ IO_WORD _TDR6 :1;\r
+ IO_WORD _TDR5 :1;\r
+ IO_WORD _TDR4 :1;\r
+ IO_WORD _TDR3 :1;\r
+ IO_WORD _TDR2 :1;\r
+ IO_WORD _TDR1 :1;\r
+ IO_WORD _TDR0 :1;\r
+ }bit;\r
+ }CUTR2STR;\r
+typedef union{ /* Clock Modulator */\r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _MP13 :1;\r
+ IO_WORD _MP12 :1;\r
+ IO_WORD _MP11 :1;\r
+ IO_WORD _MP10 :1;\r
+ IO_WORD _MP9 :1;\r
+ IO_WORD _MP8 :1;\r
+ IO_WORD _MP7 :1;\r
+ IO_WORD _MP6 :1;\r
+ IO_WORD _MP5 :1;\r
+ IO_WORD _MP4 :1;\r
+ IO_WORD _MP3 :1;\r
+ IO_WORD _MP2 :1;\r
+ IO_WORD _MP1 :1;\r
+ IO_WORD _MP0 :1;\r
+ }bit;\r
+ }CMPRSTR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _FMODRUN :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _FMOD :1;\r
+ IO_BYTE _PDX :1;\r
+ }bit;\r
+ }CMCRSTR;\r
+typedef union{ /* CAN clock control */\r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CPCKS1 :1;\r
+ IO_BYTE _CPCKS0 :1;\r
+ IO_BYTE _DVC3 :1;\r
+ IO_BYTE _DVC2 :1;\r
+ IO_BYTE _DVC1 :1;\r
+ IO_BYTE _DVC0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :2;\r
+ IO_BYTE _CPCKS :2;\r
+ IO_BYTE _DVC :4;\r
+ }bitc;\r
+ }CANPRESTR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CANCKD5 :1;\r
+ IO_BYTE _CANCKD4 :1;\r
+ IO_BYTE _CANCKD3 :1;\r
+ IO_BYTE _CANCKD2 :1;\r
+ IO_BYTE _CANCKD1 :1;\r
+ IO_BYTE _CANCKD0 :1;\r
+ }bit;\r
+ }CANCKDSTR;\r
+typedef union{ /* LV Detection / Hardware-Watchdog */\r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _LVESEL3 :1;\r
+ IO_BYTE _LVESEL2 :1;\r
+ IO_BYTE _LVESEL1 :1;\r
+ IO_BYTE _LVESEL0 :1;\r
+ IO_BYTE _LVISEL3 :1;\r
+ IO_BYTE _LVISEL2 :1;\r
+ IO_BYTE _LVISEL1 :1;\r
+ IO_BYTE _LVISEL0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE _LVESEL :4;\r
+ IO_BYTE _LVISEL :4;\r
+ }bitc;\r
+ }LVSELSTR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE _LVSEL :1;\r
+ IO_BYTE _LVEPD :1;\r
+ IO_BYTE _LVIPD :1;\r
+ IO_BYTE _LVREN :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _LVIEN :1;\r
+ IO_BYTE _LVIRQ :1;\r
+ }bit;\r
+ }LVDETSTR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ED1 :1;\r
+ IO_BYTE _ED0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ED :2;\r
+ }bitc;\r
+ }HWWDESTR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CL :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _CPUF :1;\r
+ }bit;\r
+ }HWWDSTR;\r
+typedef union{ /* Main-/Sub-Oscillatio Stabilization Timer */\r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _WIF :1;\r
+ IO_BYTE _WIE :1;\r
+ IO_BYTE _WEN :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _WS1 :1;\r
+ IO_BYTE _WS0 :1;\r
+ IO_BYTE _WCL :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _WS :2;\r
+ }bitc;\r
+ }OSCRHSTR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _WIF :1;\r
+ IO_BYTE _WIE :1;\r
+ IO_BYTE _WEN :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _WS1 :1;\r
+ IO_BYTE _WS0 :1;\r
+ IO_BYTE _WCL :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _WS :2;\r
+ }bitc;\r
+ }WPCRHSTR;\r
+typedef union{ /* Main-/Sub-Oscillatio Standby Control */\r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _OSCDS1 :1;\r
+ }bit;\r
+ }OSCCRSTR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _FLASHSEL :1;\r
+ IO_BYTE _MAINSEL :1;\r
+ IO_BYTE _SUBSEL3 :1;\r
+ IO_BYTE _SUBSEL2 :1;\r
+ IO_BYTE _SUBSEL1 :1;\r
+ IO_BYTE _SUBSEL0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :4;\r
+ IO_BYTE _SUBSEL :4;\r
+ }bitc;\r
+ }REGSELSTR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _MSTBO :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _MAINKPEN :1;\r
+ IO_BYTE _MAINDSBL :1;\r
+ }bit;\r
+ }REGCTRSTR;\r
+typedef union{ /* Mode Register */\r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _ROMA :1;\r
+ IO_BYTE _WTH1 :1;\r
+ IO_BYTE _WTH0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _WTH :2;\r
+ }bitc;\r
+ }MODRSTR;\r
+typedef union{ /* R-bus Port Data Direct Read Register */\r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PDRD14STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PDRD15STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PDRD16STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PDRD17STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ }bit;\r
+ }PDRD18STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PDRD19STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PDRD20STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PDRD21STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PDRD22STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PDRD24STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PDRD26STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PDRD27STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PDRD28STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PDRD29STR;\r
+typedef union{ /* R-bus Port Direction Register */\r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }DDR14STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }DDR15STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }DDR16STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }DDR17STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ }bit;\r
+ }DDR18STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }DDR19STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }DDR20STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }DDR21STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }DDR22STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }DDR24STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }DDR26STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }DDR27STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }DDR28STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }DDR29STR;\r
+typedef union{ /* R-bus Port Function Register */\r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PFR14STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PFR15STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PFR16STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PFR17STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ }bit;\r
+ }PFR18STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PFR19STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PFR20STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PFR21STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PFR22STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PFR24STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PFR26STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PFR27STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PFR28STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PFR29STR;\r
+typedef union{ /* R-bus Port Extra Function Register */\r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }EPFR14STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }EPFR15STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ }bit;\r
+ }EPFR16STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ }bit;\r
+ }EPFR18STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ }bit;\r
+ }EPFR19STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ }bit;\r
+ }EPFR20STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ }bit;\r
+ }EPFR21STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }EPFR26STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }EPFR27STR;\r
+typedef union{ /* R-bus Port Output Drive Select Register */\r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PODR14STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PODR15STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PODR16STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PODR17STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ }bit;\r
+ }PODR18STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PODR19STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PODR20STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PODR21STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PODR22STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PODR24STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PODR26STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PODR27STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PODR28STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PODR29STR;\r
+typedef union{ /* R-bus Port Input Level Select Register */\r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PILR14STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PILR15STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PILR16STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PILR17STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ }bit;\r
+ }PILR18STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PILR19STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PILR20STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PILR21STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PILR22STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PILR24STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PILR26STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PILR27STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PILR28STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PILR29STR;\r
+typedef union{ /* R-bus Port Extra Input Level Select Register */\r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }EPILR14STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }EPILR15STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }EPILR16STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }EPILR17STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ }bit;\r
+ }EPILR18STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }EPILR19STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }EPILR20STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }EPILR21STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }EPILR22STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }EPILR24STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }EPILR26STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }EPILR27STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }EPILR28STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }EPILR29STR;\r
+typedef union{ /* R-bus Port Pull-Up/Down Enable Register */\r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PPER14STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PPER15STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PPER16STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PPER17STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ }bit;\r
+ }PPER18STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PPER19STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PPER20STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PPER21STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PPER22STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PPER24STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PPER26STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PPER27STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PPER28STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PPER29STR;\r
+typedef union{ /* R-bus Port Pull-Up/Down Control Register */\r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PPCR14STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PPCR15STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PPCR16STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PPCR17STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ }bit;\r
+ }PPCR18STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ }bit;\r
+ }PPCR19STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PPCR20STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PPCR21STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PPCR22STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PPCR24STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PPCR26STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PPCR27STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PPCR28STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _D7 :1;\r
+ IO_BYTE _D6 :1;\r
+ IO_BYTE _D5 :1;\r
+ IO_BYTE _D4 :1;\r
+ IO_BYTE _D3 :1;\r
+ IO_BYTE _D2 :1;\r
+ IO_BYTE _D1 :1;\r
+ IO_BYTE _D0 :1;\r
+ }bit;\r
+ }PPCR29STR;\r
+typedef union{ /* Flash Memory/I-Cache Control Register */\r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE _ASYNC :1;\r
+ IO_BYTE _FIXE :1;\r
+ IO_BYTE _BIRE :1;\r
+ IO_BYTE _RDYEG :1;\r
+ IO_BYTE _RDY :1;\r
+ IO_BYTE _RDYI :1;\r
+ IO_BYTE _RW16 :1;\r
+ IO_BYTE _LPM :1;\r
+ }bit;\r
+ }FMCSSTR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _LOCK :1;\r
+ IO_BYTE _PHASE :1;\r
+ IO_BYTE _PF2I :1;\r
+ IO_BYTE _RD64 :1;\r
+ }bit;\r
+ }FMCRSTR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _REN :1;\r
+ IO_WORD _TAGE :1;\r
+ IO_WORD _FLUSH :1;\r
+ IO_WORD _DBEN :1;\r
+ IO_WORD _PFEN :1;\r
+ IO_WORD _PFMC :1;\r
+ IO_WORD _LOCK :1;\r
+ IO_WORD _ENAB :1;\r
+ IO_WORD _SIZE1 :1;\r
+ IO_WORD _SIZE0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _SIZE :2;\r
+ }bitc;\r
+ }FCHCRSTR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _WTP1 :1;\r
+ IO_WORD _WTP0 :1;\r
+ IO_WORD _WEXH1 :1;\r
+ IO_WORD _WEXH0 :1;\r
+ IO_WORD _WTC3 :1;\r
+ IO_WORD _WTC2 :1;\r
+ IO_WORD _WTC1 :1;\r
+ IO_WORD _WTC0 :1;\r
+ IO_WORD _FRAM :1;\r
+ IO_WORD _ATD2 :1;\r
+ IO_WORD _ATD1 :1;\r
+ IO_WORD _ATD0 :1;\r
+ IO_WORD _EQ3 :1;\r
+ IO_WORD _EQ2 :1;\r
+ IO_WORD _EQ1 :1;\r
+ IO_WORD _EQ0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_WORD _WTP :2;\r
+ IO_WORD _WEXH :2;\r
+ IO_WORD _WTC :4;\r
+ IO_WORD :1;\r
+ IO_WORD _ATD :3;\r
+ IO_WORD _EQ :4;\r
+ }bitc;\r
+ }FMWTSTR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE _ALEH2 :1;\r
+ IO_BYTE _ALEH1 :1;\r
+ IO_BYTE _ALEH0 :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE _ALEH :3;\r
+ }bitc;\r
+ }FMWT2STR;\r
+typedef union{ \r
+ IO_BYTE byte;\r
+ struct{ \r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _PS2 :1;\r
+ IO_BYTE _PS1 :1;\r
+ IO_BYTE _PS0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE :1;\r
+ IO_BYTE _PS :3;\r
+ }bitc;\r
+ }FMPSSTR;\r
+typedef union{ /* Flash Security Control Register */\r
+ IO_LWORD lword;\r
+ struct{ \r
+ IO_LWORD _CRC31 :1;\r
+ IO_LWORD _CRC30 :1;\r
+ IO_LWORD _CRC29 :1;\r
+ IO_LWORD _CRC28 :1;\r
+ IO_LWORD _CRC27 :1;\r
+ IO_LWORD _CRC26 :1;\r
+ IO_LWORD _CRC25 :1;\r
+ IO_LWORD _CRC24 :1;\r
+ IO_LWORD _CRC23 :1;\r
+ IO_LWORD _CRC22 :1;\r
+ IO_LWORD _CRC21 :1;\r
+ IO_LWORD _CRC20 :1;\r
+ IO_LWORD _CRC19 :1;\r
+ IO_LWORD _CRC18 :1;\r
+ IO_LWORD _CRC17 :1;\r
+ IO_LWORD _CRC16 :1;\r
+ IO_LWORD _CRC15 :1;\r
+ IO_LWORD _CRC14 :1;\r
+ IO_LWORD _CRC13 :1;\r
+ IO_LWORD _CRC12 :1;\r
+ IO_LWORD _CRC11 :1;\r
+ IO_LWORD _CRC10 :1;\r
+ IO_LWORD _CRC9 :1;\r
+ IO_LWORD _CRC8 :1;\r
+ IO_LWORD _CRC7 :1;\r
+ IO_LWORD _CRC6 :1;\r
+ IO_LWORD _CRC5 :1;\r
+ IO_LWORD _CRC4 :1;\r
+ IO_LWORD _CRC3 :1;\r
+ IO_LWORD _CRC2 :1;\r
+ IO_LWORD _CRC1 :1;\r
+ IO_LWORD _CRC0 :1;\r
+ }bit;\r
+ }FSCR0STR;\r
+typedef union{ \r
+ IO_LWORD lword;\r
+ struct{ \r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD _RDY :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD _CSZ3 :1;\r
+ IO_LWORD _CSZ2 :1;\r
+ IO_LWORD _CSZ1 :1;\r
+ IO_LWORD _CSZ0 :1;\r
+ IO_LWORD _CSA15 :1;\r
+ IO_LWORD _CSA14 :1;\r
+ IO_LWORD _CSA13 :1;\r
+ IO_LWORD _CSA12 :1;\r
+ IO_LWORD _CSA11 :1;\r
+ IO_LWORD _CSA10 :1;\r
+ IO_LWORD _CSA9 :1;\r
+ IO_LWORD _CSA8 :1;\r
+ IO_LWORD _CSA7 :1;\r
+ IO_LWORD _CSA6 :1;\r
+ IO_LWORD _CSA5 :1;\r
+ IO_LWORD _CSA4 :1;\r
+ IO_LWORD _CSA3 :1;\r
+ IO_LWORD _CSA2 :1;\r
+ IO_LWORD _CSA1 :1;\r
+ IO_LWORD _CSA0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD _CSZ :4;\r
+ }bitc;\r
+ }FSCR1STR;\r
+typedef union{ /* CAN 4 Control Register */\r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _Test :1;\r
+ IO_WORD _CCE :1;\r
+ IO_WORD _DAR :1;\r
+ IO_WORD :1;\r
+ IO_WORD _EIE :1;\r
+ IO_WORD _SIE :1;\r
+ IO_WORD _IE :1;\r
+ IO_WORD _Init :1;\r
+ }bit;\r
+ }CTRLR4STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _BOff :1;\r
+ IO_WORD _EWarn :1;\r
+ IO_WORD _EPass :1;\r
+ IO_WORD _RxOK :1;\r
+ IO_WORD _TxOK :1;\r
+ IO_WORD _LEC2 :1;\r
+ IO_WORD _LEC1 :1;\r
+ IO_WORD _LEC0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _LEC :3;\r
+ }bitc;\r
+ }STATR4STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _RP :1;\r
+ IO_WORD _REC6 :1;\r
+ IO_WORD _REC5 :1;\r
+ IO_WORD _REC4 :1;\r
+ IO_WORD _REC3 :1;\r
+ IO_WORD _REC2 :1;\r
+ IO_WORD _REC1 :1;\r
+ IO_WORD _REC0 :1;\r
+ IO_WORD _TEC7 :1;\r
+ IO_WORD _TEC6 :1;\r
+ IO_WORD _TEC5 :1;\r
+ IO_WORD _TEC4 :1;\r
+ IO_WORD _TEC3 :1;\r
+ IO_WORD _TEC2 :1;\r
+ IO_WORD _TEC1 :1;\r
+ IO_WORD _TEC0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_WORD :1;\r
+ IO_WORD _REC :7;\r
+ IO_WORD _TEC :8;\r
+ }bitc;\r
+ }ERRCNT4STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD :1;\r
+ IO_WORD _Tseg22 :1;\r
+ IO_WORD _Tseg21 :1;\r
+ IO_WORD _Tseg20 :1;\r
+ IO_WORD _Tseg13 :1;\r
+ IO_WORD _Tseg12 :1;\r
+ IO_WORD _Tseg11 :1;\r
+ IO_WORD _Tseg10 :1;\r
+ IO_WORD _SJW1 :1;\r
+ IO_WORD _SJW0 :1;\r
+ IO_WORD _BRP5 :1;\r
+ IO_WORD _BRP4 :1;\r
+ IO_WORD _BRP3 :1;\r
+ IO_WORD _BRP2 :1;\r
+ IO_WORD _BRP1 :1;\r
+ IO_WORD _BRP0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_WORD :1;\r
+ IO_WORD _Tseg2 :3;\r
+ IO_WORD _Tseg1 :4;\r
+ IO_WORD _SJW :2;\r
+ IO_WORD _BRP :6;\r
+ }bitc;\r
+ }BTR4STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _Rx :1;\r
+ IO_WORD _Tx1 :1;\r
+ IO_WORD _Tx0 :1;\r
+ IO_WORD _LBack :1;\r
+ IO_WORD _Silent :1;\r
+ IO_WORD _Basic :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ }bit;\r
+ struct{\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _Tx :2;\r
+ }bitc;\r
+ }TESTR4STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _BRPE3 :1;\r
+ IO_WORD _BRPE2 :1;\r
+ IO_WORD _BRPE1 :1;\r
+ IO_WORD _BRPE0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _BRPE :4;\r
+ }bitc;\r
+ }BRPER4STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ }bit;\r
+ }BRPE4STR;\r
+typedef union{ /* CAN 4 IF 1 */\r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _Busy :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _MN5 :1;\r
+ IO_WORD _MN4 :1;\r
+ IO_WORD _MN3 :1;\r
+ IO_WORD _MN2 :1;\r
+ IO_WORD _MN1 :1;\r
+ IO_WORD _MN0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _MN :6;\r
+ }bitc;\r
+ }IF1CREQ4STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _WR :1;\r
+ IO_WORD _Mask :1;\r
+ IO_WORD _Arb :1;\r
+ IO_WORD _Control :1;\r
+ IO_WORD _CIP :1;\r
+ IO_WORD _TxReq :1;\r
+ IO_WORD _DataA :1;\r
+ IO_WORD _DataB :1;\r
+ }bit;\r
+ }IF1CMSK4STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _MXtd :1;\r
+ IO_WORD _MDir :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ }bit;\r
+ }IF1MSK24STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _MsgVal :1;\r
+ IO_WORD _Xtd :1;\r
+ IO_WORD _DIR :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ }bit;\r
+ }IF1ARB24STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _NewDat :1;\r
+ IO_WORD _MsgLst :1;\r
+ IO_WORD _IntPnd :1;\r
+ IO_WORD _UMask :1;\r
+ IO_WORD _TxIE :1;\r
+ IO_WORD _RxIE :1;\r
+ IO_WORD _RmtEn :1;\r
+ IO_WORD _TxRqst :1;\r
+ IO_WORD _EoB :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _DLC3 :1;\r
+ IO_WORD _DLC2 :1;\r
+ IO_WORD _DLC1 :1;\r
+ IO_WORD _DLC0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _DLC :4;\r
+ }bitc;\r
+ }IF1MCTR4STR;\r
+typedef union{ /* CAN 4 IF 2 */\r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _Busy :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _MN5 :1;\r
+ IO_WORD _MN4 :1;\r
+ IO_WORD _MN3 :1;\r
+ IO_WORD _MN2 :1;\r
+ IO_WORD _MN1 :1;\r
+ IO_WORD _MN0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _MN :6;\r
+ }bitc;\r
+ }IF2CREQ4STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _WR :1;\r
+ IO_WORD _Mask :1;\r
+ IO_WORD _Arb :1;\r
+ IO_WORD _Control :1;\r
+ IO_WORD _CIP :1;\r
+ IO_WORD _TxReq :1;\r
+ IO_WORD _DataA :1;\r
+ IO_WORD _DataB :1;\r
+ }bit;\r
+ }IF2CMSK4STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _MXtd :1;\r
+ IO_WORD _MDir :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ }bit;\r
+ }IF2MSK24STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _MsgVal :1;\r
+ IO_WORD _Xtd :1;\r
+ IO_WORD _DIR :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ }bit;\r
+ }IF2ARB24STR;\r
+typedef union{ \r
+ IO_WORD word;\r
+ struct{ \r
+ IO_WORD _NewDat :1;\r
+ IO_WORD _MsgLst :1;\r
+ IO_WORD _IntPnd :1;\r
+ IO_WORD _UMask :1;\r
+ IO_WORD _TxIE :1;\r
+ IO_WORD _RxIE :1;\r
+ IO_WORD _RmtEn :1;\r
+ IO_WORD _TxRqst :1;\r
+ IO_WORD _EoB :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _DLC3 :1;\r
+ IO_WORD _DLC2 :1;\r
+ IO_WORD _DLC1 :1;\r
+ IO_WORD _DLC0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD :1;\r
+ IO_WORD _DLC :4;\r
+ }bitc;\r
+ }IF2MCTR4STR;\r
+typedef union{ /* EDSU/MPU Registers */\r
+ IO_LWORD lword;\r
+ struct{ \r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD _SR :1;\r
+ IO_LWORD _SW :1;\r
+ IO_LWORD _SX :1;\r
+ IO_LWORD _UR :1;\r
+ IO_LWORD _UW :1;\r
+ IO_LWORD _UX :1;\r
+ IO_LWORD _FCPU :1;\r
+ IO_LWORD _FDMA :1;\r
+ IO_LWORD _EEMM :1;\r
+ IO_LWORD _PFD :1;\r
+ IO_LWORD _SINT1 :1;\r
+ IO_LWORD _SINT0 :1;\r
+ IO_LWORD _EINT1 :1;\r
+ IO_LWORD _EINT0 :1;\r
+ IO_LWORD _EINTT :1;\r
+ IO_LWORD _EINTR :1;\r
+ }bit;\r
+ struct{\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD _SINT :2;\r
+ IO_LWORD _EINT :2;\r
+ }bitc;\r
+ }BCTRLSTR;\r
+typedef union{ \r
+ IO_LWORD lword;\r
+ struct{ \r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD _IDX4 :1;\r
+ IO_LWORD _IDX3 :1;\r
+ IO_LWORD _IDX2 :1;\r
+ IO_LWORD _IDX1 :1;\r
+ IO_LWORD _IDX0 :1;\r
+ IO_LWORD _CDMA :1;\r
+ IO_LWORD _CSZ1 :1;\r
+ IO_LWORD _CSZ0 :1;\r
+ IO_LWORD _CRW1 :1;\r
+ IO_LWORD _CRW0 :1;\r
+ IO_LWORD _PV :1;\r
+ IO_LWORD _RST :1;\r
+ IO_LWORD _INT1 :1;\r
+ IO_LWORD _INT0 :1;\r
+ IO_LWORD _INTT :1;\r
+ IO_LWORD _INTR :1;\r
+ }bit;\r
+ struct{\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD _IDX :5;\r
+ IO_LWORD :1;\r
+ IO_LWORD _CSZ :2;\r
+ IO_LWORD _CRW :2;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD _INT :2;\r
+ }bitc;\r
+ }BSTATSTR;\r
+typedef union{ \r
+ IO_LWORD lword;\r
+ struct{ \r
+ IO_LWORD _BD31 :1;\r
+ IO_LWORD _BD30 :1;\r
+ IO_LWORD _BD29 :1;\r
+ IO_LWORD _BD28 :1;\r
+ IO_LWORD _BD27 :1;\r
+ IO_LWORD _BD26 :1;\r
+ IO_LWORD _BD25 :1;\r
+ IO_LWORD _BD24 :1;\r
+ IO_LWORD _BD23 :1;\r
+ IO_LWORD _BD22 :1;\r
+ IO_LWORD _BD21 :1;\r
+ IO_LWORD _BD20 :1;\r
+ IO_LWORD _BD19 :1;\r
+ IO_LWORD _BD18 :1;\r
+ IO_LWORD _BD17 :1;\r
+ IO_LWORD _BD16 :1;\r
+ IO_LWORD _BD15 :1;\r
+ IO_LWORD _BD14 :1;\r
+ IO_LWORD _BD13 :1;\r
+ IO_LWORD _BD12 :1;\r
+ IO_LWORD _BD11 :1;\r
+ IO_LWORD _BD10 :1;\r
+ IO_LWORD _BD9 :1;\r
+ IO_LWORD _BD8 :1;\r
+ IO_LWORD _BD7 :1;\r
+ IO_LWORD _BD6 :1;\r
+ IO_LWORD _BD5 :1;\r
+ IO_LWORD _BD4 :1;\r
+ IO_LWORD _BD3 :1;\r
+ IO_LWORD _BD2 :1;\r
+ IO_LWORD _BD1 :1;\r
+ IO_LWORD _BD0 :1;\r
+ }bit;\r
+ }BIRQSTR;\r
+typedef union{ \r
+ IO_LWORD lword;\r
+ struct{ \r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD _SRX1 :1;\r
+ IO_LWORD _SW1 :1;\r
+ IO_LWORD _SRX0 :1;\r
+ IO_LWORD _SW0 :1;\r
+ IO_LWORD _URX1 :1;\r
+ IO_LWORD _UW1 :1;\r
+ IO_LWORD _URX0 :1;\r
+ IO_LWORD _UW0 :1;\r
+ IO_LWORD _MPE :1;\r
+ IO_LWORD _COMB :1;\r
+ IO_LWORD _CTC1 :1;\r
+ IO_LWORD _CTC0 :1;\r
+ IO_LWORD _OBS1 :1;\r
+ IO_LWORD _OBS0 :1;\r
+ IO_LWORD _OBT1 :1;\r
+ IO_LWORD _OBT0 :1;\r
+ IO_LWORD _EP3 :1;\r
+ IO_LWORD _EP2 :1;\r
+ IO_LWORD _EP1 :1;\r
+ IO_LWORD _EP0 :1;\r
+ IO_LWORD _EM1 :1;\r
+ IO_LWORD _EM0 :1;\r
+ IO_LWORD _ER1 :1;\r
+ IO_LWORD _ER0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD _CTC :2;\r
+ IO_LWORD _OBS :2;\r
+ IO_LWORD _OBT :2;\r
+ IO_LWORD _EP :4;\r
+ IO_LWORD _EM :2;\r
+ IO_LWORD _ER :2;\r
+ }bitc;\r
+ }BCR0STR;\r
+typedef union{ \r
+ IO_LWORD lword;\r
+ struct{ \r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD _SRX1 :1;\r
+ IO_LWORD _SW1 :1;\r
+ IO_LWORD _SRX0 :1;\r
+ IO_LWORD _SW0 :1;\r
+ IO_LWORD _URX1 :1;\r
+ IO_LWORD _UW1 :1;\r
+ IO_LWORD _URX0 :1;\r
+ IO_LWORD _UW0 :1;\r
+ IO_LWORD _MPE :1;\r
+ IO_LWORD _COMB :1;\r
+ IO_LWORD _CTC1 :1;\r
+ IO_LWORD _CTC0 :1;\r
+ IO_LWORD _OBS1 :1;\r
+ IO_LWORD _OBS0 :1;\r
+ IO_LWORD _OBT1 :1;\r
+ IO_LWORD _OBT0 :1;\r
+ IO_LWORD _EP3 :1;\r
+ IO_LWORD _EP2 :1;\r
+ IO_LWORD _EP1 :1;\r
+ IO_LWORD _EP0 :1;\r
+ IO_LWORD _EM1 :1;\r
+ IO_LWORD _EM0 :1;\r
+ IO_LWORD _ER1 :1;\r
+ IO_LWORD _ER0 :1;\r
+ }bit;\r
+ struct{\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD :1;\r
+ IO_LWORD _CTC :2;\r
+ IO_LWORD _OBS :2;\r
+ IO_LWORD _OBT :2;\r
+ IO_LWORD _EP :4;\r
+ IO_LWORD _EM :2;\r
+ IO_LWORD _ER :2;\r
+ }bitc;\r
+ }BCR1STR;\r
+\r
+/* C-DECLARATIONS */\r
+\r
+__IO_EXTERN __io PDR14STR pdr14; /* Port Data Register */\r
+#define PDR14 pdr14.byte\r
+#define PDR14_D7 pdr14.bit._D7\r
+#define PDR14_D6 pdr14.bit._D6\r
+#define PDR14_D5 pdr14.bit._D5\r
+#define PDR14_D4 pdr14.bit._D4\r
+#define PDR14_D3 pdr14.bit._D3\r
+#define PDR14_D2 pdr14.bit._D2\r
+#define PDR14_D1 pdr14.bit._D1\r
+#define PDR14_D0 pdr14.bit._D0\r
+__IO_EXTERN __io PDR15STR pdr15; \r
+#define PDR15 pdr15.byte\r
+#define PDR15_D7 pdr15.bit._D7\r
+#define PDR15_D6 pdr15.bit._D6\r
+#define PDR15_D5 pdr15.bit._D5\r
+#define PDR15_D4 pdr15.bit._D4\r
+#define PDR15_D3 pdr15.bit._D3\r
+#define PDR15_D2 pdr15.bit._D2\r
+#define PDR15_D1 pdr15.bit._D1\r
+#define PDR15_D0 pdr15.bit._D0\r
+__IO_EXTERN __io PDR16STR pdr16; \r
+#define PDR16 pdr16.byte\r
+#define PDR16_D7 pdr16.bit._D7\r
+#define PDR16_D6 pdr16.bit._D6\r
+#define PDR16_D5 pdr16.bit._D5\r
+#define PDR16_D4 pdr16.bit._D4\r
+#define PDR16_D3 pdr16.bit._D3\r
+#define PDR16_D2 pdr16.bit._D2\r
+#define PDR16_D1 pdr16.bit._D1\r
+#define PDR16_D0 pdr16.bit._D0\r
+__IO_EXTERN __io PDR17STR pdr17; \r
+#define PDR17 pdr17.byte\r
+#define PDR17_D7 pdr17.bit._D7\r
+#define PDR17_D6 pdr17.bit._D6\r
+#define PDR17_D5 pdr17.bit._D5\r
+#define PDR17_D4 pdr17.bit._D4\r
+#define PDR17_D3 pdr17.bit._D3\r
+#define PDR17_D2 pdr17.bit._D2\r
+#define PDR17_D1 pdr17.bit._D1\r
+#define PDR17_D0 pdr17.bit._D0\r
+__IO_EXTERN __io PDR18STR pdr18; \r
+#define PDR18 pdr18.byte\r
+#define PDR18_D6 pdr18.bit._D6\r
+#define PDR18_D2 pdr18.bit._D2\r
+__IO_EXTERN __io PDR19STR pdr19; \r
+#define PDR19 pdr19.byte\r
+#define PDR19_D6 pdr19.bit._D6\r
+#define PDR19_D2 pdr19.bit._D2\r
+#define PDR19_D1 pdr19.bit._D1\r
+#define PDR19_D0 pdr19.bit._D0\r
+__IO_EXTERN __io PDR20STR pdr20; \r
+#define PDR20 pdr20.byte\r
+#define PDR20_D7 pdr20.bit._D7\r
+#define PDR20_D6 pdr20.bit._D6\r
+#define PDR20_D5 pdr20.bit._D5\r
+#define PDR20_D4 pdr20.bit._D4\r
+#define PDR20_D3 pdr20.bit._D3\r
+#define PDR20_D2 pdr20.bit._D2\r
+#define PDR20_D1 pdr20.bit._D1\r
+#define PDR20_D0 pdr20.bit._D0\r
+__IO_EXTERN __io PDR21STR pdr21; \r
+#define PDR21 pdr21.byte\r
+#define PDR21_D7 pdr21.bit._D7\r
+#define PDR21_D6 pdr21.bit._D6\r
+#define PDR21_D5 pdr21.bit._D5\r
+#define PDR21_D4 pdr21.bit._D4\r
+#define PDR21_D3 pdr21.bit._D3\r
+#define PDR21_D2 pdr21.bit._D2\r
+#define PDR21_D1 pdr21.bit._D1\r
+#define PDR21_D0 pdr21.bit._D0\r
+__IO_EXTERN __io PDR22STR pdr22; \r
+#define PDR22 pdr22.byte\r
+#define PDR22_D5 pdr22.bit._D5\r
+#define PDR22_D4 pdr22.bit._D4\r
+#define PDR22_D1 pdr22.bit._D1\r
+#define PDR22_D0 pdr22.bit._D0\r
+__IO_EXTERN __io PDR24STR pdr24; \r
+#define PDR24 pdr24.byte\r
+#define PDR24_D7 pdr24.bit._D7\r
+#define PDR24_D6 pdr24.bit._D6\r
+#define PDR24_D5 pdr24.bit._D5\r
+#define PDR24_D4 pdr24.bit._D4\r
+#define PDR24_D3 pdr24.bit._D3\r
+#define PDR24_D2 pdr24.bit._D2\r
+#define PDR24_D1 pdr24.bit._D1\r
+#define PDR24_D0 pdr24.bit._D0\r
+__IO_EXTERN __io PDR26STR pdr26; \r
+#define PDR26 pdr26.byte\r
+#define PDR26_D1 pdr26.bit._D1\r
+#define PDR26_D0 pdr26.bit._D0\r
+__IO_EXTERN __io PDR27STR pdr27; \r
+#define PDR27 pdr27.byte\r
+#define PDR27_D7 pdr27.bit._D7\r
+#define PDR27_D6 pdr27.bit._D6\r
+#define PDR27_D5 pdr27.bit._D5\r
+#define PDR27_D4 pdr27.bit._D4\r
+#define PDR27_D3 pdr27.bit._D3\r
+#define PDR27_D2 pdr27.bit._D2\r
+#define PDR27_D1 pdr27.bit._D1\r
+#define PDR27_D0 pdr27.bit._D0\r
+__IO_EXTERN __io PDR28STR pdr28; \r
+#define PDR28 pdr28.byte\r
+#define PDR28_D7 pdr28.bit._D7\r
+#define PDR28_D6 pdr28.bit._D6\r
+#define PDR28_D5 pdr28.bit._D5\r
+#define PDR28_D4 pdr28.bit._D4\r
+#define PDR28_D3 pdr28.bit._D3\r
+#define PDR28_D2 pdr28.bit._D2\r
+#define PDR28_D1 pdr28.bit._D1\r
+#define PDR28_D0 pdr28.bit._D0\r
+__IO_EXTERN __io PDR29STR pdr29; \r
+#define PDR29 pdr29.byte\r
+#define PDR29_D7 pdr29.bit._D7\r
+#define PDR29_D6 pdr29.bit._D6\r
+#define PDR29_D5 pdr29.bit._D5\r
+#define PDR29_D4 pdr29.bit._D4\r
+#define PDR29_D3 pdr29.bit._D3\r
+#define PDR29_D2 pdr29.bit._D2\r
+#define PDR29_D1 pdr29.bit._D1\r
+#define PDR29_D0 pdr29.bit._D0\r
+__IO_EXTERN __io EIRR0STR eirr0; /* External Interrupt 0-7 */\r
+#define EIRR0 eirr0.byte\r
+#define EIRR0_ER7 eirr0.bit._ER7\r
+#define EIRR0_ER6 eirr0.bit._ER6\r
+#define EIRR0_ER5 eirr0.bit._ER5\r
+#define EIRR0_ER4 eirr0.bit._ER4\r
+#define EIRR0_ER3 eirr0.bit._ER3\r
+#define EIRR0_ER2 eirr0.bit._ER2\r
+#define EIRR0_ER1 eirr0.bit._ER1\r
+#define EIRR0_ER0 eirr0.bit._ER0\r
+__IO_EXTERN __io ENIR0STR enir0; \r
+#define ENIR0 enir0.byte\r
+#define ENIR0_EN7 enir0.bit._EN7\r
+#define ENIR0_EN6 enir0.bit._EN6\r
+#define ENIR0_EN5 enir0.bit._EN5\r
+#define ENIR0_EN4 enir0.bit._EN4\r
+#define ENIR0_EN3 enir0.bit._EN3\r
+#define ENIR0_EN2 enir0.bit._EN2\r
+#define ENIR0_EN1 enir0.bit._EN1\r
+#define ENIR0_EN0 enir0.bit._EN0\r
+__IO_EXTERN __io ELVR0STR elvr0; \r
+#define ELVR0 elvr0.word\r
+#define ELVR0_LB7 elvr0.bit._LB7\r
+#define ELVR0_LA7 elvr0.bit._LA7\r
+#define ELVR0_LB6 elvr0.bit._LB6\r
+#define ELVR0_LA6 elvr0.bit._LA6\r
+#define ELVR0_LB5 elvr0.bit._LB5\r
+#define ELVR0_LA5 elvr0.bit._LA5\r
+#define ELVR0_LB4 elvr0.bit._LB4\r
+#define ELVR0_LA4 elvr0.bit._LA4\r
+#define ELVR0_LB3 elvr0.bit._LB3\r
+#define ELVR0_LA3 elvr0.bit._LA3\r
+#define ELVR0_LB2 elvr0.bit._LB2\r
+#define ELVR0_LA2 elvr0.bit._LA2\r
+#define ELVR0_LB1 elvr0.bit._LB1\r
+#define ELVR0_LA1 elvr0.bit._LA1\r
+#define ELVR0_LB0 elvr0.bit._LB0\r
+#define ELVR0_LA0 elvr0.bit._LA0\r
+__IO_EXTERN __io EIRR1STR eirr1; /* External Interrupt 8-15 */\r
+#define EIRR1 eirr1.byte\r
+#define EIRR1_ER15 eirr1.bit._ER15\r
+#define EIRR1_ER14 eirr1.bit._ER14\r
+#define EIRR1_ER13 eirr1.bit._ER13\r
+#define EIRR1_ER12 eirr1.bit._ER12\r
+#define EIRR1_ER11 eirr1.bit._ER11\r
+#define EIRR1_ER10 eirr1.bit._ER10\r
+#define EIRR1_ER9 eirr1.bit._ER9\r
+#define EIRR1_ER8 eirr1.bit._ER8\r
+__IO_EXTERN __io ENIR1STR enir1; \r
+#define ENIR1 enir1.byte\r
+#define ENIR1_EN15 enir1.bit._EN15\r
+#define ENIR1_EN14 enir1.bit._EN14\r
+#define ENIR1_EN13 enir1.bit._EN13\r
+#define ENIR1_EN12 enir1.bit._EN12\r
+#define ENIR1_EN11 enir1.bit._EN11\r
+#define ENIR1_EN10 enir1.bit._EN10\r
+#define ENIR1_EN9 enir1.bit._EN9\r
+#define ENIR1_EN8 enir1.bit._EN8\r
+__IO_EXTERN __io ELVR1STR elvr1; \r
+#define ELVR1 elvr1.word\r
+#define ELVR1_LB15 elvr1.bit._LB15\r
+#define ELVR1_LA15 elvr1.bit._LA15\r
+#define ELVR1_LB14 elvr1.bit._LB14\r
+#define ELVR1_LA14 elvr1.bit._LA14\r
+#define ELVR1_LB13 elvr1.bit._LB13\r
+#define ELVR1_LA13 elvr1.bit._LA13\r
+#define ELVR1_LB12 elvr1.bit._LB12\r
+#define ELVR1_LA12 elvr1.bit._LA12\r
+#define ELVR1_LB11 elvr1.bit._LB11\r
+#define ELVR1_LA11 elvr1.bit._LA11\r
+#define ELVR1_LB10 elvr1.bit._LB10\r
+#define ELVR1_LA10 elvr1.bit._LA10\r
+#define ELVR1_LB9 elvr1.bit._LB9\r
+#define ELVR1_LA9 elvr1.bit._LA9\r
+#define ELVR1_LB8 elvr1.bit._LB8\r
+#define ELVR1_LA8 elvr1.bit._LA8\r
+__IO_EXTERN __io DICRSTR dicr; /* DLYI/I-unit */\r
+#define DICR dicr.byte\r
+#define DICR_DLYI dicr.bit._DLYI\r
+__IO_EXTERN __io HRCLSTR hrcl; \r
+#define HRCL hrcl.byte\r
+#define HRCL_MHALTI hrcl.bit._MHALTI\r
+#define HRCL_LVL4 hrcl.bit._LVL4\r
+#define HRCL_LVL3 hrcl.bit._LVL3\r
+#define HRCL_LVL2 hrcl.bit._LVL2\r
+#define HRCL_LVL1 hrcl.bit._LVL1\r
+#define HRCL_LVL0 hrcl.bit._LVL0\r
+#define HRCL_LVL hrcl.bitc._LVL\r
+__IO_EXTERN __io IO_WORD rbsync; /* R-Bus Sync */\r
+#define RBSYNC rbsync\r
+__IO_EXTERN __io SCR00STR scr00; /* USART (LIN) 0 */\r
+#define SCR00 scr00.byte\r
+#define SCR00_PEN scr00.bit._PEN\r
+#define SCR00_P scr00.bit._P\r
+#define SCR00_SBL scr00.bit._SBL\r
+#define SCR00_CL scr00.bit._CL\r
+#define SCR00_AD scr00.bit._AD\r
+#define SCR00_CRE scr00.bit._CRE\r
+#define SCR00_RXE scr00.bit._RXE\r
+#define SCR00_TXE scr00.bit._TXE\r
+__IO_EXTERN __io SMR00STR smr00; \r
+#define SMR00 smr00.byte\r
+#define SMR00_MD1 smr00.bit._MD1\r
+#define SMR00_MD0 smr00.bit._MD0\r
+#define SMR00_OTO smr00.bit._OTO\r
+#define SMR00_EXT smr00.bit._EXT\r
+#define SMR00_REST smr00.bit._REST\r
+#define SMR00_UPCL smr00.bit._UPCL\r
+#define SMR00_SCKE smr00.bit._SCKE\r
+#define SMR00_SOE smr00.bit._SOE\r
+#define SMR00_MD smr00.bitc._MD\r
+__IO_EXTERN __io SSR00STR ssr00; \r
+#define SSR00 ssr00.byte\r
+#define SSR00_PE ssr00.bit._PE\r
+#define SSR00_ORE ssr00.bit._ORE\r
+#define SSR00_FRE ssr00.bit._FRE\r
+#define SSR00_RDRF ssr00.bit._RDRF\r
+#define SSR00_TDRE ssr00.bit._TDRE\r
+#define SSR00_BDS ssr00.bit._BDS\r
+#define SSR00_RIE ssr00.bit._RIE\r
+#define SSR00_TIE ssr00.bit._TIE\r
+__IO_EXTERN __io IO_BYTE rdr00; \r
+#define RDR00 rdr00\r
+__IO_EXTERN __io IO_BYTE tdr00; \r
+#define TDR00 tdr00\r
+__IO_EXTERN __io ESCR00STR escr00; \r
+#define ESCR00 escr00.byte\r
+#define ESCR00_LBIE escr00.bit._LBIE\r
+#define ESCR00_LBD escr00.bit._LBD\r
+#define ESCR00_LBL1 escr00.bit._LBL1\r
+#define ESCR00_LBL0 escr00.bit._LBL0\r
+#define ESCR00_SOPE escr00.bit._SOPE\r
+#define ESCR00_SIOP escr00.bit._SIOP\r
+#define ESCR00_CCO escr00.bit._CCO\r
+#define ESCR00_SCES escr00.bit._SCES\r
+#define ESCR00_LBL escr00.bitc._LBL\r
+__IO_EXTERN __io ECCR00STR eccr00; \r
+#define ECCR00 eccr00.byte\r
+#define ECCR00_INV eccr00.bit._INV\r
+#define ECCR00_LBR eccr00.bit._LBR\r
+#define ECCR00_MS eccr00.bit._MS\r
+#define ECCR00_SCDE eccr00.bit._SCDE\r
+#define ECCR00_SSM eccr00.bit._SSM\r
+#define ECCR00_BIE eccr00.bit._BIE\r
+#define ECCR00_RBI eccr00.bit._RBI\r
+#define ECCR00_TBI eccr00.bit._TBI\r
+__IO_EXTERN __io SCR01STR scr01; /* USART (LIN) 1 */\r
+#define SCR01 scr01.byte\r
+#define SCR01_PEN scr01.bit._PEN\r
+#define SCR01_P scr01.bit._P\r
+#define SCR01_SBL scr01.bit._SBL\r
+#define SCR01_CL scr01.bit._CL\r
+#define SCR01_AD scr01.bit._AD\r
+#define SCR01_CRE scr01.bit._CRE\r
+#define SCR01_RXE scr01.bit._RXE\r
+#define SCR01_TXE scr01.bit._TXE\r
+__IO_EXTERN __io SMR01STR smr01; \r
+#define SMR01 smr01.byte\r
+#define SMR01_MD1 smr01.bit._MD1\r
+#define SMR01_MD0 smr01.bit._MD0\r
+#define SMR01_OTO smr01.bit._OTO\r
+#define SMR01_EXT smr01.bit._EXT\r
+#define SMR01_REST smr01.bit._REST\r
+#define SMR01_UPCL smr01.bit._UPCL\r
+#define SMR01_SCKE smr01.bit._SCKE\r
+#define SMR01_SOE smr01.bit._SOE\r
+#define SMR01_MD smr01.bitc._MD\r
+__IO_EXTERN __io SSR01STR ssr01; \r
+#define SSR01 ssr01.byte\r
+#define SSR01_PE ssr01.bit._PE\r
+#define SSR01_ORE ssr01.bit._ORE\r
+#define SSR01_FRE ssr01.bit._FRE\r
+#define SSR01_RDRF ssr01.bit._RDRF\r
+#define SSR01_TDRE ssr01.bit._TDRE\r
+#define SSR01_BDS ssr01.bit._BDS\r
+#define SSR01_RIE ssr01.bit._RIE\r
+#define SSR01_TIE ssr01.bit._TIE\r
+__IO_EXTERN __io IO_BYTE rdr01; \r
+#define RDR01 rdr01\r
+__IO_EXTERN __io IO_BYTE tdr01; \r
+#define TDR01 tdr01\r
+__IO_EXTERN __io ESCR01STR escr01; \r
+#define ESCR01 escr01.byte\r
+#define ESCR01_LBIE escr01.bit._LBIE\r
+#define ESCR01_LBD escr01.bit._LBD\r
+#define ESCR01_LBL1 escr01.bit._LBL1\r
+#define ESCR01_LBL0 escr01.bit._LBL0\r
+#define ESCR01_SOPE escr01.bit._SOPE\r
+#define ESCR01_SIOP escr01.bit._SIOP\r
+#define ESCR01_CCO escr01.bit._CCO\r
+#define ESCR01_SCES escr01.bit._SCES\r
+#define ESCR01_LBL escr01.bitc._LBL\r
+__IO_EXTERN __io ECCR01STR eccr01; \r
+#define ECCR01 eccr01.byte\r
+#define ECCR01_INV eccr01.bit._INV\r
+#define ECCR01_LBR eccr01.bit._LBR\r
+#define ECCR01_MS eccr01.bit._MS\r
+#define ECCR01_SCDE eccr01.bit._SCDE\r
+#define ECCR01_SSM eccr01.bit._SSM\r
+#define ECCR01_BIE eccr01.bit._BIE\r
+#define ECCR01_RBI eccr01.bit._RBI\r
+#define ECCR01_TBI eccr01.bit._TBI\r
+__IO_EXTERN __io SCR02STR scr02; /* USART (LIN) 2 */\r
+#define SCR02 scr02.byte\r
+#define SCR02_PEN scr02.bit._PEN\r
+#define SCR02_P scr02.bit._P\r
+#define SCR02_SBL scr02.bit._SBL\r
+#define SCR02_CL scr02.bit._CL\r
+#define SCR02_AD scr02.bit._AD\r
+#define SCR02_CRE scr02.bit._CRE\r
+#define SCR02_RXE scr02.bit._RXE\r
+#define SCR02_TXE scr02.bit._TXE\r
+__IO_EXTERN __io SMR02STR smr02; \r
+#define SMR02 smr02.byte\r
+#define SMR02_MD1 smr02.bit._MD1\r
+#define SMR02_MD0 smr02.bit._MD0\r
+#define SMR02_OTO smr02.bit._OTO\r
+#define SMR02_EXT smr02.bit._EXT\r
+#define SMR02_REST smr02.bit._REST\r
+#define SMR02_UPCL smr02.bit._UPCL\r
+#define SMR02_SCKE smr02.bit._SCKE\r
+#define SMR02_SOE smr02.bit._SOE\r
+#define SMR02_MD smr02.bitc._MD\r
+__IO_EXTERN __io SSR02STR ssr02; \r
+#define SSR02 ssr02.byte\r
+#define SSR02_PE ssr02.bit._PE\r
+#define SSR02_ORE ssr02.bit._ORE\r
+#define SSR02_FRE ssr02.bit._FRE\r
+#define SSR02_RDRF ssr02.bit._RDRF\r
+#define SSR02_TDRE ssr02.bit._TDRE\r
+#define SSR02_BDS ssr02.bit._BDS\r
+#define SSR02_RIE ssr02.bit._RIE\r
+#define SSR02_TIE ssr02.bit._TIE\r
+__IO_EXTERN __io IO_BYTE rdr02; \r
+#define RDR02 rdr02\r
+__IO_EXTERN __io IO_BYTE tdr02; \r
+#define TDR02 tdr02\r
+__IO_EXTERN __io ESCR02STR escr02; \r
+#define ESCR02 escr02.byte\r
+#define ESCR02_LBIE escr02.bit._LBIE\r
+#define ESCR02_LBD escr02.bit._LBD\r
+#define ESCR02_LBL1 escr02.bit._LBL1\r
+#define ESCR02_LBL0 escr02.bit._LBL0\r
+#define ESCR02_SOPE escr02.bit._SOPE\r
+#define ESCR02_SIOP escr02.bit._SIOP\r
+#define ESCR02_CCO escr02.bit._CCO\r
+#define ESCR02_SCES escr02.bit._SCES\r
+#define ESCR02_LBL escr02.bitc._LBL\r
+__IO_EXTERN __io ECCR02STR eccr02; \r
+#define ECCR02 eccr02.byte\r
+#define ECCR02_INV eccr02.bit._INV\r
+#define ECCR02_LBR eccr02.bit._LBR\r
+#define ECCR02_MS eccr02.bit._MS\r
+#define ECCR02_SCDE eccr02.bit._SCDE\r
+#define ECCR02_SSM eccr02.bit._SSM\r
+#define ECCR02_BIE eccr02.bit._BIE\r
+#define ECCR02_RBI eccr02.bit._RBI\r
+#define ECCR02_TBI eccr02.bit._TBI\r
+__IO_EXTERN __io SCR03STR scr03; /* USART (LIN) 3 */\r
+#define SCR03 scr03.byte\r
+#define SCR03_PEN scr03.bit._PEN\r
+#define SCR03_P scr03.bit._P\r
+#define SCR03_SBL scr03.bit._SBL\r
+#define SCR03_CL scr03.bit._CL\r
+#define SCR03_AD scr03.bit._AD\r
+#define SCR03_CRE scr03.bit._CRE\r
+#define SCR03_RXE scr03.bit._RXE\r
+#define SCR03_TXE scr03.bit._TXE\r
+__IO_EXTERN __io SMR03STR smr03; \r
+#define SMR03 smr03.byte\r
+#define SMR03_MD1 smr03.bit._MD1\r
+#define SMR03_MD0 smr03.bit._MD0\r
+#define SMR03_OTO smr03.bit._OTO\r
+#define SMR03_EXT smr03.bit._EXT\r
+#define SMR03_REST smr03.bit._REST\r
+#define SMR03_UPCL smr03.bit._UPCL\r
+#define SMR03_SCKE smr03.bit._SCKE\r
+#define SMR03_SOE smr03.bit._SOE\r
+#define SMR03_MD smr03.bitc._MD\r
+__IO_EXTERN __io SSR03STR ssr03; \r
+#define SSR03 ssr03.byte\r
+#define SSR03_PE ssr03.bit._PE\r
+#define SSR03_ORE ssr03.bit._ORE\r
+#define SSR03_FRE ssr03.bit._FRE\r
+#define SSR03_RDRF ssr03.bit._RDRF\r
+#define SSR03_TDRE ssr03.bit._TDRE\r
+#define SSR03_BDS ssr03.bit._BDS\r
+#define SSR03_RIE ssr03.bit._RIE\r
+#define SSR03_TIE ssr03.bit._TIE\r
+__IO_EXTERN __io IO_BYTE rdr03; \r
+#define RDR03 rdr03\r
+__IO_EXTERN __io IO_BYTE tdr03; \r
+#define TDR03 tdr03\r
+__IO_EXTERN __io ESCR03STR escr03; \r
+#define ESCR03 escr03.byte\r
+#define ESCR03_LBIE escr03.bit._LBIE\r
+#define ESCR03_LBD escr03.bit._LBD\r
+#define ESCR03_LBL1 escr03.bit._LBL1\r
+#define ESCR03_LBL0 escr03.bit._LBL0\r
+#define ESCR03_SOPE escr03.bit._SOPE\r
+#define ESCR03_SIOP escr03.bit._SIOP\r
+#define ESCR03_CCO escr03.bit._CCO\r
+#define ESCR03_SCES escr03.bit._SCES\r
+#define ESCR03_LBL escr03.bitc._LBL\r
+__IO_EXTERN __io ECCR03STR eccr03; \r
+#define ECCR03 eccr03.byte\r
+#define ECCR03_INV eccr03.bit._INV\r
+#define ECCR03_LBR eccr03.bit._LBR\r
+#define ECCR03_MS eccr03.bit._MS\r
+#define ECCR03_SCDE eccr03.bit._SCDE\r
+#define ECCR03_SSM eccr03.bit._SSM\r
+#define ECCR03_BIE eccr03.bit._BIE\r
+#define ECCR03_RBI eccr03.bit._RBI\r
+#define ECCR03_TBI eccr03.bit._TBI\r
+__IO_EXTERN __io SCR04STR scr04; /* USART (LIN) 4 with FIFO */\r
+#define SCR04 scr04.byte\r
+#define SCR04_PEN scr04.bit._PEN\r
+#define SCR04_P scr04.bit._P\r
+#define SCR04_SBL scr04.bit._SBL\r
+#define SCR04_CL scr04.bit._CL\r
+#define SCR04_AD scr04.bit._AD\r
+#define SCR04_CRE scr04.bit._CRE\r
+#define SCR04_RXE scr04.bit._RXE\r
+#define SCR04_TXE scr04.bit._TXE\r
+__IO_EXTERN __io SMR04STR smr04; \r
+#define SMR04 smr04.byte\r
+#define SMR04_MD1 smr04.bit._MD1\r
+#define SMR04_MD0 smr04.bit._MD0\r
+#define SMR04_OTO smr04.bit._OTO\r
+#define SMR04_EXT smr04.bit._EXT\r
+#define SMR04_REST smr04.bit._REST\r
+#define SMR04_UPCL smr04.bit._UPCL\r
+#define SMR04_SCKE smr04.bit._SCKE\r
+#define SMR04_SOE smr04.bit._SOE\r
+#define SMR04_MD smr04.bitc._MD\r
+__IO_EXTERN __io SSR04STR ssr04; \r
+#define SSR04 ssr04.byte\r
+#define SSR04_PE ssr04.bit._PE\r
+#define SSR04_ORE ssr04.bit._ORE\r
+#define SSR04_FRE ssr04.bit._FRE\r
+#define SSR04_RDRF ssr04.bit._RDRF\r
+#define SSR04_TDRE ssr04.bit._TDRE\r
+#define SSR04_BDS ssr04.bit._BDS\r
+#define SSR04_RIE ssr04.bit._RIE\r
+#define SSR04_TIE ssr04.bit._TIE\r
+__IO_EXTERN __io IO_BYTE rdr04; \r
+#define RDR04 rdr04\r
+__IO_EXTERN __io IO_BYTE tdr04; \r
+#define TDR04 tdr04\r
+__IO_EXTERN __io ESCR04STR escr04; \r
+#define ESCR04 escr04.byte\r
+#define ESCR04_LBIE escr04.bit._LBIE\r
+#define ESCR04_LBD escr04.bit._LBD\r
+#define ESCR04_LBL1 escr04.bit._LBL1\r
+#define ESCR04_LBL0 escr04.bit._LBL0\r
+#define ESCR04_SOPE escr04.bit._SOPE\r
+#define ESCR04_SIOP escr04.bit._SIOP\r
+#define ESCR04_CCO escr04.bit._CCO\r
+#define ESCR04_SCES escr04.bit._SCES\r
+#define ESCR04_LBL escr04.bitc._LBL\r
+__IO_EXTERN __io ECCR04STR eccr04; \r
+#define ECCR04 eccr04.byte\r
+#define ECCR04_INV eccr04.bit._INV\r
+#define ECCR04_LBR eccr04.bit._LBR\r
+#define ECCR04_MS eccr04.bit._MS\r
+#define ECCR04_SCDE eccr04.bit._SCDE\r
+#define ECCR04_SSM eccr04.bit._SSM\r
+#define ECCR04_BIE eccr04.bit._BIE\r
+#define ECCR04_RBI eccr04.bit._RBI\r
+#define ECCR04_TBI eccr04.bit._TBI\r
+__IO_EXTERN __io IO_BYTE fsr04; \r
+#define FSR04 fsr04\r
+__IO_EXTERN __io FCR04STR fcr04; \r
+#define FCR04 fcr04.byte\r
+#define FCR04_RXL3 fcr04.bit._RXL3\r
+#define FCR04_RXL2 fcr04.bit._RXL2\r
+#define FCR04_RXL1 fcr04.bit._RXL1\r
+#define FCR04_RXL0 fcr04.bit._RXL0\r
+#define FCR04_ERX fcr04.bit._ERX\r
+#define FCR04_ETX fcr04.bit._ETX\r
+#define FCR04_SVD fcr04.bit._SVD\r
+#define FCR04_RXL fcr04.bitc._RXL\r
+__IO_EXTERN __io IO_WORD bgr00; /* Bauderate Generator USART (LIN) 0-7 */\r
+#define BGR00 bgr00\r
+__IO_EXTERN __io IO_BYTE bgr100; \r
+#define BGR100 bgr100\r
+__IO_EXTERN __io IO_BYTE bgr000; \r
+#define BGR000 bgr000\r
+__IO_EXTERN __io IO_WORD bgr01; \r
+#define BGR01 bgr01\r
+__IO_EXTERN __io IO_BYTE bgr101; \r
+#define BGR101 bgr101\r
+__IO_EXTERN __io IO_BYTE bgr001; \r
+#define BGR001 bgr001\r
+__IO_EXTERN __io IO_WORD bgr02; \r
+#define BGR02 bgr02\r
+__IO_EXTERN __io IO_BYTE bgr102; \r
+#define BGR102 bgr102\r
+__IO_EXTERN __io IO_BYTE bgr002; \r
+#define BGR002 bgr002\r
+__IO_EXTERN __io IO_WORD bgr03; \r
+#define BGR03 bgr03\r
+__IO_EXTERN __io IO_BYTE bgr103; \r
+#define BGR103 bgr103\r
+__IO_EXTERN __io IO_BYTE bgr003; \r
+#define BGR003 bgr003\r
+__IO_EXTERN __io IO_WORD bgr04; \r
+#define BGR04 bgr04\r
+__IO_EXTERN __io IO_BYTE bgr104; \r
+#define BGR104 bgr104\r
+__IO_EXTERN __io IO_BYTE bgr004; \r
+#define BGR004 bgr004\r
+__IO_EXTERN __io IBCR0STR ibcr0; /* I2C 0 */\r
+#define IBCR0 ibcr0.byte\r
+#define IBCR0_BER ibcr0.bit._BER\r
+#define IBCR0_BEIE ibcr0.bit._BEIE\r
+#define IBCR0_SCC ibcr0.bit._SCC\r
+#define IBCR0_MSS ibcr0.bit._MSS\r
+#define IBCR0_ACK ibcr0.bit._ACK\r
+#define IBCR0_GCAA ibcr0.bit._GCAA\r
+#define IBCR0_INTE ibcr0.bit._INTE\r
+#define IBCR0_INT ibcr0.bit._INT\r
+__IO_EXTERN __io IBSR0STR ibsr0; \r
+#define IBSR0 ibsr0.byte\r
+#define IBSR0_BB ibsr0.bit._BB\r
+#define IBSR0_RSC ibsr0.bit._RSC\r
+#define IBSR0_AL ibsr0.bit._AL\r
+#define IBSR0_LRB ibsr0.bit._LRB\r
+#define IBSR0_TRX ibsr0.bit._TRX\r
+#define IBSR0_AAS ibsr0.bit._AAS\r
+#define IBSR0_GCA ibsr0.bit._GCA\r
+#define IBSR0_ADT ibsr0.bit._ADT\r
+__IO_EXTERN __io ITBA0STR itba0; \r
+#define ITBA0 itba0.word\r
+#define ITBA0_TA9 itba0.bit._TA9\r
+#define ITBA0_TA8 itba0.bit._TA8\r
+#define ITBA0_TA7 itba0.bit._TA7\r
+#define ITBA0_TA6 itba0.bit._TA6\r
+#define ITBA0_TA5 itba0.bit._TA5\r
+#define ITBA0_TA4 itba0.bit._TA4\r
+#define ITBA0_TA3 itba0.bit._TA3\r
+#define ITBA0_TA2 itba0.bit._TA2\r
+#define ITBA0_TA1 itba0.bit._TA1\r
+#define ITBA0_TA0 itba0.bit._TA0\r
+__IO_EXTERN __io ITBAH0STR itbah0; \r
+#define ITBAH0 itbah0.byte\r
+#define ITBAH0_TA9 itbah0.bit._TA9\r
+#define ITBAH0_TA8 itbah0.bit._TA8\r
+__IO_EXTERN __io ITBAL0STR itbal0; \r
+#define ITBAL0 itbal0.byte\r
+#define ITBAL0_TA7 itbal0.bit._TA7\r
+#define ITBAL0_TA6 itbal0.bit._TA6\r
+#define ITBAL0_TA5 itbal0.bit._TA5\r
+#define ITBAL0_TA4 itbal0.bit._TA4\r
+#define ITBAL0_TA3 itbal0.bit._TA3\r
+#define ITBAL0_TA2 itbal0.bit._TA2\r
+#define ITBAL0_TA1 itbal0.bit._TA1\r
+#define ITBAL0_TA0 itbal0.bit._TA0\r
+__IO_EXTERN __io ITMK0STR itmk0; \r
+#define ITMK0 itmk0.word\r
+#define ITMK0_ENTB itmk0.bit._ENTB\r
+#define ITMK0_RAL itmk0.bit._RAL\r
+#define ITMK0_TM9 itmk0.bit._TM9\r
+#define ITMK0_TM8 itmk0.bit._TM8\r
+#define ITMK0_TM7 itmk0.bit._TM7\r
+#define ITMK0_TM6 itmk0.bit._TM6\r
+#define ITMK0_TM5 itmk0.bit._TM5\r
+#define ITMK0_TM4 itmk0.bit._TM4\r
+#define ITMK0_TM3 itmk0.bit._TM3\r
+#define ITMK0_TM2 itmk0.bit._TM2\r
+#define ITMK0_TM1 itmk0.bit._TM1\r
+#define ITMK0_TM0 itmk0.bit._TM0\r
+__IO_EXTERN __io ITMKH0STR itmkh0; \r
+#define ITMKH0 itmkh0.byte\r
+#define ITMKH0_ENTB itmkh0.bit._ENTB\r
+#define ITMKH0_RAL itmkh0.bit._RAL\r
+#define ITMKH0_TM9 itmkh0.bit._TM9\r
+#define ITMKH0_TM8 itmkh0.bit._TM8\r
+__IO_EXTERN __io ITMKL0STR itmkl0; \r
+#define ITMKL0 itmkl0.byte\r
+#define ITMKL0_TM7 itmkl0.bit._TM7\r
+#define ITMKL0_TM6 itmkl0.bit._TM6\r
+#define ITMKL0_TM5 itmkl0.bit._TM5\r
+#define ITMKL0_TM4 itmkl0.bit._TM4\r
+#define ITMKL0_TM3 itmkl0.bit._TM3\r
+#define ITMKL0_TM2 itmkl0.bit._TM2\r
+#define ITMKL0_TM1 itmkl0.bit._TM1\r
+#define ITMKL0_TM0 itmkl0.bit._TM0\r
+__IO_EXTERN __io ISMK0STR ismk0; \r
+#define ISMK0 ismk0.byte\r
+#define ISMK0_ENSB ismk0.bit._ENSB\r
+#define ISMK0_SM6 ismk0.bit._SM6\r
+#define ISMK0_SM5 ismk0.bit._SM5\r
+#define ISMK0_SM4 ismk0.bit._SM4\r
+#define ISMK0_SM3 ismk0.bit._SM3\r
+#define ISMK0_SM2 ismk0.bit._SM2\r
+#define ISMK0_SM1 ismk0.bit._SM1\r
+#define ISMK0_SM0 ismk0.bit._SM0\r
+__IO_EXTERN __io ISBA0STR isba0; \r
+#define ISBA0 isba0.byte\r
+#define ISBA0_SA6 isba0.bit._SA6\r
+#define ISBA0_SA5 isba0.bit._SA5\r
+#define ISBA0_SA4 isba0.bit._SA4\r
+#define ISBA0_SA3 isba0.bit._SA3\r
+#define ISBA0_SA2 isba0.bit._SA2\r
+#define ISBA0_SA1 isba0.bit._SA1\r
+#define ISBA0_SA0 isba0.bit._SA0\r
+__IO_EXTERN __io IDAR0STR idar0; \r
+#define IDAR0 idar0.byte\r
+#define IDAR0_D7 idar0.bit._D7\r
+#define IDAR0_D6 idar0.bit._D6\r
+#define IDAR0_D5 idar0.bit._D5\r
+#define IDAR0_D4 idar0.bit._D4\r
+#define IDAR0_D3 idar0.bit._D3\r
+#define IDAR0_D2 idar0.bit._D2\r
+#define IDAR0_D1 idar0.bit._D1\r
+#define IDAR0_D0 idar0.bit._D0\r
+__IO_EXTERN __io ICCR0STR iccr0; \r
+#define ICCR0 iccr0.byte\r
+#define ICCR0_NSF iccr0.bit._NSF\r
+#define ICCR0_EN iccr0.bit._EN\r
+#define ICCR0_CS4 iccr0.bit._CS4\r
+#define ICCR0_CS3 iccr0.bit._CS3\r
+#define ICCR0_CS2 iccr0.bit._CS2\r
+#define ICCR0_CS1 iccr0.bit._CS1\r
+#define ICCR0_CS0 iccr0.bit._CS0\r
+#define ICCR0_CS iccr0.bitc._CS\r
+__IO_EXTERN GCN10STR gcn10; /* PPG Control 0-3 */\r
+#define GCN10 gcn10.word\r
+#define GCN10_TSEL33 gcn10.bit._TSEL33\r
+#define GCN10_TSEL32 gcn10.bit._TSEL32\r
+#define GCN10_TSEL31 gcn10.bit._TSEL31\r
+#define GCN10_TSEL30 gcn10.bit._TSEL30\r
+#define GCN10_TSEL23 gcn10.bit._TSEL23\r
+#define GCN10_TSEL22 gcn10.bit._TSEL22\r
+#define GCN10_TSEL21 gcn10.bit._TSEL21\r
+#define GCN10_TSEL20 gcn10.bit._TSEL20\r
+#define GCN10_TSEL13 gcn10.bit._TSEL13\r
+#define GCN10_TSEL12 gcn10.bit._TSEL12\r
+#define GCN10_TSEL11 gcn10.bit._TSEL11\r
+#define GCN10_TSEL10 gcn10.bit._TSEL10\r
+#define GCN10_TSEL03 gcn10.bit._TSEL03\r
+#define GCN10_TSEL02 gcn10.bit._TSEL02\r
+#define GCN10_TSEL01 gcn10.bit._TSEL01\r
+#define GCN10_TSEL00 gcn10.bit._TSEL00\r
+__IO_EXTERN GCN20STR gcn20; \r
+#define GCN20 gcn20.byte\r
+#define GCN20_EN3 gcn20.bit._EN3\r
+#define GCN20_EN2 gcn20.bit._EN2\r
+#define GCN20_EN1 gcn20.bit._EN1\r
+#define GCN20_EN0 gcn20.bit._EN0\r
+__IO_EXTERN GCN11STR gcn11; /* PPG Control 4-7 */\r
+#define GCN11 gcn11.word\r
+#define GCN11_TSEL33 gcn11.bit._TSEL33\r
+#define GCN11_TSEL32 gcn11.bit._TSEL32\r
+#define GCN11_TSEL31 gcn11.bit._TSEL31\r
+#define GCN11_TSEL30 gcn11.bit._TSEL30\r
+#define GCN11_TSEL23 gcn11.bit._TSEL23\r
+#define GCN11_TSEL22 gcn11.bit._TSEL22\r
+#define GCN11_TSEL21 gcn11.bit._TSEL21\r
+#define GCN11_TSEL20 gcn11.bit._TSEL20\r
+#define GCN11_TSEL13 gcn11.bit._TSEL13\r
+#define GCN11_TSEL12 gcn11.bit._TSEL12\r
+#define GCN11_TSEL11 gcn11.bit._TSEL11\r
+#define GCN11_TSEL10 gcn11.bit._TSEL10\r
+#define GCN11_TSEL03 gcn11.bit._TSEL03\r
+#define GCN11_TSEL02 gcn11.bit._TSEL02\r
+#define GCN11_TSEL01 gcn11.bit._TSEL01\r
+#define GCN11_TSEL00 gcn11.bit._TSEL00\r
+__IO_EXTERN GCN21STR gcn21; \r
+#define GCN21 gcn21.byte\r
+#define GCN21_EN3 gcn21.bit._EN3\r
+#define GCN21_EN2 gcn21.bit._EN2\r
+#define GCN21_EN1 gcn21.bit._EN1\r
+#define GCN21_EN0 gcn21.bit._EN0\r
+__IO_EXTERN GCN12STR gcn12; /* PPG Control 8-11 */\r
+#define GCN12 gcn12.word\r
+#define GCN12_TSEL33 gcn12.bit._TSEL33\r
+#define GCN12_TSEL32 gcn12.bit._TSEL32\r
+#define GCN12_TSEL31 gcn12.bit._TSEL31\r
+#define GCN12_TSEL30 gcn12.bit._TSEL30\r
+#define GCN12_TSEL23 gcn12.bit._TSEL23\r
+#define GCN12_TSEL22 gcn12.bit._TSEL22\r
+#define GCN12_TSEL21 gcn12.bit._TSEL21\r
+#define GCN12_TSEL20 gcn12.bit._TSEL20\r
+#define GCN12_TSEL13 gcn12.bit._TSEL13\r
+#define GCN12_TSEL12 gcn12.bit._TSEL12\r
+#define GCN12_TSEL11 gcn12.bit._TSEL11\r
+#define GCN12_TSEL10 gcn12.bit._TSEL10\r
+#define GCN12_TSEL03 gcn12.bit._TSEL03\r
+#define GCN12_TSEL02 gcn12.bit._TSEL02\r
+#define GCN12_TSEL01 gcn12.bit._TSEL01\r
+#define GCN12_TSEL00 gcn12.bit._TSEL00\r
+__IO_EXTERN GCN22STR gcn22; \r
+#define GCN22 gcn22.byte\r
+#define GCN22_EN3 gcn22.bit._EN3\r
+#define GCN22_EN2 gcn22.bit._EN2\r
+#define GCN22_EN1 gcn22.bit._EN1\r
+#define GCN22_EN0 gcn22.bit._EN0\r
+__IO_EXTERN IO_WORD ptmr00; /* PPG 0 */\r
+#define PTMR00 ptmr00\r
+__IO_EXTERN IO_WORD pcsr00; \r
+#define PCSR00 pcsr00\r
+__IO_EXTERN IO_WORD pdut00; \r
+#define PDUT00 pdut00\r
+__IO_EXTERN PCN00STR pcn00; \r
+#define PCN00 pcn00.word\r
+#define PCN00_CNTE pcn00.bit._CNTE\r
+#define PCN00_STGR pcn00.bit._STGR\r
+#define PCN00_MDSE pcn00.bit._MDSE\r
+#define PCN00_RTRG pcn00.bit._RTRG\r
+#define PCN00_CKS1 pcn00.bit._CKS1\r
+#define PCN00_CKS0 pcn00.bit._CKS0\r
+#define PCN00_PGMS pcn00.bit._PGMS\r
+#define PCN00_EGS1 pcn00.bit._EGS1\r
+#define PCN00_EGS0 pcn00.bit._EGS0\r
+#define PCN00_IREN pcn00.bit._IREN\r
+#define PCN00_IRQF pcn00.bit._IRQF\r
+#define PCN00_IRS1 pcn00.bit._IRS1\r
+#define PCN00_IRS0 pcn00.bit._IRS0\r
+#define PCN00_OSEL pcn00.bit._OSEL\r
+#define PCN00_CKS pcn00.bitc._CKS\r
+#define PCN00_EGS pcn00.bitc._EGS\r
+#define PCN00_IRS pcn00.bitc._IRS\r
+__IO_EXTERN PCNH00STR pcnh00; \r
+#define PCNH00 pcnh00.byte\r
+#define PCNH00_CNTE pcnh00.bit._CNTE\r
+#define PCNH00_STGR pcnh00.bit._STGR\r
+#define PCNH00_MDSE pcnh00.bit._MDSE\r
+#define PCNH00_RTRG pcnh00.bit._RTRG\r
+#define PCNH00_CKS1 pcnh00.bit._CKS1\r
+#define PCNH00_CKS0 pcnh00.bit._CKS0\r
+#define PCNH00_PGMS pcnh00.bit._PGMS\r
+#define PCNH00_CKS pcnh00.bitc._CKS\r
+__IO_EXTERN PCNL00STR pcnl00; \r
+#define PCNL00 pcnl00.byte\r
+#define PCNL00_EGS1 pcnl00.bit._EGS1\r
+#define PCNL00_EGS0 pcnl00.bit._EGS0\r
+#define PCNL00_IREN pcnl00.bit._IREN\r
+#define PCNL00_IRQF pcnl00.bit._IRQF\r
+#define PCNL00_IRS1 pcnl00.bit._IRS1\r
+#define PCNL00_IRS0 pcnl00.bit._IRS0\r
+#define PCNL00_OSEL pcnl00.bit._OSEL\r
+#define PCNL00_EGS pcnl00.bitc._EGS\r
+#define PCNL00_IRS pcnl00.bitc._IRS\r
+__IO_EXTERN IO_WORD ptmr01; /* PPG 1 */\r
+#define PTMR01 ptmr01\r
+__IO_EXTERN IO_WORD pcsr01; \r
+#define PCSR01 pcsr01\r
+__IO_EXTERN IO_WORD pdut01; \r
+#define PDUT01 pdut01\r
+__IO_EXTERN PCN01STR pcn01; \r
+#define PCN01 pcn01.word\r
+#define PCN01_CNTE pcn01.bit._CNTE\r
+#define PCN01_STGR pcn01.bit._STGR\r
+#define PCN01_MDSE pcn01.bit._MDSE\r
+#define PCN01_RTRG pcn01.bit._RTRG\r
+#define PCN01_CKS1 pcn01.bit._CKS1\r
+#define PCN01_CKS0 pcn01.bit._CKS0\r
+#define PCN01_PGMS pcn01.bit._PGMS\r
+#define PCN01_EGS1 pcn01.bit._EGS1\r
+#define PCN01_EGS0 pcn01.bit._EGS0\r
+#define PCN01_IREN pcn01.bit._IREN\r
+#define PCN01_IRQF pcn01.bit._IRQF\r
+#define PCN01_IRS1 pcn01.bit._IRS1\r
+#define PCN01_IRS0 pcn01.bit._IRS0\r
+#define PCN01_OSEL pcn01.bit._OSEL\r
+#define PCN01_CKS pcn01.bitc._CKS\r
+#define PCN01_EGS pcn01.bitc._EGS\r
+#define PCN01_IRS pcn01.bitc._IRS\r
+__IO_EXTERN PCNH01STR pcnh01; \r
+#define PCNH01 pcnh01.byte\r
+#define PCNH01_CNTE pcnh01.bit._CNTE\r
+#define PCNH01_STGR pcnh01.bit._STGR\r
+#define PCNH01_MDSE pcnh01.bit._MDSE\r
+#define PCNH01_RTRG pcnh01.bit._RTRG\r
+#define PCNH01_CKS1 pcnh01.bit._CKS1\r
+#define PCNH01_CKS0 pcnh01.bit._CKS0\r
+#define PCNH01_PGMS pcnh01.bit._PGMS\r
+#define PCNH01_CKS pcnh01.bitc._CKS\r
+__IO_EXTERN PCNL01STR pcnl01; \r
+#define PCNL01 pcnl01.byte\r
+#define PCNL01_EGS1 pcnl01.bit._EGS1\r
+#define PCNL01_EGS0 pcnl01.bit._EGS0\r
+#define PCNL01_IREN pcnl01.bit._IREN\r
+#define PCNL01_IRQF pcnl01.bit._IRQF\r
+#define PCNL01_IRS1 pcnl01.bit._IRS1\r
+#define PCNL01_IRS0 pcnl01.bit._IRS0\r
+#define PCNL01_OSEL pcnl01.bit._OSEL\r
+#define PCNL01_EGS pcnl01.bitc._EGS\r
+#define PCNL01_IRS pcnl01.bitc._IRS\r
+__IO_EXTERN IO_WORD ptmr02; /* PPG 2 */\r
+#define PTMR02 ptmr02\r
+__IO_EXTERN IO_WORD pcsr02; \r
+#define PCSR02 pcsr02\r
+__IO_EXTERN IO_WORD pdut02; \r
+#define PDUT02 pdut02\r
+__IO_EXTERN PCN02STR pcn02; \r
+#define PCN02 pcn02.word\r
+#define PCN02_CNTE pcn02.bit._CNTE\r
+#define PCN02_STGR pcn02.bit._STGR\r
+#define PCN02_MDSE pcn02.bit._MDSE\r
+#define PCN02_RTRG pcn02.bit._RTRG\r
+#define PCN02_CKS1 pcn02.bit._CKS1\r
+#define PCN02_CKS0 pcn02.bit._CKS0\r
+#define PCN02_PGMS pcn02.bit._PGMS\r
+#define PCN02_EGS1 pcn02.bit._EGS1\r
+#define PCN02_EGS0 pcn02.bit._EGS0\r
+#define PCN02_IREN pcn02.bit._IREN\r
+#define PCN02_IRQF pcn02.bit._IRQF\r
+#define PCN02_IRS1 pcn02.bit._IRS1\r
+#define PCN02_IRS0 pcn02.bit._IRS0\r
+#define PCN02_OSEL pcn02.bit._OSEL\r
+#define PCN02_CKS pcn02.bitc._CKS\r
+#define PCN02_EGS pcn02.bitc._EGS\r
+#define PCN02_IRS pcn02.bitc._IRS\r
+__IO_EXTERN PCNH02STR pcnh02; \r
+#define PCNH02 pcnh02.byte\r
+#define PCNH02_CNTE pcnh02.bit._CNTE\r
+#define PCNH02_STGR pcnh02.bit._STGR\r
+#define PCNH02_MDSE pcnh02.bit._MDSE\r
+#define PCNH02_RTRG pcnh02.bit._RTRG\r
+#define PCNH02_CKS1 pcnh02.bit._CKS1\r
+#define PCNH02_CKS0 pcnh02.bit._CKS0\r
+#define PCNH02_PGMS pcnh02.bit._PGMS\r
+#define PCNH02_CKS pcnh02.bitc._CKS\r
+__IO_EXTERN PCNL02STR pcnl02; \r
+#define PCNL02 pcnl02.byte\r
+#define PCNL02_EGS1 pcnl02.bit._EGS1\r
+#define PCNL02_EGS0 pcnl02.bit._EGS0\r
+#define PCNL02_IREN pcnl02.bit._IREN\r
+#define PCNL02_IRQF pcnl02.bit._IRQF\r
+#define PCNL02_IRS1 pcnl02.bit._IRS1\r
+#define PCNL02_IRS0 pcnl02.bit._IRS0\r
+#define PCNL02_OSEL pcnl02.bit._OSEL\r
+#define PCNL02_EGS pcnl02.bitc._EGS\r
+#define PCNL02_IRS pcnl02.bitc._IRS\r
+__IO_EXTERN IO_WORD ptmr03; /* PPG 3 */\r
+#define PTMR03 ptmr03\r
+__IO_EXTERN IO_WORD pcsr03; \r
+#define PCSR03 pcsr03\r
+__IO_EXTERN IO_WORD pdut03; \r
+#define PDUT03 pdut03\r
+__IO_EXTERN PCN03STR pcn03; \r
+#define PCN03 pcn03.word\r
+#define PCN03_CNTE pcn03.bit._CNTE\r
+#define PCN03_STGR pcn03.bit._STGR\r
+#define PCN03_MDSE pcn03.bit._MDSE\r
+#define PCN03_RTRG pcn03.bit._RTRG\r
+#define PCN03_CKS1 pcn03.bit._CKS1\r
+#define PCN03_CKS0 pcn03.bit._CKS0\r
+#define PCN03_PGMS pcn03.bit._PGMS\r
+#define PCN03_EGS1 pcn03.bit._EGS1\r
+#define PCN03_EGS0 pcn03.bit._EGS0\r
+#define PCN03_IREN pcn03.bit._IREN\r
+#define PCN03_IRQF pcn03.bit._IRQF\r
+#define PCN03_IRS1 pcn03.bit._IRS1\r
+#define PCN03_IRS0 pcn03.bit._IRS0\r
+#define PCN03_OSEL pcn03.bit._OSEL\r
+#define PCN03_CKS pcn03.bitc._CKS\r
+#define PCN03_EGS pcn03.bitc._EGS\r
+#define PCN03_IRS pcn03.bitc._IRS\r
+__IO_EXTERN PCNH03STR pcnh03; \r
+#define PCNH03 pcnh03.byte\r
+#define PCNH03_CNTE pcnh03.bit._CNTE\r
+#define PCNH03_STGR pcnh03.bit._STGR\r
+#define PCNH03_MDSE pcnh03.bit._MDSE\r
+#define PCNH03_RTRG pcnh03.bit._RTRG\r
+#define PCNH03_CKS1 pcnh03.bit._CKS1\r
+#define PCNH03_CKS0 pcnh03.bit._CKS0\r
+#define PCNH03_PGMS pcnh03.bit._PGMS\r
+#define PCNH03_CKS pcnh03.bitc._CKS\r
+__IO_EXTERN PCNL03STR pcnl03; \r
+#define PCNL03 pcnl03.byte\r
+#define PCNL03_EGS1 pcnl03.bit._EGS1\r
+#define PCNL03_EGS0 pcnl03.bit._EGS0\r
+#define PCNL03_IREN pcnl03.bit._IREN\r
+#define PCNL03_IRQF pcnl03.bit._IRQF\r
+#define PCNL03_IRS1 pcnl03.bit._IRS1\r
+#define PCNL03_IRS0 pcnl03.bit._IRS0\r
+#define PCNL03_OSEL pcnl03.bit._OSEL\r
+#define PCNL03_EGS pcnl03.bitc._EGS\r
+#define PCNL03_IRS pcnl03.bitc._IRS\r
+__IO_EXTERN IO_WORD ptmr04; /* PPG 4 */\r
+#define PTMR04 ptmr04\r
+__IO_EXTERN IO_WORD pcsr04; \r
+#define PCSR04 pcsr04\r
+__IO_EXTERN IO_WORD pdut04; \r
+#define PDUT04 pdut04\r
+__IO_EXTERN PCN04STR pcn04; \r
+#define PCN04 pcn04.word\r
+#define PCN04_CNTE pcn04.bit._CNTE\r
+#define PCN04_STGR pcn04.bit._STGR\r
+#define PCN04_MDSE pcn04.bit._MDSE\r
+#define PCN04_RTRG pcn04.bit._RTRG\r
+#define PCN04_CKS1 pcn04.bit._CKS1\r
+#define PCN04_CKS0 pcn04.bit._CKS0\r
+#define PCN04_PGMS pcn04.bit._PGMS\r
+#define PCN04_EGS1 pcn04.bit._EGS1\r
+#define PCN04_EGS0 pcn04.bit._EGS0\r
+#define PCN04_IREN pcn04.bit._IREN\r
+#define PCN04_IRQF pcn04.bit._IRQF\r
+#define PCN04_IRS1 pcn04.bit._IRS1\r
+#define PCN04_IRS0 pcn04.bit._IRS0\r
+#define PCN04_OSEL pcn04.bit._OSEL\r
+#define PCN04_CKS pcn04.bitc._CKS\r
+#define PCN04_EGS pcn04.bitc._EGS\r
+#define PCN04_IRS pcn04.bitc._IRS\r
+__IO_EXTERN PCNH04STR pcnh04; \r
+#define PCNH04 pcnh04.byte\r
+#define PCNH04_CNTE pcnh04.bit._CNTE\r
+#define PCNH04_STGR pcnh04.bit._STGR\r
+#define PCNH04_MDSE pcnh04.bit._MDSE\r
+#define PCNH04_RTRG pcnh04.bit._RTRG\r
+#define PCNH04_CKS1 pcnh04.bit._CKS1\r
+#define PCNH04_CKS0 pcnh04.bit._CKS0\r
+#define PCNH04_PGMS pcnh04.bit._PGMS\r
+#define PCNH04_CKS pcnh04.bitc._CKS\r
+__IO_EXTERN PCNL04STR pcnl04; \r
+#define PCNL04 pcnl04.byte\r
+#define PCNL04_EGS1 pcnl04.bit._EGS1\r
+#define PCNL04_EGS0 pcnl04.bit._EGS0\r
+#define PCNL04_IREN pcnl04.bit._IREN\r
+#define PCNL04_IRQF pcnl04.bit._IRQF\r
+#define PCNL04_IRS1 pcnl04.bit._IRS1\r
+#define PCNL04_IRS0 pcnl04.bit._IRS0\r
+#define PCNL04_OSEL pcnl04.bit._OSEL\r
+#define PCNL04_EGS pcnl04.bitc._EGS\r
+#define PCNL04_IRS pcnl04.bitc._IRS\r
+__IO_EXTERN IO_WORD ptmr05; /* PPG 5 */\r
+#define PTMR05 ptmr05\r
+__IO_EXTERN IO_WORD pcsr05; \r
+#define PCSR05 pcsr05\r
+__IO_EXTERN IO_WORD pdut05; \r
+#define PDUT05 pdut05\r
+__IO_EXTERN PCN05STR pcn05; \r
+#define PCN05 pcn05.word\r
+#define PCN05_CNTE pcn05.bit._CNTE\r
+#define PCN05_STGR pcn05.bit._STGR\r
+#define PCN05_MDSE pcn05.bit._MDSE\r
+#define PCN05_RTRG pcn05.bit._RTRG\r
+#define PCN05_CKS1 pcn05.bit._CKS1\r
+#define PCN05_CKS0 pcn05.bit._CKS0\r
+#define PCN05_PGMS pcn05.bit._PGMS\r
+#define PCN05_EGS1 pcn05.bit._EGS1\r
+#define PCN05_EGS0 pcn05.bit._EGS0\r
+#define PCN05_IREN pcn05.bit._IREN\r
+#define PCN05_IRQF pcn05.bit._IRQF\r
+#define PCN05_IRS1 pcn05.bit._IRS1\r
+#define PCN05_IRS0 pcn05.bit._IRS0\r
+#define PCN05_OSEL pcn05.bit._OSEL\r
+#define PCN05_CKS pcn05.bitc._CKS\r
+#define PCN05_EGS pcn05.bitc._EGS\r
+#define PCN05_IRS pcn05.bitc._IRS\r
+__IO_EXTERN PCNH05STR pcnh05; \r
+#define PCNH05 pcnh05.byte\r
+#define PCNH05_CNTE pcnh05.bit._CNTE\r
+#define PCNH05_STGR pcnh05.bit._STGR\r
+#define PCNH05_MDSE pcnh05.bit._MDSE\r
+#define PCNH05_RTRG pcnh05.bit._RTRG\r
+#define PCNH05_CKS1 pcnh05.bit._CKS1\r
+#define PCNH05_CKS0 pcnh05.bit._CKS0\r
+#define PCNH05_PGMS pcnh05.bit._PGMS\r
+#define PCNH05_CKS pcnh05.bitc._CKS\r
+__IO_EXTERN PCNL05STR pcnl05; \r
+#define PCNL05 pcnl05.byte\r
+#define PCNL05_EGS1 pcnl05.bit._EGS1\r
+#define PCNL05_EGS0 pcnl05.bit._EGS0\r
+#define PCNL05_IREN pcnl05.bit._IREN\r
+#define PCNL05_IRQF pcnl05.bit._IRQF\r
+#define PCNL05_IRS1 pcnl05.bit._IRS1\r
+#define PCNL05_IRS0 pcnl05.bit._IRS0\r
+#define PCNL05_OSEL pcnl05.bit._OSEL\r
+#define PCNL05_EGS pcnl05.bitc._EGS\r
+#define PCNL05_IRS pcnl05.bitc._IRS\r
+__IO_EXTERN IO_WORD ptmr06; /* PPG 6 */\r
+#define PTMR06 ptmr06\r
+__IO_EXTERN IO_WORD pcsr06; \r
+#define PCSR06 pcsr06\r
+__IO_EXTERN IO_WORD pdut06; \r
+#define PDUT06 pdut06\r
+__IO_EXTERN PCN06STR pcn06; \r
+#define PCN06 pcn06.word\r
+#define PCN06_CNTE pcn06.bit._CNTE\r
+#define PCN06_STGR pcn06.bit._STGR\r
+#define PCN06_MDSE pcn06.bit._MDSE\r
+#define PCN06_RTRG pcn06.bit._RTRG\r
+#define PCN06_CKS1 pcn06.bit._CKS1\r
+#define PCN06_CKS0 pcn06.bit._CKS0\r
+#define PCN06_PGMS pcn06.bit._PGMS\r
+#define PCN06_EGS1 pcn06.bit._EGS1\r
+#define PCN06_EGS0 pcn06.bit._EGS0\r
+#define PCN06_IREN pcn06.bit._IREN\r
+#define PCN06_IRQF pcn06.bit._IRQF\r
+#define PCN06_IRS1 pcn06.bit._IRS1\r
+#define PCN06_IRS0 pcn06.bit._IRS0\r
+#define PCN06_OSEL pcn06.bit._OSEL\r
+#define PCN06_CKS pcn06.bitc._CKS\r
+#define PCN06_EGS pcn06.bitc._EGS\r
+#define PCN06_IRS pcn06.bitc._IRS\r
+__IO_EXTERN PCNH06STR pcnh06; \r
+#define PCNH06 pcnh06.byte\r
+#define PCNH06_CNTE pcnh06.bit._CNTE\r
+#define PCNH06_STGR pcnh06.bit._STGR\r
+#define PCNH06_MDSE pcnh06.bit._MDSE\r
+#define PCNH06_RTRG pcnh06.bit._RTRG\r
+#define PCNH06_CKS1 pcnh06.bit._CKS1\r
+#define PCNH06_CKS0 pcnh06.bit._CKS0\r
+#define PCNH06_PGMS pcnh06.bit._PGMS\r
+#define PCNH06_CKS pcnh06.bitc._CKS\r
+__IO_EXTERN PCNL06STR pcnl06; \r
+#define PCNL06 pcnl06.byte\r
+#define PCNL06_EGS1 pcnl06.bit._EGS1\r
+#define PCNL06_EGS0 pcnl06.bit._EGS0\r
+#define PCNL06_IREN pcnl06.bit._IREN\r
+#define PCNL06_IRQF pcnl06.bit._IRQF\r
+#define PCNL06_IRS1 pcnl06.bit._IRS1\r
+#define PCNL06_IRS0 pcnl06.bit._IRS0\r
+#define PCNL06_OSEL pcnl06.bit._OSEL\r
+#define PCNL06_EGS pcnl06.bitc._EGS\r
+#define PCNL06_IRS pcnl06.bitc._IRS\r
+__IO_EXTERN IO_WORD ptmr07; /* PPG 7 */\r
+#define PTMR07 ptmr07\r
+__IO_EXTERN IO_WORD pcsr07; \r
+#define PCSR07 pcsr07\r
+__IO_EXTERN IO_WORD pdut07; \r
+#define PDUT07 pdut07\r
+__IO_EXTERN PCN07STR pcn07; \r
+#define PCN07 pcn07.word\r
+#define PCN07_CNTE pcn07.bit._CNTE\r
+#define PCN07_STGR pcn07.bit._STGR\r
+#define PCN07_MDSE pcn07.bit._MDSE\r
+#define PCN07_RTRG pcn07.bit._RTRG\r
+#define PCN07_CKS1 pcn07.bit._CKS1\r
+#define PCN07_CKS0 pcn07.bit._CKS0\r
+#define PCN07_PGMS pcn07.bit._PGMS\r
+#define PCN07_EGS1 pcn07.bit._EGS1\r
+#define PCN07_EGS0 pcn07.bit._EGS0\r
+#define PCN07_IREN pcn07.bit._IREN\r
+#define PCN07_IRQF pcn07.bit._IRQF\r
+#define PCN07_IRS1 pcn07.bit._IRS1\r
+#define PCN07_IRS0 pcn07.bit._IRS0\r
+#define PCN07_OSEL pcn07.bit._OSEL\r
+#define PCN07_CKS pcn07.bitc._CKS\r
+#define PCN07_EGS pcn07.bitc._EGS\r
+#define PCN07_IRS pcn07.bitc._IRS\r
+__IO_EXTERN PCNH07STR pcnh07; \r
+#define PCNH07 pcnh07.byte\r
+#define PCNH07_CNTE pcnh07.bit._CNTE\r
+#define PCNH07_STGR pcnh07.bit._STGR\r
+#define PCNH07_MDSE pcnh07.bit._MDSE\r
+#define PCNH07_RTRG pcnh07.bit._RTRG\r
+#define PCNH07_CKS1 pcnh07.bit._CKS1\r
+#define PCNH07_CKS0 pcnh07.bit._CKS0\r
+#define PCNH07_PGMS pcnh07.bit._PGMS\r
+#define PCNH07_CKS pcnh07.bitc._CKS\r
+__IO_EXTERN PCNL07STR pcnl07; \r
+#define PCNL07 pcnl07.byte\r
+#define PCNL07_EGS1 pcnl07.bit._EGS1\r
+#define PCNL07_EGS0 pcnl07.bit._EGS0\r
+#define PCNL07_IREN pcnl07.bit._IREN\r
+#define PCNL07_IRQF pcnl07.bit._IRQF\r
+#define PCNL07_IRS1 pcnl07.bit._IRS1\r
+#define PCNL07_IRS0 pcnl07.bit._IRS0\r
+#define PCNL07_OSEL pcnl07.bit._OSEL\r
+#define PCNL07_EGS pcnl07.bitc._EGS\r
+#define PCNL07_IRS pcnl07.bitc._IRS\r
+__IO_EXTERN IO_WORD ptmr08; /* PPG 8 */\r
+#define PTMR08 ptmr08\r
+__IO_EXTERN IO_WORD pcsr08; \r
+#define PCSR08 pcsr08\r
+__IO_EXTERN IO_WORD pdut08; \r
+#define PDUT08 pdut08\r
+__IO_EXTERN PCN08STR pcn08; \r
+#define PCN08 pcn08.word\r
+#define PCN08_CNTE pcn08.bit._CNTE\r
+#define PCN08_STGR pcn08.bit._STGR\r
+#define PCN08_MDSE pcn08.bit._MDSE\r
+#define PCN08_RTRG pcn08.bit._RTRG\r
+#define PCN08_CKS1 pcn08.bit._CKS1\r
+#define PCN08_CKS0 pcn08.bit._CKS0\r
+#define PCN08_PGMS pcn08.bit._PGMS\r
+#define PCN08_EGS1 pcn08.bit._EGS1\r
+#define PCN08_EGS0 pcn08.bit._EGS0\r
+#define PCN08_IREN pcn08.bit._IREN\r
+#define PCN08_IRQF pcn08.bit._IRQF\r
+#define PCN08_IRS1 pcn08.bit._IRS1\r
+#define PCN08_IRS0 pcn08.bit._IRS0\r
+#define PCN08_OSEL pcn08.bit._OSEL\r
+#define PCN08_CKS pcn08.bitc._CKS\r
+#define PCN08_EGS pcn08.bitc._EGS\r
+#define PCN08_IRS pcn08.bitc._IRS\r
+__IO_EXTERN PCNH08STR pcnh08; \r
+#define PCNH08 pcnh08.byte\r
+#define PCNH08_CNTE pcnh08.bit._CNTE\r
+#define PCNH08_STGR pcnh08.bit._STGR\r
+#define PCNH08_MDSE pcnh08.bit._MDSE\r
+#define PCNH08_RTRG pcnh08.bit._RTRG\r
+#define PCNH08_CKS1 pcnh08.bit._CKS1\r
+#define PCNH08_CKS0 pcnh08.bit._CKS0\r
+#define PCNH08_PGMS pcnh08.bit._PGMS\r
+#define PCNH08_CKS pcnh08.bitc._CKS\r
+__IO_EXTERN PCNL08STR pcnl08; \r
+#define PCNL08 pcnl08.byte\r
+#define PCNL08_EGS1 pcnl08.bit._EGS1\r
+#define PCNL08_EGS0 pcnl08.bit._EGS0\r
+#define PCNL08_IREN pcnl08.bit._IREN\r
+#define PCNL08_IRQF pcnl08.bit._IRQF\r
+#define PCNL08_IRS1 pcnl08.bit._IRS1\r
+#define PCNL08_IRS0 pcnl08.bit._IRS0\r
+#define PCNL08_OSEL pcnl08.bit._OSEL\r
+#define PCNL08_EGS pcnl08.bitc._EGS\r
+#define PCNL08_IRS pcnl08.bitc._IRS\r
+__IO_EXTERN IO_WORD ptmr09; /* PPG 9 */\r
+#define PTMR09 ptmr09\r
+__IO_EXTERN IO_WORD pcsr09; \r
+#define PCSR09 pcsr09\r
+__IO_EXTERN IO_WORD pdut09; \r
+#define PDUT09 pdut09\r
+__IO_EXTERN PCN09STR pcn09; \r
+#define PCN09 pcn09.word\r
+#define PCN09_CNTE pcn09.bit._CNTE\r
+#define PCN09_STGR pcn09.bit._STGR\r
+#define PCN09_MDSE pcn09.bit._MDSE\r
+#define PCN09_RTRG pcn09.bit._RTRG\r
+#define PCN09_CKS1 pcn09.bit._CKS1\r
+#define PCN09_CKS0 pcn09.bit._CKS0\r
+#define PCN09_PGMS pcn09.bit._PGMS\r
+#define PCN09_EGS1 pcn09.bit._EGS1\r
+#define PCN09_EGS0 pcn09.bit._EGS0\r
+#define PCN09_IREN pcn09.bit._IREN\r
+#define PCN09_IRQF pcn09.bit._IRQF\r
+#define PCN09_IRS1 pcn09.bit._IRS1\r
+#define PCN09_IRS0 pcn09.bit._IRS0\r
+#define PCN09_OSEL pcn09.bit._OSEL\r
+#define PCN09_CKS pcn09.bitc._CKS\r
+#define PCN09_EGS pcn09.bitc._EGS\r
+#define PCN09_IRS pcn09.bitc._IRS\r
+__IO_EXTERN PCNH09STR pcnh09; \r
+#define PCNH09 pcnh09.byte\r
+#define PCNH09_CNTE pcnh09.bit._CNTE\r
+#define PCNH09_STGR pcnh09.bit._STGR\r
+#define PCNH09_MDSE pcnh09.bit._MDSE\r
+#define PCNH09_RTRG pcnh09.bit._RTRG\r
+#define PCNH09_CKS1 pcnh09.bit._CKS1\r
+#define PCNH09_CKS0 pcnh09.bit._CKS0\r
+#define PCNH09_PGMS pcnh09.bit._PGMS\r
+#define PCNH09_CKS pcnh09.bitc._CKS\r
+__IO_EXTERN PCNL09STR pcnl09; \r
+#define PCNL09 pcnl09.byte\r
+#define PCNL09_EGS1 pcnl09.bit._EGS1\r
+#define PCNL09_EGS0 pcnl09.bit._EGS0\r
+#define PCNL09_IREN pcnl09.bit._IREN\r
+#define PCNL09_IRQF pcnl09.bit._IRQF\r
+#define PCNL09_IRS1 pcnl09.bit._IRS1\r
+#define PCNL09_IRS0 pcnl09.bit._IRS0\r
+#define PCNL09_OSEL pcnl09.bit._OSEL\r
+#define PCNL09_EGS pcnl09.bitc._EGS\r
+#define PCNL09_IRS pcnl09.bitc._IRS\r
+__IO_EXTERN IO_WORD ptmr10; /* PPG 10 */\r
+#define PTMR10 ptmr10\r
+__IO_EXTERN IO_WORD pcsr10; \r
+#define PCSR10 pcsr10\r
+__IO_EXTERN IO_WORD pdut10; \r
+#define PDUT10 pdut10\r
+__IO_EXTERN PCN10STR pcn10; \r
+#define PCN10 pcn10.word\r
+#define PCN10_CNTE pcn10.bit._CNTE\r
+#define PCN10_STGR pcn10.bit._STGR\r
+#define PCN10_MDSE pcn10.bit._MDSE\r
+#define PCN10_RTRG pcn10.bit._RTRG\r
+#define PCN10_CKS1 pcn10.bit._CKS1\r
+#define PCN10_CKS0 pcn10.bit._CKS0\r
+#define PCN10_PGMS pcn10.bit._PGMS\r
+#define PCN10_EGS1 pcn10.bit._EGS1\r
+#define PCN10_EGS0 pcn10.bit._EGS0\r
+#define PCN10_IREN pcn10.bit._IREN\r
+#define PCN10_IRQF pcn10.bit._IRQF\r
+#define PCN10_IRS1 pcn10.bit._IRS1\r
+#define PCN10_IRS0 pcn10.bit._IRS0\r
+#define PCN10_OSEL pcn10.bit._OSEL\r
+#define PCN10_CKS pcn10.bitc._CKS\r
+#define PCN10_EGS pcn10.bitc._EGS\r
+#define PCN10_IRS pcn10.bitc._IRS\r
+__IO_EXTERN PCNH10STR pcnh10; \r
+#define PCNH10 pcnh10.byte\r
+#define PCNH10_CNTE pcnh10.bit._CNTE\r
+#define PCNH10_STGR pcnh10.bit._STGR\r
+#define PCNH10_MDSE pcnh10.bit._MDSE\r
+#define PCNH10_RTRG pcnh10.bit._RTRG\r
+#define PCNH10_CKS1 pcnh10.bit._CKS1\r
+#define PCNH10_CKS0 pcnh10.bit._CKS0\r
+#define PCNH10_PGMS pcnh10.bit._PGMS\r
+#define PCNH10_CKS pcnh10.bitc._CKS\r
+__IO_EXTERN PCNL10STR pcnl10; \r
+#define PCNL10 pcnl10.byte\r
+#define PCNL10_EGS1 pcnl10.bit._EGS1\r
+#define PCNL10_EGS0 pcnl10.bit._EGS0\r
+#define PCNL10_IREN pcnl10.bit._IREN\r
+#define PCNL10_IRQF pcnl10.bit._IRQF\r
+#define PCNL10_IRS1 pcnl10.bit._IRS1\r
+#define PCNL10_IRS0 pcnl10.bit._IRS0\r
+#define PCNL10_OSEL pcnl10.bit._OSEL\r
+#define PCNL10_EGS pcnl10.bitc._EGS\r
+#define PCNL10_IRS pcnl10.bitc._IRS\r
+__IO_EXTERN IO_WORD ptmr11; /* PPG 11 */\r
+#define PTMR11 ptmr11\r
+__IO_EXTERN IO_WORD pcsr11; \r
+#define PCSR11 pcsr11\r
+__IO_EXTERN IO_WORD pdut11; \r
+#define PDUT11 pdut11\r
+__IO_EXTERN PCN11STR pcn11; \r
+#define PCN11 pcn11.word\r
+#define PCN11_CNTE pcn11.bit._CNTE\r
+#define PCN11_STGR pcn11.bit._STGR\r
+#define PCN11_MDSE pcn11.bit._MDSE\r
+#define PCN11_RTRG pcn11.bit._RTRG\r
+#define PCN11_CKS1 pcn11.bit._CKS1\r
+#define PCN11_CKS0 pcn11.bit._CKS0\r
+#define PCN11_PGMS pcn11.bit._PGMS\r
+#define PCN11_EGS1 pcn11.bit._EGS1\r
+#define PCN11_EGS0 pcn11.bit._EGS0\r
+#define PCN11_IREN pcn11.bit._IREN\r
+#define PCN11_IRQF pcn11.bit._IRQF\r
+#define PCN11_IRS1 pcn11.bit._IRS1\r
+#define PCN11_IRS0 pcn11.bit._IRS0\r
+#define PCN11_OSEL pcn11.bit._OSEL\r
+#define PCN11_CKS pcn11.bitc._CKS\r
+#define PCN11_EGS pcn11.bitc._EGS\r
+#define PCN11_IRS pcn11.bitc._IRS\r
+__IO_EXTERN PCNH11STR pcnh11; \r
+#define PCNH11 pcnh11.byte\r
+#define PCNH11_CNTE pcnh11.bit._CNTE\r
+#define PCNH11_STGR pcnh11.bit._STGR\r
+#define PCNH11_MDSE pcnh11.bit._MDSE\r
+#define PCNH11_RTRG pcnh11.bit._RTRG\r
+#define PCNH11_CKS1 pcnh11.bit._CKS1\r
+#define PCNH11_CKS0 pcnh11.bit._CKS0\r
+#define PCNH11_PGMS pcnh11.bit._PGMS\r
+#define PCNH11_CKS pcnh11.bitc._CKS\r
+__IO_EXTERN PCNL11STR pcnl11; \r
+#define PCNL11 pcnl11.byte\r
+#define PCNL11_EGS1 pcnl11.bit._EGS1\r
+#define PCNL11_EGS0 pcnl11.bit._EGS0\r
+#define PCNL11_IREN pcnl11.bit._IREN\r
+#define PCNL11_IRQF pcnl11.bit._IRQF\r
+#define PCNL11_IRS1 pcnl11.bit._IRS1\r
+#define PCNL11_IRS0 pcnl11.bit._IRS0\r
+#define PCNL11_OSEL pcnl11.bit._OSEL\r
+#define PCNL11_EGS pcnl11.bitc._EGS\r
+#define PCNL11_IRS pcnl11.bitc._IRS\r
+__IO_EXTERN ICS01STR ics01; /* Input Capture 0-3 */\r
+#define ICS01 ics01.byte\r
+#define ICS01_ICP1 ics01.bit._ICP1\r
+#define ICS01_ICP0 ics01.bit._ICP0\r
+#define ICS01_ICE1 ics01.bit._ICE1\r
+#define ICS01_ICE0 ics01.bit._ICE0\r
+#define ICS01_EG11 ics01.bit._EG11\r
+#define ICS01_EG10 ics01.bit._EG10\r
+#define ICS01_EG01 ics01.bit._EG01\r
+#define ICS01_EG00 ics01.bit._EG00\r
+#define ICS01_EG1 ics01.bitc._EG1\r
+#define ICS01_EG0 ics01.bitc._EG0\r
+__IO_EXTERN ICS23STR ics23; \r
+#define ICS23 ics23.byte\r
+#define ICS23_ICP3 ics23.bit._ICP3\r
+#define ICS23_ICP2 ics23.bit._ICP2\r
+#define ICS23_ICE3 ics23.bit._ICE3\r
+#define ICS23_ICE2 ics23.bit._ICE2\r
+#define ICS23_EG31 ics23.bit._EG31\r
+#define ICS23_EG30 ics23.bit._EG30\r
+#define ICS23_EG21 ics23.bit._EG21\r
+#define ICS23_EG20 ics23.bit._EG20\r
+#define ICS23_EG3 ics23.bitc._EG3\r
+#define ICS23_EG2 ics23.bitc._EG2\r
+__IO_EXTERN IPCP0STR ipcp0; \r
+#define IPCP0 ipcp0.word\r
+#define IPCP0_CP15 ipcp0.bit._CP15\r
+#define IPCP0_CP14 ipcp0.bit._CP14\r
+#define IPCP0_CP13 ipcp0.bit._CP13\r
+#define IPCP0_CP12 ipcp0.bit._CP12\r
+#define IPCP0_CP11 ipcp0.bit._CP11\r
+#define IPCP0_CP10 ipcp0.bit._CP10\r
+#define IPCP0_CP9 ipcp0.bit._CP9\r
+#define IPCP0_CP8 ipcp0.bit._CP8\r
+#define IPCP0_CP7 ipcp0.bit._CP7\r
+#define IPCP0_CP6 ipcp0.bit._CP6\r
+#define IPCP0_CP5 ipcp0.bit._CP5\r
+#define IPCP0_CP4 ipcp0.bit._CP4\r
+#define IPCP0_CP3 ipcp0.bit._CP3\r
+#define IPCP0_CP2 ipcp0.bit._CP2\r
+#define IPCP0_CP1 ipcp0.bit._CP1\r
+#define IPCP0_CP0 ipcp0.bit._CP0\r
+__IO_EXTERN IPCP1STR ipcp1; \r
+#define IPCP1 ipcp1.word\r
+#define IPCP1_CP15 ipcp1.bit._CP15\r
+#define IPCP1_CP14 ipcp1.bit._CP14\r
+#define IPCP1_CP13 ipcp1.bit._CP13\r
+#define IPCP1_CP12 ipcp1.bit._CP12\r
+#define IPCP1_CP11 ipcp1.bit._CP11\r
+#define IPCP1_CP10 ipcp1.bit._CP10\r
+#define IPCP1_CP9 ipcp1.bit._CP9\r
+#define IPCP1_CP8 ipcp1.bit._CP8\r
+#define IPCP1_CP7 ipcp1.bit._CP7\r
+#define IPCP1_CP6 ipcp1.bit._CP6\r
+#define IPCP1_CP5 ipcp1.bit._CP5\r
+#define IPCP1_CP4 ipcp1.bit._CP4\r
+#define IPCP1_CP3 ipcp1.bit._CP3\r
+#define IPCP1_CP2 ipcp1.bit._CP2\r
+#define IPCP1_CP1 ipcp1.bit._CP1\r
+#define IPCP1_CP0 ipcp1.bit._CP0\r
+__IO_EXTERN IPCP2STR ipcp2; \r
+#define IPCP2 ipcp2.word\r
+#define IPCP2_CP15 ipcp2.bit._CP15\r
+#define IPCP2_CP14 ipcp2.bit._CP14\r
+#define IPCP2_CP13 ipcp2.bit._CP13\r
+#define IPCP2_CP12 ipcp2.bit._CP12\r
+#define IPCP2_CP11 ipcp2.bit._CP11\r
+#define IPCP2_CP10 ipcp2.bit._CP10\r
+#define IPCP2_CP9 ipcp2.bit._CP9\r
+#define IPCP2_CP8 ipcp2.bit._CP8\r
+#define IPCP2_CP7 ipcp2.bit._CP7\r
+#define IPCP2_CP6 ipcp2.bit._CP6\r
+#define IPCP2_CP5 ipcp2.bit._CP5\r
+#define IPCP2_CP4 ipcp2.bit._CP4\r
+#define IPCP2_CP3 ipcp2.bit._CP3\r
+#define IPCP2_CP2 ipcp2.bit._CP2\r
+#define IPCP2_CP1 ipcp2.bit._CP1\r
+#define IPCP2_CP0 ipcp2.bit._CP0\r
+__IO_EXTERN IPCP3STR ipcp3; \r
+#define IPCP3 ipcp3.word\r
+#define IPCP3_CP15 ipcp3.bit._CP15\r
+#define IPCP3_CP14 ipcp3.bit._CP14\r
+#define IPCP3_CP13 ipcp3.bit._CP13\r
+#define IPCP3_CP12 ipcp3.bit._CP12\r
+#define IPCP3_CP11 ipcp3.bit._CP11\r
+#define IPCP3_CP10 ipcp3.bit._CP10\r
+#define IPCP3_CP9 ipcp3.bit._CP9\r
+#define IPCP3_CP8 ipcp3.bit._CP8\r
+#define IPCP3_CP7 ipcp3.bit._CP7\r
+#define IPCP3_CP6 ipcp3.bit._CP6\r
+#define IPCP3_CP5 ipcp3.bit._CP5\r
+#define IPCP3_CP4 ipcp3.bit._CP4\r
+#define IPCP3_CP3 ipcp3.bit._CP3\r
+#define IPCP3_CP2 ipcp3.bit._CP2\r
+#define IPCP3_CP1 ipcp3.bit._CP1\r
+#define IPCP3_CP0 ipcp3.bit._CP0\r
+__IO_EXTERN OCS01STR ocs01; /* Output Compare 0-3 */\r
+#define OCS01 ocs01.word\r
+#define OCS01_CMOD ocs01.bit._CMOD\r
+#define OCS01_OTD1 ocs01.bit._OTD1\r
+#define OCS01_OTD0 ocs01.bit._OTD0\r
+#define OCS01_ICP1 ocs01.bit._ICP1\r
+#define OCS01_ICP0 ocs01.bit._ICP0\r
+#define OCS01_ICE1 ocs01.bit._ICE1\r
+#define OCS01_ICE0 ocs01.bit._ICE0\r
+#define OCS01_CST1 ocs01.bit._CST1\r
+#define OCS01_CST0 ocs01.bit._CST0\r
+__IO_EXTERN OCS23STR ocs23; \r
+#define OCS23 ocs23.word\r
+#define OCS23_CMOD ocs23.bit._CMOD\r
+#define OCS23_OTD3 ocs23.bit._OTD3\r
+#define OCS23_OTD2 ocs23.bit._OTD2\r
+#define OCS23_ICP3 ocs23.bit._ICP3\r
+#define OCS23_ICP2 ocs23.bit._ICP2\r
+#define OCS23_ICE3 ocs23.bit._ICE3\r
+#define OCS23_ICE2 ocs23.bit._ICE2\r
+#define OCS23_CST3 ocs23.bit._CST3\r
+#define OCS23_CST2 ocs23.bit._CST2\r
+__IO_EXTERN OCCP0STR occp0; \r
+#define OCCP0 occp0.word\r
+#define OCCP0_C15 occp0.bit._C15\r
+#define OCCP0_C14 occp0.bit._C14\r
+#define OCCP0_C13 occp0.bit._C13\r
+#define OCCP0_C12 occp0.bit._C12\r
+#define OCCP0_C11 occp0.bit._C11\r
+#define OCCP0_C10 occp0.bit._C10\r
+#define OCCP0_C9 occp0.bit._C9\r
+#define OCCP0_C8 occp0.bit._C8\r
+#define OCCP0_C7 occp0.bit._C7\r
+#define OCCP0_C6 occp0.bit._C6\r
+#define OCCP0_C5 occp0.bit._C5\r
+#define OCCP0_C4 occp0.bit._C4\r
+#define OCCP0_C3 occp0.bit._C3\r
+#define OCCP0_C2 occp0.bit._C2\r
+#define OCCP0_C1 occp0.bit._C1\r
+#define OCCP0_C0 occp0.bit._C0\r
+__IO_EXTERN OCCP1STR occp1; \r
+#define OCCP1 occp1.word\r
+#define OCCP1_C15 occp1.bit._C15\r
+#define OCCP1_C14 occp1.bit._C14\r
+#define OCCP1_C13 occp1.bit._C13\r
+#define OCCP1_C12 occp1.bit._C12\r
+#define OCCP1_C11 occp1.bit._C11\r
+#define OCCP1_C10 occp1.bit._C10\r
+#define OCCP1_C9 occp1.bit._C9\r
+#define OCCP1_C8 occp1.bit._C8\r
+#define OCCP1_C7 occp1.bit._C7\r
+#define OCCP1_C6 occp1.bit._C6\r
+#define OCCP1_C5 occp1.bit._C5\r
+#define OCCP1_C4 occp1.bit._C4\r
+#define OCCP1_C3 occp1.bit._C3\r
+#define OCCP1_C2 occp1.bit._C2\r
+#define OCCP1_C1 occp1.bit._C1\r
+#define OCCP1_C0 occp1.bit._C0\r
+__IO_EXTERN OCCP2STR occp2; \r
+#define OCCP2 occp2.word\r
+#define OCCP2_C15 occp2.bit._C15\r
+#define OCCP2_C14 occp2.bit._C14\r
+#define OCCP2_C13 occp2.bit._C13\r
+#define OCCP2_C12 occp2.bit._C12\r
+#define OCCP2_C11 occp2.bit._C11\r
+#define OCCP2_C10 occp2.bit._C10\r
+#define OCCP2_C9 occp2.bit._C9\r
+#define OCCP2_C8 occp2.bit._C8\r
+#define OCCP2_C7 occp2.bit._C7\r
+#define OCCP2_C6 occp2.bit._C6\r
+#define OCCP2_C5 occp2.bit._C5\r
+#define OCCP2_C4 occp2.bit._C4\r
+#define OCCP2_C3 occp2.bit._C3\r
+#define OCCP2_C2 occp2.bit._C2\r
+#define OCCP2_C1 occp2.bit._C1\r
+#define OCCP2_C0 occp2.bit._C0\r
+__IO_EXTERN OCCP3STR occp3; \r
+#define OCCP3 occp3.word\r
+#define OCCP3_C15 occp3.bit._C15\r
+#define OCCP3_C14 occp3.bit._C14\r
+#define OCCP3_C13 occp3.bit._C13\r
+#define OCCP3_C12 occp3.bit._C12\r
+#define OCCP3_C11 occp3.bit._C11\r
+#define OCCP3_C10 occp3.bit._C10\r
+#define OCCP3_C9 occp3.bit._C9\r
+#define OCCP3_C8 occp3.bit._C8\r
+#define OCCP3_C7 occp3.bit._C7\r
+#define OCCP3_C6 occp3.bit._C6\r
+#define OCCP3_C5 occp3.bit._C5\r
+#define OCCP3_C4 occp3.bit._C4\r
+#define OCCP3_C3 occp3.bit._C3\r
+#define OCCP3_C2 occp3.bit._C2\r
+#define OCCP3_C1 occp3.bit._C1\r
+#define OCCP3_C0 occp3.bit._C0\r
+__IO_EXTERN ADERHSTR aderh; /* ADC */\r
+#define ADERH aderh.word\r
+#define ADERH_ADE31 aderh.bit._ADE31\r
+#define ADERH_ADE30 aderh.bit._ADE30\r
+#define ADERH_ADE29 aderh.bit._ADE29\r
+#define ADERH_ADE28 aderh.bit._ADE28\r
+#define ADERH_ADE27 aderh.bit._ADE27\r
+#define ADERH_ADE26 aderh.bit._ADE26\r
+#define ADERH_ADE25 aderh.bit._ADE25\r
+#define ADERH_ADE24 aderh.bit._ADE24\r
+#define ADERH_ADE23 aderh.bit._ADE23\r
+#define ADERH_ADE22 aderh.bit._ADE22\r
+#define ADERH_ADE21 aderh.bit._ADE21\r
+#define ADERH_ADE20 aderh.bit._ADE20\r
+#define ADERH_ADE19 aderh.bit._ADE19\r
+#define ADERH_ADE18 aderh.bit._ADE18\r
+#define ADERH_ADE17 aderh.bit._ADE17\r
+#define ADERH_ADE16 aderh.bit._ADE16\r
+__IO_EXTERN ADERLSTR aderl; \r
+#define ADERL aderl.word\r
+#define ADERL_ADE15 aderl.bit._ADE15\r
+#define ADERL_ADE14 aderl.bit._ADE14\r
+#define ADERL_ADE13 aderl.bit._ADE13\r
+#define ADERL_ADE12 aderl.bit._ADE12\r
+#define ADERL_ADE11 aderl.bit._ADE11\r
+#define ADERL_ADE10 aderl.bit._ADE10\r
+#define ADERL_ADE9 aderl.bit._ADE9\r
+#define ADERL_ADE8 aderl.bit._ADE8\r
+#define ADERL_ADE7 aderl.bit._ADE7\r
+#define ADERL_ADE6 aderl.bit._ADE6\r
+#define ADERL_ADE5 aderl.bit._ADE5\r
+#define ADERL_ADE4 aderl.bit._ADE4\r
+#define ADERL_ADE3 aderl.bit._ADE3\r
+#define ADERL_ADE2 aderl.bit._ADE2\r
+#define ADERL_ADE1 aderl.bit._ADE1\r
+#define ADERL_ADE0 aderl.bit._ADE0\r
+__IO_EXTERN IO_LWORD ader; \r
+#define ADER ader\r
+__IO_EXTERN ADCS1STR adcs1; \r
+#define ADCS1 adcs1.byte\r
+#define ADCS1_BUSY adcs1.bit._BUSY\r
+#define ADCS1_INT adcs1.bit._INT\r
+#define ADCS1_INTE adcs1.bit._INTE\r
+#define ADCS1_PAUS adcs1.bit._PAUS\r
+#define ADCS1_STS1 adcs1.bit._STS1\r
+#define ADCS1_STS0 adcs1.bit._STS0\r
+#define ADCS1_STRT adcs1.bit._STRT\r
+#define ADCS1_STS adcs1.bitc._STS\r
+__IO_EXTERN ADCS0STR adcs0; \r
+#define ADCS0 adcs0.byte\r
+#define ADCS0_MD1 adcs0.bit._MD1\r
+#define ADCS0_MD0 adcs0.bit._MD0\r
+#define ADCS0_S10 adcs0.bit._S10\r
+#define ADCS0_ACH4 adcs0.bit._ACH4\r
+#define ADCS0_ACH3 adcs0.bit._ACH3\r
+#define ADCS0_ACH2 adcs0.bit._ACH2\r
+#define ADCS0_ACH1 adcs0.bit._ACH1\r
+#define ADCS0_ACH0 adcs0.bit._ACH0\r
+#define ADCS0_MD adcs0.bitc._MD\r
+#define ADCS0_ACH adcs0.bitc._ACH\r
+__IO_EXTERN IO_WORD adcs; \r
+#define ADCS adcs\r
+__IO_EXTERN ADCR1STR adcr1; \r
+#define ADCR1 adcr1.byte\r
+#define ADCR1_D9 adcr1.bit._D9\r
+#define ADCR1_D8 adcr1.bit._D8\r
+__IO_EXTERN ADCR0STR adcr0; \r
+#define ADCR0 adcr0.byte\r
+#define ADCR0_D7 adcr0.bit._D7\r
+#define ADCR0_D6 adcr0.bit._D6\r
+#define ADCR0_D5 adcr0.bit._D5\r
+#define ADCR0_D4 adcr0.bit._D4\r
+#define ADCR0_D3 adcr0.bit._D3\r
+#define ADCR0_D2 adcr0.bit._D2\r
+#define ADCR0_D1 adcr0.bit._D1\r
+#define ADCR0_D0 adcr0.bit._D0\r
+__IO_EXTERN IO_WORD adcr; \r
+#define ADCR adcr\r
+__IO_EXTERN ADCT1STR adct1; \r
+#define ADCT1 adct1.byte\r
+#define ADCT1_CT5 adct1.bit._CT5\r
+#define ADCT1_CT4 adct1.bit._CT4\r
+#define ADCT1_CT3 adct1.bit._CT3\r
+#define ADCT1_CT2 adct1.bit._CT2\r
+#define ADCT1_CT1 adct1.bit._CT1\r
+#define ADCT1_CT0 adct1.bit._CT0\r
+#define ADCT1_ST9 adct1.bit._ST9\r
+#define ADCT1_ST8 adct1.bit._ST8\r
+__IO_EXTERN ADCT0STR adct0; \r
+#define ADCT0 adct0.byte\r
+#define ADCT0_ST7 adct0.bit._ST7\r
+#define ADCT0_ST6 adct0.bit._ST6\r
+#define ADCT0_ST5 adct0.bit._ST5\r
+#define ADCT0_ST4 adct0.bit._ST4\r
+#define ADCT0_ST3 adct0.bit._ST3\r
+#define ADCT0_ST2 adct0.bit._ST2\r
+#define ADCT0_ST1 adct0.bit._ST1\r
+#define ADCT0_ST0 adct0.bit._ST0\r
+__IO_EXTERN IO_WORD adct; \r
+#define ADCT adct\r
+__IO_EXTERN ADSCHSTR adsch; \r
+#define ADSCH adsch.byte\r
+#define ADSCH_ANS4 adsch.bit._ANS4\r
+#define ADSCH_ANS3 adsch.bit._ANS3\r
+#define ADSCH_ANS2 adsch.bit._ANS2\r
+#define ADSCH_ANS1 adsch.bit._ANS1\r
+#define ADSCH_ASN0 adsch.bit._ASN0\r
+#define ADSCH_ANS adsch.bitc._ANS\r
+__IO_EXTERN ADECHSTR adech; \r
+#define ADECH adech.byte\r
+#define ADECH_ANE4 adech.bit._ANE4\r
+#define ADECH_ANE3 adech.bit._ANE3\r
+#define ADECH_ANE2 adech.bit._ANE2\r
+#define ADECH_ANE1 adech.bit._ANE1\r
+#define ADECH_ANE0 adech.bit._ANE0\r
+#define ADECH_ANE adech.bitc._ANE\r
+__IO_EXTERN TMRLR0STR tmrlr0; /* Reload Timer 0 */\r
+#define TMRLR0 tmrlr0.word\r
+#define TMRLR0_D15 tmrlr0.bit._D15\r
+#define TMRLR0_D14 tmrlr0.bit._D14\r
+#define TMRLR0_D13 tmrlr0.bit._D13\r
+#define TMRLR0_D12 tmrlr0.bit._D12\r
+#define TMRLR0_D11 tmrlr0.bit._D11\r
+#define TMRLR0_D10 tmrlr0.bit._D10\r
+#define TMRLR0_D9 tmrlr0.bit._D9\r
+#define TMRLR0_D8 tmrlr0.bit._D8\r
+#define TMRLR0_D7 tmrlr0.bit._D7\r
+#define TMRLR0_D6 tmrlr0.bit._D6\r
+#define TMRLR0_D5 tmrlr0.bit._D5\r
+#define TMRLR0_D4 tmrlr0.bit._D4\r
+#define TMRLR0_D3 tmrlr0.bit._D3\r
+#define TMRLR0_D2 tmrlr0.bit._D2\r
+#define TMRLR0_D1 tmrlr0.bit._D1\r
+#define TMRLR0_D0 tmrlr0.bit._D0\r
+__IO_EXTERN TMR0STR tmr0; \r
+#define TMR0 tmr0.word\r
+#define TMR0_D15 tmr0.bit._D15\r
+#define TMR0_D14 tmr0.bit._D14\r
+#define TMR0_D13 tmr0.bit._D13\r
+#define TMR0_D12 tmr0.bit._D12\r
+#define TMR0_D11 tmr0.bit._D11\r
+#define TMR0_D10 tmr0.bit._D10\r
+#define TMR0_D9 tmr0.bit._D9\r
+#define TMR0_D8 tmr0.bit._D8\r
+#define TMR0_D7 tmr0.bit._D7\r
+#define TMR0_D6 tmr0.bit._D6\r
+#define TMR0_D5 tmr0.bit._D5\r
+#define TMR0_D4 tmr0.bit._D4\r
+#define TMR0_D3 tmr0.bit._D3\r
+#define TMR0_D2 tmr0.bit._D2\r
+#define TMR0_D1 tmr0.bit._D1\r
+#define TMR0_D0 tmr0.bit._D0\r
+__IO_EXTERN TMCSR0STR tmcsr0; \r
+#define TMCSR0 tmcsr0.word\r
+#define TMCSR0_CSL2 tmcsr0.bit._CSL2\r
+#define TMCSR0_CSL1 tmcsr0.bit._CSL1\r
+#define TMCSR0_CSL0 tmcsr0.bit._CSL0\r
+#define TMCSR0_MOD2 tmcsr0.bit._MOD2\r
+#define TMCSR0_MOD1 tmcsr0.bit._MOD1\r
+#define TMCSR0_MOD0 tmcsr0.bit._MOD0\r
+#define TMCSR0_OULT tmcsr0.bit._OULT\r
+#define TMCSR0_RELD tmcsr0.bit._RELD\r
+#define TMCSR0_INTE tmcsr0.bit._INTE\r
+#define TMCSR0_UF tmcsr0.bit._UF\r
+#define TMCSR0_CNTE tmcsr0.bit._CNTE\r
+#define TMCSR0_TRG tmcsr0.bit._TRG\r
+#define TMCSR0_CSL tmcsr0.bitc._CSL\r
+#define TMCSR0_MOD tmcsr0.bitc._MOD\r
+__IO_EXTERN TMCSRH0STR tmcsrh0; \r
+#define TMCSRH0 tmcsrh0.byte\r
+#define TMCSRH0_CSL2 tmcsrh0.bit._CSL2\r
+#define TMCSRH0_CSL1 tmcsrh0.bit._CSL1\r
+#define TMCSRH0_CSL0 tmcsrh0.bit._CSL0\r
+#define TMCSRH0_MOD2 tmcsrh0.bit._MOD2\r
+#define TMCSRH0_MOD1 tmcsrh0.bit._MOD1\r
+#define TMCSRH0_CSL tmcsrh0.bitc._CSL\r
+__IO_EXTERN TMCSRL0STR tmcsrl0; \r
+#define TMCSRL0 tmcsrl0.byte\r
+#define TMCSRL0_MOD0 tmcsrl0.bit._MOD0\r
+#define TMCSRL0_OULT tmcsrl0.bit._OULT\r
+#define TMCSRL0_RELD tmcsrl0.bit._RELD\r
+#define TMCSRL0_INTE tmcsrl0.bit._INTE\r
+#define TMCSRL0_UF tmcsrl0.bit._UF\r
+#define TMCSRL0_CNTE tmcsrl0.bit._CNTE\r
+#define TMCSRL0_TRG tmcsrl0.bit._TRG\r
+__IO_EXTERN TMRLR1STR tmrlr1; /* Reload Timer 1 */\r
+#define TMRLR1 tmrlr1.word\r
+#define TMRLR1_D15 tmrlr1.bit._D15\r
+#define TMRLR1_D14 tmrlr1.bit._D14\r
+#define TMRLR1_D13 tmrlr1.bit._D13\r
+#define TMRLR1_D12 tmrlr1.bit._D12\r
+#define TMRLR1_D11 tmrlr1.bit._D11\r
+#define TMRLR1_D10 tmrlr1.bit._D10\r
+#define TMRLR1_D9 tmrlr1.bit._D9\r
+#define TMRLR1_D8 tmrlr1.bit._D8\r
+#define TMRLR1_D7 tmrlr1.bit._D7\r
+#define TMRLR1_D6 tmrlr1.bit._D6\r
+#define TMRLR1_D5 tmrlr1.bit._D5\r
+#define TMRLR1_D4 tmrlr1.bit._D4\r
+#define TMRLR1_D3 tmrlr1.bit._D3\r
+#define TMRLR1_D2 tmrlr1.bit._D2\r
+#define TMRLR1_D1 tmrlr1.bit._D1\r
+#define TMRLR1_D0 tmrlr1.bit._D0\r
+__IO_EXTERN TMR1STR tmr1; \r
+#define TMR1 tmr1.word\r
+#define TMR1_D15 tmr1.bit._D15\r
+#define TMR1_D14 tmr1.bit._D14\r
+#define TMR1_D13 tmr1.bit._D13\r
+#define TMR1_D12 tmr1.bit._D12\r
+#define TMR1_D11 tmr1.bit._D11\r
+#define TMR1_D10 tmr1.bit._D10\r
+#define TMR1_D9 tmr1.bit._D9\r
+#define TMR1_D8 tmr1.bit._D8\r
+#define TMR1_D7 tmr1.bit._D7\r
+#define TMR1_D6 tmr1.bit._D6\r
+#define TMR1_D5 tmr1.bit._D5\r
+#define TMR1_D4 tmr1.bit._D4\r
+#define TMR1_D3 tmr1.bit._D3\r
+#define TMR1_D2 tmr1.bit._D2\r
+#define TMR1_D1 tmr1.bit._D1\r
+#define TMR1_D0 tmr1.bit._D0\r
+__IO_EXTERN TMCSR1STR tmcsr1; \r
+#define TMCSR1 tmcsr1.word\r
+#define TMCSR1_CSL2 tmcsr1.bit._CSL2\r
+#define TMCSR1_CSL1 tmcsr1.bit._CSL1\r
+#define TMCSR1_CSL0 tmcsr1.bit._CSL0\r
+#define TMCSR1_MOD2 tmcsr1.bit._MOD2\r
+#define TMCSR1_MOD1 tmcsr1.bit._MOD1\r
+#define TMCSR1_MOD0 tmcsr1.bit._MOD0\r
+#define TMCSR1_OULT tmcsr1.bit._OULT\r
+#define TMCSR1_RELD tmcsr1.bit._RELD\r
+#define TMCSR1_INTE tmcsr1.bit._INTE\r
+#define TMCSR1_UF tmcsr1.bit._UF\r
+#define TMCSR1_CNTE tmcsr1.bit._CNTE\r
+#define TMCSR1_TRG tmcsr1.bit._TRG\r
+#define TMCSR1_CSL tmcsr1.bitc._CSL\r
+#define TMCSR1_MOD tmcsr1.bitc._MOD\r
+__IO_EXTERN TMCSRH1STR tmcsrh1; \r
+#define TMCSRH1 tmcsrh1.byte\r
+#define TMCSRH1_CSL2 tmcsrh1.bit._CSL2\r
+#define TMCSRH1_CSL1 tmcsrh1.bit._CSL1\r
+#define TMCSRH1_CSL0 tmcsrh1.bit._CSL0\r
+#define TMCSRH1_MOD2 tmcsrh1.bit._MOD2\r
+#define TMCSRH1_MOD1 tmcsrh1.bit._MOD1\r
+#define TMCSRH1_CSL tmcsrh1.bitc._CSL\r
+__IO_EXTERN TMCSRL1STR tmcsrl1; \r
+#define TMCSRL1 tmcsrl1.byte\r
+#define TMCSRL1_MOD0 tmcsrl1.bit._MOD0\r
+#define TMCSRL1_OULT tmcsrl1.bit._OULT\r
+#define TMCSRL1_RELD tmcsrl1.bit._RELD\r
+#define TMCSRL1_INTE tmcsrl1.bit._INTE\r
+#define TMCSRL1_UF tmcsrl1.bit._UF\r
+#define TMCSRL1_CNTE tmcsrl1.bit._CNTE\r
+#define TMCSRL1_TRG tmcsrl1.bit._TRG\r
+__IO_EXTERN TMRLR2STR tmrlr2; /* Reload Timer 2 */\r
+#define TMRLR2 tmrlr2.word\r
+#define TMRLR2_D15 tmrlr2.bit._D15\r
+#define TMRLR2_D14 tmrlr2.bit._D14\r
+#define TMRLR2_D13 tmrlr2.bit._D13\r
+#define TMRLR2_D12 tmrlr2.bit._D12\r
+#define TMRLR2_D11 tmrlr2.bit._D11\r
+#define TMRLR2_D10 tmrlr2.bit._D10\r
+#define TMRLR2_D9 tmrlr2.bit._D9\r
+#define TMRLR2_D8 tmrlr2.bit._D8\r
+#define TMRLR2_D7 tmrlr2.bit._D7\r
+#define TMRLR2_D6 tmrlr2.bit._D6\r
+#define TMRLR2_D5 tmrlr2.bit._D5\r
+#define TMRLR2_D4 tmrlr2.bit._D4\r
+#define TMRLR2_D3 tmrlr2.bit._D3\r
+#define TMRLR2_D2 tmrlr2.bit._D2\r
+#define TMRLR2_D1 tmrlr2.bit._D1\r
+#define TMRLR2_D0 tmrlr2.bit._D0\r
+__IO_EXTERN TMR2STR tmr2; \r
+#define TMR2 tmr2.word\r
+#define TMR2_D15 tmr2.bit._D15\r
+#define TMR2_D14 tmr2.bit._D14\r
+#define TMR2_D13 tmr2.bit._D13\r
+#define TMR2_D12 tmr2.bit._D12\r
+#define TMR2_D11 tmr2.bit._D11\r
+#define TMR2_D10 tmr2.bit._D10\r
+#define TMR2_D9 tmr2.bit._D9\r
+#define TMR2_D8 tmr2.bit._D8\r
+#define TMR2_D7 tmr2.bit._D7\r
+#define TMR2_D6 tmr2.bit._D6\r
+#define TMR2_D5 tmr2.bit._D5\r
+#define TMR2_D4 tmr2.bit._D4\r
+#define TMR2_D3 tmr2.bit._D3\r
+#define TMR2_D2 tmr2.bit._D2\r
+#define TMR2_D1 tmr2.bit._D1\r
+#define TMR2_D0 tmr2.bit._D0\r
+__IO_EXTERN TMCSR2STR tmcsr2; \r
+#define TMCSR2 tmcsr2.word\r
+#define TMCSR2_CSL2 tmcsr2.bit._CSL2\r
+#define TMCSR2_CSL1 tmcsr2.bit._CSL1\r
+#define TMCSR2_CSL0 tmcsr2.bit._CSL0\r
+#define TMCSR2_MOD2 tmcsr2.bit._MOD2\r
+#define TMCSR2_MOD1 tmcsr2.bit._MOD1\r
+#define TMCSR2_MOD0 tmcsr2.bit._MOD0\r
+#define TMCSR2_OULT tmcsr2.bit._OULT\r
+#define TMCSR2_RELD tmcsr2.bit._RELD\r
+#define TMCSR2_INTE tmcsr2.bit._INTE\r
+#define TMCSR2_UF tmcsr2.bit._UF\r
+#define TMCSR2_CNTE tmcsr2.bit._CNTE\r
+#define TMCSR2_TRG tmcsr2.bit._TRG\r
+#define TMCSR2_CSL tmcsr2.bitc._CSL\r
+#define TMCSR2_MOD tmcsr2.bitc._MOD\r
+__IO_EXTERN TMCSRH2STR tmcsrh2; \r
+#define TMCSRH2 tmcsrh2.byte\r
+#define TMCSRH2_CSL2 tmcsrh2.bit._CSL2\r
+#define TMCSRH2_CSL1 tmcsrh2.bit._CSL1\r
+#define TMCSRH2_CSL0 tmcsrh2.bit._CSL0\r
+#define TMCSRH2_MOD2 tmcsrh2.bit._MOD2\r
+#define TMCSRH2_MOD1 tmcsrh2.bit._MOD1\r
+#define TMCSRH2_CSL tmcsrh2.bitc._CSL\r
+__IO_EXTERN TMCSRL2STR tmcsrl2; \r
+#define TMCSRL2 tmcsrl2.byte\r
+#define TMCSRL2_MOD0 tmcsrl2.bit._MOD0\r
+#define TMCSRL2_OULT tmcsrl2.bit._OULT\r
+#define TMCSRL2_RELD tmcsrl2.bit._RELD\r
+#define TMCSRL2_INTE tmcsrl2.bit._INTE\r
+#define TMCSRL2_UF tmcsrl2.bit._UF\r
+#define TMCSRL2_CNTE tmcsrl2.bit._CNTE\r
+#define TMCSRL2_TRG tmcsrl2.bit._TRG\r
+__IO_EXTERN TMRLR3STR tmrlr3; /* Reload Timer 3 */\r
+#define TMRLR3 tmrlr3.word\r
+#define TMRLR3_D15 tmrlr3.bit._D15\r
+#define TMRLR3_D14 tmrlr3.bit._D14\r
+#define TMRLR3_D13 tmrlr3.bit._D13\r
+#define TMRLR3_D12 tmrlr3.bit._D12\r
+#define TMRLR3_D11 tmrlr3.bit._D11\r
+#define TMRLR3_D10 tmrlr3.bit._D10\r
+#define TMRLR3_D9 tmrlr3.bit._D9\r
+#define TMRLR3_D8 tmrlr3.bit._D8\r
+#define TMRLR3_D7 tmrlr3.bit._D7\r
+#define TMRLR3_D6 tmrlr3.bit._D6\r
+#define TMRLR3_D5 tmrlr3.bit._D5\r
+#define TMRLR3_D4 tmrlr3.bit._D4\r
+#define TMRLR3_D3 tmrlr3.bit._D3\r
+#define TMRLR3_D2 tmrlr3.bit._D2\r
+#define TMRLR3_D1 tmrlr3.bit._D1\r
+#define TMRLR3_D0 tmrlr3.bit._D0\r
+__IO_EXTERN TMR3STR tmr3; \r
+#define TMR3 tmr3.word\r
+#define TMR3_D15 tmr3.bit._D15\r
+#define TMR3_D14 tmr3.bit._D14\r
+#define TMR3_D13 tmr3.bit._D13\r
+#define TMR3_D12 tmr3.bit._D12\r
+#define TMR3_D11 tmr3.bit._D11\r
+#define TMR3_D10 tmr3.bit._D10\r
+#define TMR3_D9 tmr3.bit._D9\r
+#define TMR3_D8 tmr3.bit._D8\r
+#define TMR3_D7 tmr3.bit._D7\r
+#define TMR3_D6 tmr3.bit._D6\r
+#define TMR3_D5 tmr3.bit._D5\r
+#define TMR3_D4 tmr3.bit._D4\r
+#define TMR3_D3 tmr3.bit._D3\r
+#define TMR3_D2 tmr3.bit._D2\r
+#define TMR3_D1 tmr3.bit._D1\r
+#define TMR3_D0 tmr3.bit._D0\r
+__IO_EXTERN TMCSR3STR tmcsr3; \r
+#define TMCSR3 tmcsr3.word\r
+#define TMCSR3_CSL2 tmcsr3.bit._CSL2\r
+#define TMCSR3_CSL1 tmcsr3.bit._CSL1\r
+#define TMCSR3_CSL0 tmcsr3.bit._CSL0\r
+#define TMCSR3_MOD2 tmcsr3.bit._MOD2\r
+#define TMCSR3_MOD1 tmcsr3.bit._MOD1\r
+#define TMCSR3_MOD0 tmcsr3.bit._MOD0\r
+#define TMCSR3_OULT tmcsr3.bit._OULT\r
+#define TMCSR3_RELD tmcsr3.bit._RELD\r
+#define TMCSR3_INTE tmcsr3.bit._INTE\r
+#define TMCSR3_UF tmcsr3.bit._UF\r
+#define TMCSR3_CNTE tmcsr3.bit._CNTE\r
+#define TMCSR3_TRG tmcsr3.bit._TRG\r
+#define TMCSR3_CSL tmcsr3.bitc._CSL\r
+#define TMCSR3_MOD tmcsr3.bitc._MOD\r
+__IO_EXTERN TMCSRH3STR tmcsrh3; \r
+#define TMCSRH3 tmcsrh3.byte\r
+#define TMCSRH3_CSL2 tmcsrh3.bit._CSL2\r
+#define TMCSRH3_CSL1 tmcsrh3.bit._CSL1\r
+#define TMCSRH3_CSL0 tmcsrh3.bit._CSL0\r
+#define TMCSRH3_MOD2 tmcsrh3.bit._MOD2\r
+#define TMCSRH3_MOD1 tmcsrh3.bit._MOD1\r
+#define TMCSRH3_CSL tmcsrh3.bitc._CSL\r
+__IO_EXTERN TMCSRL3STR tmcsrl3; \r
+#define TMCSRL3 tmcsrl3.byte\r
+#define TMCSRL3_MOD0 tmcsrl3.bit._MOD0\r
+#define TMCSRL3_OULT tmcsrl3.bit._OULT\r
+#define TMCSRL3_RELD tmcsrl3.bit._RELD\r
+#define TMCSRL3_INTE tmcsrl3.bit._INTE\r
+#define TMCSRL3_UF tmcsrl3.bit._UF\r
+#define TMCSRL3_CNTE tmcsrl3.bit._CNTE\r
+#define TMCSRL3_TRG tmcsrl3.bit._TRG\r
+__IO_EXTERN TMRLR4STR tmrlr4; /* Reload Timer 4 */\r
+#define TMRLR4 tmrlr4.word\r
+#define TMRLR4_D15 tmrlr4.bit._D15\r
+#define TMRLR4_D14 tmrlr4.bit._D14\r
+#define TMRLR4_D13 tmrlr4.bit._D13\r
+#define TMRLR4_D12 tmrlr4.bit._D12\r
+#define TMRLR4_D11 tmrlr4.bit._D11\r
+#define TMRLR4_D10 tmrlr4.bit._D10\r
+#define TMRLR4_D9 tmrlr4.bit._D9\r
+#define TMRLR4_D8 tmrlr4.bit._D8\r
+#define TMRLR4_D7 tmrlr4.bit._D7\r
+#define TMRLR4_D6 tmrlr4.bit._D6\r
+#define TMRLR4_D5 tmrlr4.bit._D5\r
+#define TMRLR4_D4 tmrlr4.bit._D4\r
+#define TMRLR4_D3 tmrlr4.bit._D3\r
+#define TMRLR4_D2 tmrlr4.bit._D2\r
+#define TMRLR4_D1 tmrlr4.bit._D1\r
+#define TMRLR4_D0 tmrlr4.bit._D0\r
+__IO_EXTERN TMR4STR tmr4; \r
+#define TMR4 tmr4.word\r
+#define TMR4_D15 tmr4.bit._D15\r
+#define TMR4_D14 tmr4.bit._D14\r
+#define TMR4_D13 tmr4.bit._D13\r
+#define TMR4_D12 tmr4.bit._D12\r
+#define TMR4_D11 tmr4.bit._D11\r
+#define TMR4_D10 tmr4.bit._D10\r
+#define TMR4_D9 tmr4.bit._D9\r
+#define TMR4_D8 tmr4.bit._D8\r
+#define TMR4_D7 tmr4.bit._D7\r
+#define TMR4_D6 tmr4.bit._D6\r
+#define TMR4_D5 tmr4.bit._D5\r
+#define TMR4_D4 tmr4.bit._D4\r
+#define TMR4_D3 tmr4.bit._D3\r
+#define TMR4_D2 tmr4.bit._D2\r
+#define TMR4_D1 tmr4.bit._D1\r
+#define TMR4_D0 tmr4.bit._D0\r
+__IO_EXTERN TMCSR4STR tmcsr4; \r
+#define TMCSR4 tmcsr4.word\r
+#define TMCSR4_CSL2 tmcsr4.bit._CSL2\r
+#define TMCSR4_CSL1 tmcsr4.bit._CSL1\r
+#define TMCSR4_CSL0 tmcsr4.bit._CSL0\r
+#define TMCSR4_MOD2 tmcsr4.bit._MOD2\r
+#define TMCSR4_MOD1 tmcsr4.bit._MOD1\r
+#define TMCSR4_MOD0 tmcsr4.bit._MOD0\r
+#define TMCSR4_OULT tmcsr4.bit._OULT\r
+#define TMCSR4_RELD tmcsr4.bit._RELD\r
+#define TMCSR4_INTE tmcsr4.bit._INTE\r
+#define TMCSR4_UF tmcsr4.bit._UF\r
+#define TMCSR4_CNTE tmcsr4.bit._CNTE\r
+#define TMCSR4_TRG tmcsr4.bit._TRG\r
+#define TMCSR4_CSL tmcsr4.bitc._CSL\r
+#define TMCSR4_MOD tmcsr4.bitc._MOD\r
+__IO_EXTERN TMCSRH4STR tmcsrh4; \r
+#define TMCSRH4 tmcsrh4.byte\r
+#define TMCSRH4_CSL2 tmcsrh4.bit._CSL2\r
+#define TMCSRH4_CSL1 tmcsrh4.bit._CSL1\r
+#define TMCSRH4_CSL0 tmcsrh4.bit._CSL0\r
+#define TMCSRH4_MOD2 tmcsrh4.bit._MOD2\r
+#define TMCSRH4_MOD1 tmcsrh4.bit._MOD1\r
+#define TMCSRH4_CSL tmcsrh4.bitc._CSL\r
+__IO_EXTERN TMCSRL4STR tmcsrl4; \r
+#define TMCSRL4 tmcsrl4.byte\r
+#define TMCSRL4_MOD0 tmcsrl4.bit._MOD0\r
+#define TMCSRL4_OULT tmcsrl4.bit._OULT\r
+#define TMCSRL4_RELD tmcsrl4.bit._RELD\r
+#define TMCSRL4_INTE tmcsrl4.bit._INTE\r
+#define TMCSRL4_UF tmcsrl4.bit._UF\r
+#define TMCSRL4_CNTE tmcsrl4.bit._CNTE\r
+#define TMCSRL4_TRG tmcsrl4.bit._TRG\r
+__IO_EXTERN TMRLR5STR tmrlr5; /* Reload Timer 5 */\r
+#define TMRLR5 tmrlr5.word\r
+#define TMRLR5_D15 tmrlr5.bit._D15\r
+#define TMRLR5_D14 tmrlr5.bit._D14\r
+#define TMRLR5_D13 tmrlr5.bit._D13\r
+#define TMRLR5_D12 tmrlr5.bit._D12\r
+#define TMRLR5_D11 tmrlr5.bit._D11\r
+#define TMRLR5_D10 tmrlr5.bit._D10\r
+#define TMRLR5_D9 tmrlr5.bit._D9\r
+#define TMRLR5_D8 tmrlr5.bit._D8\r
+#define TMRLR5_D7 tmrlr5.bit._D7\r
+#define TMRLR5_D6 tmrlr5.bit._D6\r
+#define TMRLR5_D5 tmrlr5.bit._D5\r
+#define TMRLR5_D4 tmrlr5.bit._D4\r
+#define TMRLR5_D3 tmrlr5.bit._D3\r
+#define TMRLR5_D2 tmrlr5.bit._D2\r
+#define TMRLR5_D1 tmrlr5.bit._D1\r
+#define TMRLR5_D0 tmrlr5.bit._D0\r
+__IO_EXTERN TMR5STR tmr5; \r
+#define TMR5 tmr5.word\r
+#define TMR5_D15 tmr5.bit._D15\r
+#define TMR5_D14 tmr5.bit._D14\r
+#define TMR5_D13 tmr5.bit._D13\r
+#define TMR5_D12 tmr5.bit._D12\r
+#define TMR5_D11 tmr5.bit._D11\r
+#define TMR5_D10 tmr5.bit._D10\r
+#define TMR5_D9 tmr5.bit._D9\r
+#define TMR5_D8 tmr5.bit._D8\r
+#define TMR5_D7 tmr5.bit._D7\r
+#define TMR5_D6 tmr5.bit._D6\r
+#define TMR5_D5 tmr5.bit._D5\r
+#define TMR5_D4 tmr5.bit._D4\r
+#define TMR5_D3 tmr5.bit._D3\r
+#define TMR5_D2 tmr5.bit._D2\r
+#define TMR5_D1 tmr5.bit._D1\r
+#define TMR5_D0 tmr5.bit._D0\r
+__IO_EXTERN TMCSR5STR tmcsr5; \r
+#define TMCSR5 tmcsr5.word\r
+#define TMCSR5_CSL2 tmcsr5.bit._CSL2\r
+#define TMCSR5_CSL1 tmcsr5.bit._CSL1\r
+#define TMCSR5_CSL0 tmcsr5.bit._CSL0\r
+#define TMCSR5_MOD2 tmcsr5.bit._MOD2\r
+#define TMCSR5_MOD1 tmcsr5.bit._MOD1\r
+#define TMCSR5_MOD0 tmcsr5.bit._MOD0\r
+#define TMCSR5_OULT tmcsr5.bit._OULT\r
+#define TMCSR5_RELD tmcsr5.bit._RELD\r
+#define TMCSR5_INTE tmcsr5.bit._INTE\r
+#define TMCSR5_UF tmcsr5.bit._UF\r
+#define TMCSR5_CNTE tmcsr5.bit._CNTE\r
+#define TMCSR5_TRG tmcsr5.bit._TRG\r
+#define TMCSR5_CSL tmcsr5.bitc._CSL\r
+#define TMCSR5_MOD tmcsr5.bitc._MOD\r
+__IO_EXTERN TMCSRH5STR tmcsrh5; \r
+#define TMCSRH5 tmcsrh5.byte\r
+#define TMCSRH5_CSL2 tmcsrh5.bit._CSL2\r
+#define TMCSRH5_CSL1 tmcsrh5.bit._CSL1\r
+#define TMCSRH5_CSL0 tmcsrh5.bit._CSL0\r
+#define TMCSRH5_MOD2 tmcsrh5.bit._MOD2\r
+#define TMCSRH5_MOD1 tmcsrh5.bit._MOD1\r
+#define TMCSRH5_CSL tmcsrh5.bitc._CSL\r
+__IO_EXTERN TMCSRL5STR tmcsrl5; \r
+#define TMCSRL5 tmcsrl5.byte\r
+#define TMCSRL5_MOD0 tmcsrl5.bit._MOD0\r
+#define TMCSRL5_OULT tmcsrl5.bit._OULT\r
+#define TMCSRL5_RELD tmcsrl5.bit._RELD\r
+#define TMCSRL5_INTE tmcsrl5.bit._INTE\r
+#define TMCSRL5_UF tmcsrl5.bit._UF\r
+#define TMCSRL5_CNTE tmcsrl5.bit._CNTE\r
+#define TMCSRL5_TRG tmcsrl5.bit._TRG\r
+__IO_EXTERN TMRLR6STR tmrlr6; /* Reload Timer 6 */\r
+#define TMRLR6 tmrlr6.word\r
+#define TMRLR6_D15 tmrlr6.bit._D15\r
+#define TMRLR6_D14 tmrlr6.bit._D14\r
+#define TMRLR6_D13 tmrlr6.bit._D13\r
+#define TMRLR6_D12 tmrlr6.bit._D12\r
+#define TMRLR6_D11 tmrlr6.bit._D11\r
+#define TMRLR6_D10 tmrlr6.bit._D10\r
+#define TMRLR6_D9 tmrlr6.bit._D9\r
+#define TMRLR6_D8 tmrlr6.bit._D8\r
+#define TMRLR6_D7 tmrlr6.bit._D7\r
+#define TMRLR6_D6 tmrlr6.bit._D6\r
+#define TMRLR6_D5 tmrlr6.bit._D5\r
+#define TMRLR6_D4 tmrlr6.bit._D4\r
+#define TMRLR6_D3 tmrlr6.bit._D3\r
+#define TMRLR6_D2 tmrlr6.bit._D2\r
+#define TMRLR6_D1 tmrlr6.bit._D1\r
+#define TMRLR6_D0 tmrlr6.bit._D0\r
+__IO_EXTERN TMR6STR tmr6; \r
+#define TMR6 tmr6.word\r
+#define TMR6_D15 tmr6.bit._D15\r
+#define TMR6_D14 tmr6.bit._D14\r
+#define TMR6_D13 tmr6.bit._D13\r
+#define TMR6_D12 tmr6.bit._D12\r
+#define TMR6_D11 tmr6.bit._D11\r
+#define TMR6_D10 tmr6.bit._D10\r
+#define TMR6_D9 tmr6.bit._D9\r
+#define TMR6_D8 tmr6.bit._D8\r
+#define TMR6_D7 tmr6.bit._D7\r
+#define TMR6_D6 tmr6.bit._D6\r
+#define TMR6_D5 tmr6.bit._D5\r
+#define TMR6_D4 tmr6.bit._D4\r
+#define TMR6_D3 tmr6.bit._D3\r
+#define TMR6_D2 tmr6.bit._D2\r
+#define TMR6_D1 tmr6.bit._D1\r
+#define TMR6_D0 tmr6.bit._D0\r
+__IO_EXTERN TMCSR6STR tmcsr6; \r
+#define TMCSR6 tmcsr6.word\r
+#define TMCSR6_CSL2 tmcsr6.bit._CSL2\r
+#define TMCSR6_CSL1 tmcsr6.bit._CSL1\r
+#define TMCSR6_CSL0 tmcsr6.bit._CSL0\r
+#define TMCSR6_MOD2 tmcsr6.bit._MOD2\r
+#define TMCSR6_MOD1 tmcsr6.bit._MOD1\r
+#define TMCSR6_MOD0 tmcsr6.bit._MOD0\r
+#define TMCSR6_OULT tmcsr6.bit._OULT\r
+#define TMCSR6_RELD tmcsr6.bit._RELD\r
+#define TMCSR6_INTE tmcsr6.bit._INTE\r
+#define TMCSR6_UF tmcsr6.bit._UF\r
+#define TMCSR6_CNTE tmcsr6.bit._CNTE\r
+#define TMCSR6_TRG tmcsr6.bit._TRG\r
+#define TMCSR6_CSL tmcsr6.bitc._CSL\r
+#define TMCSR6_MOD tmcsr6.bitc._MOD\r
+__IO_EXTERN TMCSRH6STR tmcsrh6; \r
+#define TMCSRH6 tmcsrh6.byte\r
+#define TMCSRH6_CSL2 tmcsrh6.bit._CSL2\r
+#define TMCSRH6_CSL1 tmcsrh6.bit._CSL1\r
+#define TMCSRH6_CSL0 tmcsrh6.bit._CSL0\r
+#define TMCSRH6_MOD2 tmcsrh6.bit._MOD2\r
+#define TMCSRH6_MOD1 tmcsrh6.bit._MOD1\r
+#define TMCSRH6_CSL tmcsrh6.bitc._CSL\r
+__IO_EXTERN TMCSRL6STR tmcsrl6; \r
+#define TMCSRL6 tmcsrl6.byte\r
+#define TMCSRL6_MOD0 tmcsrl6.bit._MOD0\r
+#define TMCSRL6_OULT tmcsrl6.bit._OULT\r
+#define TMCSRL6_RELD tmcsrl6.bit._RELD\r
+#define TMCSRL6_INTE tmcsrl6.bit._INTE\r
+#define TMCSRL6_UF tmcsrl6.bit._UF\r
+#define TMCSRL6_CNTE tmcsrl6.bit._CNTE\r
+#define TMCSRL6_TRG tmcsrl6.bit._TRG\r
+__IO_EXTERN TMRLR7STR tmrlr7; /* Reload Timer 7 */\r
+#define TMRLR7 tmrlr7.word\r
+#define TMRLR7_D15 tmrlr7.bit._D15\r
+#define TMRLR7_D14 tmrlr7.bit._D14\r
+#define TMRLR7_D13 tmrlr7.bit._D13\r
+#define TMRLR7_D12 tmrlr7.bit._D12\r
+#define TMRLR7_D11 tmrlr7.bit._D11\r
+#define TMRLR7_D10 tmrlr7.bit._D10\r
+#define TMRLR7_D9 tmrlr7.bit._D9\r
+#define TMRLR7_D8 tmrlr7.bit._D8\r
+#define TMRLR7_D7 tmrlr7.bit._D7\r
+#define TMRLR7_D6 tmrlr7.bit._D6\r
+#define TMRLR7_D5 tmrlr7.bit._D5\r
+#define TMRLR7_D4 tmrlr7.bit._D4\r
+#define TMRLR7_D3 tmrlr7.bit._D3\r
+#define TMRLR7_D2 tmrlr7.bit._D2\r
+#define TMRLR7_D1 tmrlr7.bit._D1\r
+#define TMRLR7_D0 tmrlr7.bit._D0\r
+__IO_EXTERN TMR7STR tmr7; \r
+#define TMR7 tmr7.word\r
+#define TMR7_D15 tmr7.bit._D15\r
+#define TMR7_D14 tmr7.bit._D14\r
+#define TMR7_D13 tmr7.bit._D13\r
+#define TMR7_D12 tmr7.bit._D12\r
+#define TMR7_D11 tmr7.bit._D11\r
+#define TMR7_D10 tmr7.bit._D10\r
+#define TMR7_D9 tmr7.bit._D9\r
+#define TMR7_D8 tmr7.bit._D8\r
+#define TMR7_D7 tmr7.bit._D7\r
+#define TMR7_D6 tmr7.bit._D6\r
+#define TMR7_D5 tmr7.bit._D5\r
+#define TMR7_D4 tmr7.bit._D4\r
+#define TMR7_D3 tmr7.bit._D3\r
+#define TMR7_D2 tmr7.bit._D2\r
+#define TMR7_D1 tmr7.bit._D1\r
+#define TMR7_D0 tmr7.bit._D0\r
+__IO_EXTERN TMCSR7STR tmcsr7; \r
+#define TMCSR7 tmcsr7.word\r
+#define TMCSR7_CSL2 tmcsr7.bit._CSL2\r
+#define TMCSR7_CSL1 tmcsr7.bit._CSL1\r
+#define TMCSR7_CSL0 tmcsr7.bit._CSL0\r
+#define TMCSR7_MOD2 tmcsr7.bit._MOD2\r
+#define TMCSR7_MOD1 tmcsr7.bit._MOD1\r
+#define TMCSR7_MOD0 tmcsr7.bit._MOD0\r
+#define TMCSR7_OULT tmcsr7.bit._OULT\r
+#define TMCSR7_RELD tmcsr7.bit._RELD\r
+#define TMCSR7_INTE tmcsr7.bit._INTE\r
+#define TMCSR7_UF tmcsr7.bit._UF\r
+#define TMCSR7_CNTE tmcsr7.bit._CNTE\r
+#define TMCSR7_TRG tmcsr7.bit._TRG\r
+#define TMCSR7_CSL tmcsr7.bitc._CSL\r
+#define TMCSR7_MOD tmcsr7.bitc._MOD\r
+__IO_EXTERN TMCSRH7STR tmcsrh7; \r
+#define TMCSRH7 tmcsrh7.byte\r
+#define TMCSRH7_CSL2 tmcsrh7.bit._CSL2\r
+#define TMCSRH7_CSL1 tmcsrh7.bit._CSL1\r
+#define TMCSRH7_CSL0 tmcsrh7.bit._CSL0\r
+#define TMCSRH7_MOD2 tmcsrh7.bit._MOD2\r
+#define TMCSRH7_MOD1 tmcsrh7.bit._MOD1\r
+#define TMCSRH7_CSL tmcsrh7.bitc._CSL\r
+__IO_EXTERN TMCSRL7STR tmcsrl7; \r
+#define TMCSRL7 tmcsrl7.byte\r
+#define TMCSRL7_MOD0 tmcsrl7.bit._MOD0\r
+#define TMCSRL7_OULT tmcsrl7.bit._OULT\r
+#define TMCSRL7_RELD tmcsrl7.bit._RELD\r
+#define TMCSRL7_INTE tmcsrl7.bit._INTE\r
+#define TMCSRL7_UF tmcsrl7.bit._UF\r
+#define TMCSRL7_CNTE tmcsrl7.bit._CNTE\r
+#define TMCSRL7_TRG tmcsrl7.bit._TRG\r
+__IO_EXTERN TCDT0STR tcdt0; /* Free Running Timer0 */\r
+#define TCDT0 tcdt0.word\r
+#define TCDT0_T15 tcdt0.bit._T15\r
+#define TCDT0_T14 tcdt0.bit._T14\r
+#define TCDT0_T13 tcdt0.bit._T13\r
+#define TCDT0_T12 tcdt0.bit._T12\r
+#define TCDT0_T11 tcdt0.bit._T11\r
+#define TCDT0_T10 tcdt0.bit._T10\r
+#define TCDT0_T9 tcdt0.bit._T9\r
+#define TCDT0_T8 tcdt0.bit._T8\r
+#define TCDT0_T7 tcdt0.bit._T7\r
+#define TCDT0_T6 tcdt0.bit._T6\r
+#define TCDT0_T5 tcdt0.bit._T5\r
+#define TCDT0_T4 tcdt0.bit._T4\r
+#define TCDT0_T3 tcdt0.bit._T3\r
+#define TCDT0_T2 tcdt0.bit._T2\r
+#define TCDT0_T1 tcdt0.bit._T1\r
+#define TCDT0_T0 tcdt0.bit._T0\r
+__IO_EXTERN TCCS0STR tccs0; \r
+#define TCCS0 tccs0.byte\r
+#define TCCS0_ECLK tccs0.bit._ECLK\r
+#define TCCS0_IVF tccs0.bit._IVF\r
+#define TCCS0_IVFE tccs0.bit._IVFE\r
+#define TCCS0_STOP tccs0.bit._STOP\r
+#define TCCS0_MODE tccs0.bit._MODE\r
+#define TCCS0_CLR tccs0.bit._CLR\r
+#define TCCS0_CLK1 tccs0.bit._CLK1\r
+#define TCCS0_CLK0 tccs0.bit._CLK0\r
+#define TCCS0_CLK tccs0.bitc._CLK\r
+__IO_EXTERN TCDT1STR tcdt1; /* Free Running Timer1 */\r
+#define TCDT1 tcdt1.word\r
+#define TCDT1_T15 tcdt1.bit._T15\r
+#define TCDT1_T14 tcdt1.bit._T14\r
+#define TCDT1_T13 tcdt1.bit._T13\r
+#define TCDT1_T12 tcdt1.bit._T12\r
+#define TCDT1_T11 tcdt1.bit._T11\r
+#define TCDT1_T10 tcdt1.bit._T10\r
+#define TCDT1_T9 tcdt1.bit._T9\r
+#define TCDT1_T8 tcdt1.bit._T8\r
+#define TCDT1_T7 tcdt1.bit._T7\r
+#define TCDT1_T6 tcdt1.bit._T6\r
+#define TCDT1_T5 tcdt1.bit._T5\r
+#define TCDT1_T4 tcdt1.bit._T4\r
+#define TCDT1_T3 tcdt1.bit._T3\r
+#define TCDT1_T2 tcdt1.bit._T2\r
+#define TCDT1_T1 tcdt1.bit._T1\r
+#define TCDT1_T0 tcdt1.bit._T0\r
+__IO_EXTERN TCCS1STR tccs1; \r
+#define TCCS1 tccs1.byte\r
+#define TCCS1_ECLK tccs1.bit._ECLK\r
+#define TCCS1_IVF tccs1.bit._IVF\r
+#define TCCS1_IVFE tccs1.bit._IVFE\r
+#define TCCS1_STOP tccs1.bit._STOP\r
+#define TCCS1_MODE tccs1.bit._MODE\r
+#define TCCS1_CLR tccs1.bit._CLR\r
+#define TCCS1_CLK1 tccs1.bit._CLK1\r
+#define TCCS1_CLK0 tccs1.bit._CLK0\r
+#define TCCS1_CLK tccs1.bitc._CLK\r
+__IO_EXTERN TCDT2STR tcdt2; /* Free Running Timer2 */\r
+#define TCDT2 tcdt2.word\r
+#define TCDT2_T15 tcdt2.bit._T15\r
+#define TCDT2_T14 tcdt2.bit._T14\r
+#define TCDT2_T13 tcdt2.bit._T13\r
+#define TCDT2_T12 tcdt2.bit._T12\r
+#define TCDT2_T11 tcdt2.bit._T11\r
+#define TCDT2_T10 tcdt2.bit._T10\r
+#define TCDT2_T9 tcdt2.bit._T9\r
+#define TCDT2_T8 tcdt2.bit._T8\r
+#define TCDT2_T7 tcdt2.bit._T7\r
+#define TCDT2_T6 tcdt2.bit._T6\r
+#define TCDT2_T5 tcdt2.bit._T5\r
+#define TCDT2_T4 tcdt2.bit._T4\r
+#define TCDT2_T3 tcdt2.bit._T3\r
+#define TCDT2_T2 tcdt2.bit._T2\r
+#define TCDT2_T1 tcdt2.bit._T1\r
+#define TCDT2_T0 tcdt2.bit._T0\r
+__IO_EXTERN TCCS2STR tccs2; \r
+#define TCCS2 tccs2.byte\r
+#define TCCS2_ECLK tccs2.bit._ECLK\r
+#define TCCS2_IVF tccs2.bit._IVF\r
+#define TCCS2_IVFE tccs2.bit._IVFE\r
+#define TCCS2_STOP tccs2.bit._STOP\r
+#define TCCS2_MODE tccs2.bit._MODE\r
+#define TCCS2_CLR tccs2.bit._CLR\r
+#define TCCS2_CLK1 tccs2.bit._CLK1\r
+#define TCCS2_CLK0 tccs2.bit._CLK0\r
+#define TCCS2_CLK tccs2.bitc._CLK\r
+__IO_EXTERN TCDT3STR tcdt3; /* Free Running Timer3 */\r
+#define TCDT3 tcdt3.word\r
+#define TCDT3_T15 tcdt3.bit._T15\r
+#define TCDT3_T14 tcdt3.bit._T14\r
+#define TCDT3_T13 tcdt3.bit._T13\r
+#define TCDT3_T12 tcdt3.bit._T12\r
+#define TCDT3_T11 tcdt3.bit._T11\r
+#define TCDT3_T10 tcdt3.bit._T10\r
+#define TCDT3_T9 tcdt3.bit._T9\r
+#define TCDT3_T8 tcdt3.bit._T8\r
+#define TCDT3_T7 tcdt3.bit._T7\r
+#define TCDT3_T6 tcdt3.bit._T6\r
+#define TCDT3_T5 tcdt3.bit._T5\r
+#define TCDT3_T4 tcdt3.bit._T4\r
+#define TCDT3_T3 tcdt3.bit._T3\r
+#define TCDT3_T2 tcdt3.bit._T2\r
+#define TCDT3_T1 tcdt3.bit._T1\r
+#define TCDT3_T0 tcdt3.bit._T0\r
+__IO_EXTERN TCCS3STR tccs3; \r
+#define TCCS3 tccs3.byte\r
+#define TCCS3_ECLK tccs3.bit._ECLK\r
+#define TCCS3_IVF tccs3.bit._IVF\r
+#define TCCS3_IVFE tccs3.bit._IVFE\r
+#define TCCS3_STOP tccs3.bit._STOP\r
+#define TCCS3_MODE tccs3.bit._MODE\r
+#define TCCS3_CLR tccs3.bit._CLR\r
+#define TCCS3_CLK1 tccs3.bit._CLK1\r
+#define TCCS3_CLK0 tccs3.bit._CLK0\r
+#define TCCS3_CLK tccs3.bitc._CLK\r
+__IO_EXTERN DMACA0STR dmaca0; /* DMAC */\r
+#define DMACA0 dmaca0.lword\r
+#define DMACA0_DENB dmaca0.bit._DENB\r
+#define DMACA0_PAUS dmaca0.bit._PAUS\r
+#define DMACA0_STRG dmaca0.bit._STRG\r
+#define DMACA0_IS4 dmaca0.bit._IS4\r
+#define DMACA0_IS3 dmaca0.bit._IS3\r
+#define DMACA0_IS2 dmaca0.bit._IS2\r
+#define DMACA0_IS1 dmaca0.bit._IS1\r
+#define DMACA0_IS0 dmaca0.bit._IS0\r
+#define DMACA0_EIS3 dmaca0.bit._EIS3\r
+#define DMACA0_EIS2 dmaca0.bit._EIS2\r
+#define DMACA0_EIS1 dmaca0.bit._EIS1\r
+#define DMACA0_EIS0 dmaca0.bit._EIS0\r
+#define DMACA0_BLK3 dmaca0.bit._BLK3\r
+#define DMACA0_BLK2 dmaca0.bit._BLK2\r
+#define DMACA0_BLK1 dmaca0.bit._BLK1\r
+#define DMACA0_BLK0 dmaca0.bit._BLK0\r
+#define DMACA0_DTCF dmaca0.bit._DTCF\r
+#define DMACA0_DTCE dmaca0.bit._DTCE\r
+#define DMACA0_DTCD dmaca0.bit._DTCD\r
+#define DMACA0_DTCC dmaca0.bit._DTCC\r
+#define DMACA0_DTCB dmaca0.bit._DTCB\r
+#define DMACA0_DTCA dmaca0.bit._DTCA\r
+#define DMACA0_DTC9 dmaca0.bit._DTC9\r
+#define DMACA0_DTC8 dmaca0.bit._DTC8\r
+#define DMACA0_DTC7 dmaca0.bit._DTC7\r
+#define DMACA0_DTC6 dmaca0.bit._DTC6\r
+#define DMACA0_DTC5 dmaca0.bit._DTC5\r
+#define DMACA0_DTC4 dmaca0.bit._DTC4\r
+#define DMACA0_DTC3 dmaca0.bit._DTC3\r
+#define DMACA0_DTC2 dmaca0.bit._DTC2\r
+#define DMACA0_DTC1 dmaca0.bit._DTC1\r
+#define DMACA0_DTC0 dmaca0.bit._DTC0\r
+#define DMACA0_IS dmaca0.bitc._IS\r
+#define DMACA0_EIS dmaca0.bitc._EIS\r
+#define DMACA0_BLK dmaca0.bitc._BLK\r
+#define DMACA0_DTC dmaca0.bitc._DTC\r
+__IO_EXTERN DMACB0STR dmacb0; \r
+#define DMACB0 dmacb0.lword\r
+#define DMACB0_TYPE1 dmacb0.bit._TYPE1\r
+#define DMACB0_TYPE0 dmacb0.bit._TYPE0\r
+#define DMACB0_MOD1 dmacb0.bit._MOD1\r
+#define DMACB0_MOD0 dmacb0.bit._MOD0\r
+#define DMACB0_WS1 dmacb0.bit._WS1\r
+#define DMACB0_WS0 dmacb0.bit._WS0\r
+#define DMACB0_SADM dmacb0.bit._SADM\r
+#define DMACB0_DADM dmacb0.bit._DADM\r
+#define DMACB0_DTCR dmacb0.bit._DTCR\r
+#define DMACB0_SADR dmacb0.bit._SADR\r
+#define DMACB0_DADR dmacb0.bit._DADR\r
+#define DMACB0_ERIE dmacb0.bit._ERIE\r
+#define DMACB0_EDIE dmacb0.bit._EDIE\r
+#define DMACB0_DSS2 dmacb0.bit._DSS2\r
+#define DMACB0_DSS1 dmacb0.bit._DSS1\r
+#define DMACB0_DSS0 dmacb0.bit._DSS0\r
+#define DMACB0_SASZ7 dmacb0.bit._SASZ7\r
+#define DMACB0_SASZ6 dmacb0.bit._SASZ6\r
+#define DMACB0_SASZ5 dmacb0.bit._SASZ5\r
+#define DMACB0_SASZ4 dmacb0.bit._SASZ4\r
+#define DMACB0_SASZ3 dmacb0.bit._SASZ3\r
+#define DMACB0_SASZ2 dmacb0.bit._SASZ2\r
+#define DMACB0_SASZ1 dmacb0.bit._SASZ1\r
+#define DMACB0_SASZ0 dmacb0.bit._SASZ0\r
+#define DMACB0_DASZ7 dmacb0.bit._DASZ7\r
+#define DMACB0_DASZ6 dmacb0.bit._DASZ6\r
+#define DMACB0_DASZ5 dmacb0.bit._DASZ5\r
+#define DMACB0_DASZ4 dmacb0.bit._DASZ4\r
+#define DMACB0_DASZ3 dmacb0.bit._DASZ3\r
+#define DMACB0_DASZ2 dmacb0.bit._DASZ2\r
+#define DMACB0_DASZ1 dmacb0.bit._DASZ1\r
+#define DMACB0_DASZ0 dmacb0.bit._DASZ0\r
+#define DMACB0_TYPE dmacb0.bitc._TYPE\r
+#define DMACB0_MOD dmacb0.bitc._MOD\r
+#define DMACB0_WS dmacb0.bitc._WS\r
+#define DMACB0_DSS dmacb0.bitc._DSS\r
+#define DMACB0_SASZ dmacb0.bitc._SASZ\r
+#define DMACB0_DASZ dmacb0.bitc._DASZ\r
+__IO_EXTERN DMACA1STR dmaca1; \r
+#define DMACA1 dmaca1.lword\r
+#define DMACA1_DENB dmaca1.bit._DENB\r
+#define DMACA1_PAUS dmaca1.bit._PAUS\r
+#define DMACA1_STRG dmaca1.bit._STRG\r
+#define DMACA1_IS4 dmaca1.bit._IS4\r
+#define DMACA1_IS3 dmaca1.bit._IS3\r
+#define DMACA1_IS2 dmaca1.bit._IS2\r
+#define DMACA1_IS1 dmaca1.bit._IS1\r
+#define DMACA1_IS0 dmaca1.bit._IS0\r
+#define DMACA1_EIS3 dmaca1.bit._EIS3\r
+#define DMACA1_EIS2 dmaca1.bit._EIS2\r
+#define DMACA1_EIS1 dmaca1.bit._EIS1\r
+#define DMACA1_EIS0 dmaca1.bit._EIS0\r
+#define DMACA1_BLK3 dmaca1.bit._BLK3\r
+#define DMACA1_BLK2 dmaca1.bit._BLK2\r
+#define DMACA1_BLK1 dmaca1.bit._BLK1\r
+#define DMACA1_BLK0 dmaca1.bit._BLK0\r
+#define DMACA1_DTCF dmaca1.bit._DTCF\r
+#define DMACA1_DTCE dmaca1.bit._DTCE\r
+#define DMACA1_DTCD dmaca1.bit._DTCD\r
+#define DMACA1_DTCC dmaca1.bit._DTCC\r
+#define DMACA1_DTCB dmaca1.bit._DTCB\r
+#define DMACA1_DTCA dmaca1.bit._DTCA\r
+#define DMACA1_DTC9 dmaca1.bit._DTC9\r
+#define DMACA1_DTC8 dmaca1.bit._DTC8\r
+#define DMACA1_DTC7 dmaca1.bit._DTC7\r
+#define DMACA1_DTC6 dmaca1.bit._DTC6\r
+#define DMACA1_DTC5 dmaca1.bit._DTC5\r
+#define DMACA1_DTC4 dmaca1.bit._DTC4\r
+#define DMACA1_DTC3 dmaca1.bit._DTC3\r
+#define DMACA1_DTC2 dmaca1.bit._DTC2\r
+#define DMACA1_DTC1 dmaca1.bit._DTC1\r
+#define DMACA1_DTC0 dmaca1.bit._DTC0\r
+#define DMACA1_IS dmaca1.bitc._IS\r
+#define DMACA1_EIS dmaca1.bitc._EIS\r
+#define DMACA1_BLK dmaca1.bitc._BLK\r
+#define DMACA1_DTC dmaca1.bitc._DTC\r
+__IO_EXTERN DMACB1STR dmacb1; \r
+#define DMACB1 dmacb1.lword\r
+#define DMACB1_TYPE1 dmacb1.bit._TYPE1\r
+#define DMACB1_TYPE0 dmacb1.bit._TYPE0\r
+#define DMACB1_MOD1 dmacb1.bit._MOD1\r
+#define DMACB1_MOD0 dmacb1.bit._MOD0\r
+#define DMACB1_WS1 dmacb1.bit._WS1\r
+#define DMACB1_WS0 dmacb1.bit._WS0\r
+#define DMACB1_SADM dmacb1.bit._SADM\r
+#define DMACB1_DADM dmacb1.bit._DADM\r
+#define DMACB1_DTCR dmacb1.bit._DTCR\r
+#define DMACB1_SADR dmacb1.bit._SADR\r
+#define DMACB1_DADR dmacb1.bit._DADR\r
+#define DMACB1_ERIE dmacb1.bit._ERIE\r
+#define DMACB1_EDIE dmacb1.bit._EDIE\r
+#define DMACB1_DSS2 dmacb1.bit._DSS2\r
+#define DMACB1_DSS1 dmacb1.bit._DSS1\r
+#define DMACB1_DSS0 dmacb1.bit._DSS0\r
+#define DMACB1_SASZ7 dmacb1.bit._SASZ7\r
+#define DMACB1_SASZ6 dmacb1.bit._SASZ6\r
+#define DMACB1_SASZ5 dmacb1.bit._SASZ5\r
+#define DMACB1_SASZ4 dmacb1.bit._SASZ4\r
+#define DMACB1_SASZ3 dmacb1.bit._SASZ3\r
+#define DMACB1_SASZ2 dmacb1.bit._SASZ2\r
+#define DMACB1_SASZ1 dmacb1.bit._SASZ1\r
+#define DMACB1_SASZ0 dmacb1.bit._SASZ0\r
+#define DMACB1_DASZ7 dmacb1.bit._DASZ7\r
+#define DMACB1_DASZ6 dmacb1.bit._DASZ6\r
+#define DMACB1_DASZ5 dmacb1.bit._DASZ5\r
+#define DMACB1_DASZ4 dmacb1.bit._DASZ4\r
+#define DMACB1_DASZ3 dmacb1.bit._DASZ3\r
+#define DMACB1_DASZ2 dmacb1.bit._DASZ2\r
+#define DMACB1_DASZ1 dmacb1.bit._DASZ1\r
+#define DMACB1_DASZ0 dmacb1.bit._DASZ0\r
+#define DMACB1_TYPE dmacb1.bitc._TYPE\r
+#define DMACB1_MOD dmacb1.bitc._MOD\r
+#define DMACB1_WS dmacb1.bitc._WS\r
+#define DMACB1_DSS dmacb1.bitc._DSS\r
+#define DMACB1_SASZ dmacb1.bitc._SASZ\r
+#define DMACB1_DASZ dmacb1.bitc._DASZ\r
+__IO_EXTERN DMACA2STR dmaca2; \r
+#define DMACA2 dmaca2.lword\r
+#define DMACA2_DENB dmaca2.bit._DENB\r
+#define DMACA2_PAUS dmaca2.bit._PAUS\r
+#define DMACA2_STRG dmaca2.bit._STRG\r
+#define DMACA2_IS4 dmaca2.bit._IS4\r
+#define DMACA2_IS3 dmaca2.bit._IS3\r
+#define DMACA2_IS2 dmaca2.bit._IS2\r
+#define DMACA2_IS1 dmaca2.bit._IS1\r
+#define DMACA2_IS0 dmaca2.bit._IS0\r
+#define DMACA2_EIS3 dmaca2.bit._EIS3\r
+#define DMACA2_EIS2 dmaca2.bit._EIS2\r
+#define DMACA2_EIS1 dmaca2.bit._EIS1\r
+#define DMACA2_EIS0 dmaca2.bit._EIS0\r
+#define DMACA2_BLK3 dmaca2.bit._BLK3\r
+#define DMACA2_BLK2 dmaca2.bit._BLK2\r
+#define DMACA2_BLK1 dmaca2.bit._BLK1\r
+#define DMACA2_BLK0 dmaca2.bit._BLK0\r
+#define DMACA2_DTCF dmaca2.bit._DTCF\r
+#define DMACA2_DTCE dmaca2.bit._DTCE\r
+#define DMACA2_DTCD dmaca2.bit._DTCD\r
+#define DMACA2_DTCC dmaca2.bit._DTCC\r
+#define DMACA2_DTCB dmaca2.bit._DTCB\r
+#define DMACA2_DTCA dmaca2.bit._DTCA\r
+#define DMACA2_DTC9 dmaca2.bit._DTC9\r
+#define DMACA2_DTC8 dmaca2.bit._DTC8\r
+#define DMACA2_DTC7 dmaca2.bit._DTC7\r
+#define DMACA2_DTC6 dmaca2.bit._DTC6\r
+#define DMACA2_DTC5 dmaca2.bit._DTC5\r
+#define DMACA2_DTC4 dmaca2.bit._DTC4\r
+#define DMACA2_DTC3 dmaca2.bit._DTC3\r
+#define DMACA2_DTC2 dmaca2.bit._DTC2\r
+#define DMACA2_DTC1 dmaca2.bit._DTC1\r
+#define DMACA2_DTC0 dmaca2.bit._DTC0\r
+#define DMACA2_IS dmaca2.bitc._IS\r
+#define DMACA2_EIS dmaca2.bitc._EIS\r
+#define DMACA2_BLK dmaca2.bitc._BLK\r
+#define DMACA2_DTC dmaca2.bitc._DTC\r
+__IO_EXTERN DMACB2STR dmacb2; \r
+#define DMACB2 dmacb2.lword\r
+#define DMACB2_TYPE1 dmacb2.bit._TYPE1\r
+#define DMACB2_TYPE0 dmacb2.bit._TYPE0\r
+#define DMACB2_MOD1 dmacb2.bit._MOD1\r
+#define DMACB2_MOD0 dmacb2.bit._MOD0\r
+#define DMACB2_WS1 dmacb2.bit._WS1\r
+#define DMACB2_WS0 dmacb2.bit._WS0\r
+#define DMACB2_SADM dmacb2.bit._SADM\r
+#define DMACB2_DADM dmacb2.bit._DADM\r
+#define DMACB2_DTCR dmacb2.bit._DTCR\r
+#define DMACB2_SADR dmacb2.bit._SADR\r
+#define DMACB2_DADR dmacb2.bit._DADR\r
+#define DMACB2_ERIE dmacb2.bit._ERIE\r
+#define DMACB2_EDIE dmacb2.bit._EDIE\r
+#define DMACB2_DSS2 dmacb2.bit._DSS2\r
+#define DMACB2_DSS1 dmacb2.bit._DSS1\r
+#define DMACB2_DSS0 dmacb2.bit._DSS0\r
+#define DMACB2_SASZ7 dmacb2.bit._SASZ7\r
+#define DMACB2_SASZ6 dmacb2.bit._SASZ6\r
+#define DMACB2_SASZ5 dmacb2.bit._SASZ5\r
+#define DMACB2_SASZ4 dmacb2.bit._SASZ4\r
+#define DMACB2_SASZ3 dmacb2.bit._SASZ3\r
+#define DMACB2_SASZ2 dmacb2.bit._SASZ2\r
+#define DMACB2_SASZ1 dmacb2.bit._SASZ1\r
+#define DMACB2_SASZ0 dmacb2.bit._SASZ0\r
+#define DMACB2_DASZ7 dmacb2.bit._DASZ7\r
+#define DMACB2_DASZ6 dmacb2.bit._DASZ6\r
+#define DMACB2_DASZ5 dmacb2.bit._DASZ5\r
+#define DMACB2_DASZ4 dmacb2.bit._DASZ4\r
+#define DMACB2_DASZ3 dmacb2.bit._DASZ3\r
+#define DMACB2_DASZ2 dmacb2.bit._DASZ2\r
+#define DMACB2_DASZ1 dmacb2.bit._DASZ1\r
+#define DMACB2_DASZ0 dmacb2.bit._DASZ0\r
+#define DMACB2_TYPE dmacb2.bitc._TYPE\r
+#define DMACB2_MOD dmacb2.bitc._MOD\r
+#define DMACB2_WS dmacb2.bitc._WS\r
+#define DMACB2_DSS dmacb2.bitc._DSS\r
+#define DMACB2_SASZ dmacb2.bitc._SASZ\r
+#define DMACB2_DASZ dmacb2.bitc._DASZ\r
+__IO_EXTERN DMACA3STR dmaca3; \r
+#define DMACA3 dmaca3.lword\r
+#define DMACA3_DENB dmaca3.bit._DENB\r
+#define DMACA3_PAUS dmaca3.bit._PAUS\r
+#define DMACA3_STRG dmaca3.bit._STRG\r
+#define DMACA3_IS4 dmaca3.bit._IS4\r
+#define DMACA3_IS3 dmaca3.bit._IS3\r
+#define DMACA3_IS2 dmaca3.bit._IS2\r
+#define DMACA3_IS1 dmaca3.bit._IS1\r
+#define DMACA3_IS0 dmaca3.bit._IS0\r
+#define DMACA3_EIS3 dmaca3.bit._EIS3\r
+#define DMACA3_EIS2 dmaca3.bit._EIS2\r
+#define DMACA3_EIS1 dmaca3.bit._EIS1\r
+#define DMACA3_EIS0 dmaca3.bit._EIS0\r
+#define DMACA3_BLK3 dmaca3.bit._BLK3\r
+#define DMACA3_BLK2 dmaca3.bit._BLK2\r
+#define DMACA3_BLK1 dmaca3.bit._BLK1\r
+#define DMACA3_BLK0 dmaca3.bit._BLK0\r
+#define DMACA3_DTCF dmaca3.bit._DTCF\r
+#define DMACA3_DTCE dmaca3.bit._DTCE\r
+#define DMACA3_DTCD dmaca3.bit._DTCD\r
+#define DMACA3_DTCC dmaca3.bit._DTCC\r
+#define DMACA3_DTCB dmaca3.bit._DTCB\r
+#define DMACA3_DTCA dmaca3.bit._DTCA\r
+#define DMACA3_DTC9 dmaca3.bit._DTC9\r
+#define DMACA3_DTC8 dmaca3.bit._DTC8\r
+#define DMACA3_DTC7 dmaca3.bit._DTC7\r
+#define DMACA3_DTC6 dmaca3.bit._DTC6\r
+#define DMACA3_DTC5 dmaca3.bit._DTC5\r
+#define DMACA3_DTC4 dmaca3.bit._DTC4\r
+#define DMACA3_DTC3 dmaca3.bit._DTC3\r
+#define DMACA3_DTC2 dmaca3.bit._DTC2\r
+#define DMACA3_DTC1 dmaca3.bit._DTC1\r
+#define DMACA3_DTC0 dmaca3.bit._DTC0\r
+#define DMACA3_IS dmaca3.bitc._IS\r
+#define DMACA3_EIS dmaca3.bitc._EIS\r
+#define DMACA3_BLK dmaca3.bitc._BLK\r
+#define DMACA3_DTC dmaca3.bitc._DTC\r
+__IO_EXTERN DMACB3STR dmacb3; \r
+#define DMACB3 dmacb3.lword\r
+#define DMACB3_TYPE1 dmacb3.bit._TYPE1\r
+#define DMACB3_TYPE0 dmacb3.bit._TYPE0\r
+#define DMACB3_MOD1 dmacb3.bit._MOD1\r
+#define DMACB3_MOD0 dmacb3.bit._MOD0\r
+#define DMACB3_WS1 dmacb3.bit._WS1\r
+#define DMACB3_WS0 dmacb3.bit._WS0\r
+#define DMACB3_SADM dmacb3.bit._SADM\r
+#define DMACB3_DADM dmacb3.bit._DADM\r
+#define DMACB3_DTCR dmacb3.bit._DTCR\r
+#define DMACB3_SADR dmacb3.bit._SADR\r
+#define DMACB3_DADR dmacb3.bit._DADR\r
+#define DMACB3_ERIE dmacb3.bit._ERIE\r
+#define DMACB3_EDIE dmacb3.bit._EDIE\r
+#define DMACB3_DSS2 dmacb3.bit._DSS2\r
+#define DMACB3_DSS1 dmacb3.bit._DSS1\r
+#define DMACB3_DSS0 dmacb3.bit._DSS0\r
+#define DMACB3_SASZ7 dmacb3.bit._SASZ7\r
+#define DMACB3_SASZ6 dmacb3.bit._SASZ6\r
+#define DMACB3_SASZ5 dmacb3.bit._SASZ5\r
+#define DMACB3_SASZ4 dmacb3.bit._SASZ4\r
+#define DMACB3_SASZ3 dmacb3.bit._SASZ3\r
+#define DMACB3_SASZ2 dmacb3.bit._SASZ2\r
+#define DMACB3_SASZ1 dmacb3.bit._SASZ1\r
+#define DMACB3_SASZ0 dmacb3.bit._SASZ0\r
+#define DMACB3_DASZ7 dmacb3.bit._DASZ7\r
+#define DMACB3_DASZ6 dmacb3.bit._DASZ6\r
+#define DMACB3_DASZ5 dmacb3.bit._DASZ5\r
+#define DMACB3_DASZ4 dmacb3.bit._DASZ4\r
+#define DMACB3_DASZ3 dmacb3.bit._DASZ3\r
+#define DMACB3_DASZ2 dmacb3.bit._DASZ2\r
+#define DMACB3_DASZ1 dmacb3.bit._DASZ1\r
+#define DMACB3_DASZ0 dmacb3.bit._DASZ0\r
+#define DMACB3_TYPE dmacb3.bitc._TYPE\r
+#define DMACB3_MOD dmacb3.bitc._MOD\r
+#define DMACB3_WS dmacb3.bitc._WS\r
+#define DMACB3_DSS dmacb3.bitc._DSS\r
+#define DMACB3_SASZ dmacb3.bitc._SASZ\r
+#define DMACB3_DASZ dmacb3.bitc._DASZ\r
+__IO_EXTERN DMACA4STR dmaca4; \r
+#define DMACA4 dmaca4.lword\r
+#define DMACA4_DENB dmaca4.bit._DENB\r
+#define DMACA4_PAUS dmaca4.bit._PAUS\r
+#define DMACA4_STRG dmaca4.bit._STRG\r
+#define DMACA4_IS4 dmaca4.bit._IS4\r
+#define DMACA4_IS3 dmaca4.bit._IS3\r
+#define DMACA4_IS2 dmaca4.bit._IS2\r
+#define DMACA4_IS1 dmaca4.bit._IS1\r
+#define DMACA4_IS0 dmaca4.bit._IS0\r
+#define DMACA4_EIS3 dmaca4.bit._EIS3\r
+#define DMACA4_EIS2 dmaca4.bit._EIS2\r
+#define DMACA4_EIS1 dmaca4.bit._EIS1\r
+#define DMACA4_EIS0 dmaca4.bit._EIS0\r
+#define DMACA4_BLK3 dmaca4.bit._BLK3\r
+#define DMACA4_BLK2 dmaca4.bit._BLK2\r
+#define DMACA4_BLK1 dmaca4.bit._BLK1\r
+#define DMACA4_BLK0 dmaca4.bit._BLK0\r
+#define DMACA4_DTCF dmaca4.bit._DTCF\r
+#define DMACA4_DTCE dmaca4.bit._DTCE\r
+#define DMACA4_DTCD dmaca4.bit._DTCD\r
+#define DMACA4_DTCC dmaca4.bit._DTCC\r
+#define DMACA4_DTCB dmaca4.bit._DTCB\r
+#define DMACA4_DTCA dmaca4.bit._DTCA\r
+#define DMACA4_DTC9 dmaca4.bit._DTC9\r
+#define DMACA4_DTC8 dmaca4.bit._DTC8\r
+#define DMACA4_DTC7 dmaca4.bit._DTC7\r
+#define DMACA4_DTC6 dmaca4.bit._DTC6\r
+#define DMACA4_DTC5 dmaca4.bit._DTC5\r
+#define DMACA4_DTC4 dmaca4.bit._DTC4\r
+#define DMACA4_DTC3 dmaca4.bit._DTC3\r
+#define DMACA4_DTC2 dmaca4.bit._DTC2\r
+#define DMACA4_DTC1 dmaca4.bit._DTC1\r
+#define DMACA4_DTC0 dmaca4.bit._DTC0\r
+#define DMACA4_IS dmaca4.bitc._IS\r
+#define DMACA4_EIS dmaca4.bitc._EIS\r
+#define DMACA4_BLK dmaca4.bitc._BLK\r
+#define DMACA4_DTC dmaca4.bitc._DTC\r
+__IO_EXTERN DMACB4STR dmacb4; \r
+#define DMACB4 dmacb4.lword\r
+#define DMACB4_TYPE1 dmacb4.bit._TYPE1\r
+#define DMACB4_TYPE0 dmacb4.bit._TYPE0\r
+#define DMACB4_MOD1 dmacb4.bit._MOD1\r
+#define DMACB4_MOD0 dmacb4.bit._MOD0\r
+#define DMACB4_WS1 dmacb4.bit._WS1\r
+#define DMACB4_WS0 dmacb4.bit._WS0\r
+#define DMACB4_SADM dmacb4.bit._SADM\r
+#define DMACB4_DADM dmacb4.bit._DADM\r
+#define DMACB4_DTCR dmacb4.bit._DTCR\r
+#define DMACB4_SADR dmacb4.bit._SADR\r
+#define DMACB4_DADR dmacb4.bit._DADR\r
+#define DMACB4_ERIE dmacb4.bit._ERIE\r
+#define DMACB4_EDIE dmacb4.bit._EDIE\r
+#define DMACB4_DSS2 dmacb4.bit._DSS2\r
+#define DMACB4_DSS1 dmacb4.bit._DSS1\r
+#define DMACB4_DSS0 dmacb4.bit._DSS0\r
+#define DMACB4_SASZ7 dmacb4.bit._SASZ7\r
+#define DMACB4_SASZ6 dmacb4.bit._SASZ6\r
+#define DMACB4_SASZ5 dmacb4.bit._SASZ5\r
+#define DMACB4_SASZ4 dmacb4.bit._SASZ4\r
+#define DMACB4_SASZ3 dmacb4.bit._SASZ3\r
+#define DMACB4_SASZ2 dmacb4.bit._SASZ2\r
+#define DMACB4_SASZ1 dmacb4.bit._SASZ1\r
+#define DMACB4_SASZ0 dmacb4.bit._SASZ0\r
+#define DMACB4_DASZ7 dmacb4.bit._DASZ7\r
+#define DMACB4_DASZ6 dmacb4.bit._DASZ6\r
+#define DMACB4_DASZ5 dmacb4.bit._DASZ5\r
+#define DMACB4_DASZ4 dmacb4.bit._DASZ4\r
+#define DMACB4_DASZ3 dmacb4.bit._DASZ3\r
+#define DMACB4_DASZ2 dmacb4.bit._DASZ2\r
+#define DMACB4_DASZ1 dmacb4.bit._DASZ1\r
+#define DMACB4_DASZ0 dmacb4.bit._DASZ0\r
+#define DMACB4_TYPE dmacb4.bitc._TYPE\r
+#define DMACB4_MOD dmacb4.bitc._MOD\r
+#define DMACB4_WS dmacb4.bitc._WS\r
+#define DMACB4_DSS dmacb4.bitc._DSS\r
+#define DMACB4_SASZ dmacb4.bitc._SASZ\r
+#define DMACB4_DASZ dmacb4.bitc._DASZ\r
+__IO_EXTERN DMACRSTR dmacr; \r
+#define DMACR dmacr.byte\r
+#define DMACR_DMAE dmacr.bit._DMAE\r
+#define DMACR_PM01 dmacr.bit._PM01\r
+#define DMACR_DMAH3 dmacr.bit._DMAH3\r
+#define DMACR_DMAH2 dmacr.bit._DMAH2\r
+#define DMACR_DMAH1 dmacr.bit._DMAH1\r
+#define DMACR_DMAH0 dmacr.bit._DMAH0\r
+#define DMACR_DMAH dmacr.bitc._DMAH\r
+__IO_EXTERN ICS45STR ics45; /* Input Capture 4-7 */\r
+#define ICS45 ics45.byte\r
+#define ICS45_ICP5 ics45.bit._ICP5\r
+#define ICS45_ICP4 ics45.bit._ICP4\r
+#define ICS45_ICE5 ics45.bit._ICE5\r
+#define ICS45_ICE4 ics45.bit._ICE4\r
+#define ICS45_EG51 ics45.bit._EG51\r
+#define ICS45_EG50 ics45.bit._EG50\r
+#define ICS45_EG41 ics45.bit._EG41\r
+#define ICS45_EG40 ics45.bit._EG40\r
+#define ICS45_EG5 ics45.bitc._EG5\r
+#define ICS45_EG4 ics45.bitc._EG4\r
+__IO_EXTERN ICS67STR ics67; \r
+#define ICS67 ics67.byte\r
+#define ICS67_ICP7 ics67.bit._ICP7\r
+#define ICS67_ICP6 ics67.bit._ICP6\r
+#define ICS67_ICE7 ics67.bit._ICE7\r
+#define ICS67_ICE6 ics67.bit._ICE6\r
+#define ICS67_EG71 ics67.bit._EG71\r
+#define ICS67_EG70 ics67.bit._EG70\r
+#define ICS67_EG61 ics67.bit._EG61\r
+#define ICS67_EG60 ics67.bit._EG60\r
+#define ICS67_EG7 ics67.bitc._EG7\r
+#define ICS67_EG6 ics67.bitc._EG6\r
+__IO_EXTERN IPCP4STR ipcp4; \r
+#define IPCP4 ipcp4.word\r
+#define IPCP4_CP15 ipcp4.bit._CP15\r
+#define IPCP4_CP14 ipcp4.bit._CP14\r
+#define IPCP4_CP13 ipcp4.bit._CP13\r
+#define IPCP4_CP12 ipcp4.bit._CP12\r
+#define IPCP4_CP11 ipcp4.bit._CP11\r
+#define IPCP4_CP10 ipcp4.bit._CP10\r
+#define IPCP4_CP9 ipcp4.bit._CP9\r
+#define IPCP4_CP8 ipcp4.bit._CP8\r
+#define IPCP4_CP7 ipcp4.bit._CP7\r
+#define IPCP4_CP6 ipcp4.bit._CP6\r
+#define IPCP4_CP5 ipcp4.bit._CP5\r
+#define IPCP4_CP4 ipcp4.bit._CP4\r
+#define IPCP4_CP3 ipcp4.bit._CP3\r
+#define IPCP4_CP2 ipcp4.bit._CP2\r
+#define IPCP4_CP1 ipcp4.bit._CP1\r
+#define IPCP4_CP0 ipcp4.bit._CP0\r
+__IO_EXTERN IPCP5STR ipcp5; \r
+#define IPCP5 ipcp5.word\r
+#define IPCP5_CP15 ipcp5.bit._CP15\r
+#define IPCP5_CP14 ipcp5.bit._CP14\r
+#define IPCP5_CP13 ipcp5.bit._CP13\r
+#define IPCP5_CP12 ipcp5.bit._CP12\r
+#define IPCP5_CP11 ipcp5.bit._CP11\r
+#define IPCP5_CP10 ipcp5.bit._CP10\r
+#define IPCP5_CP9 ipcp5.bit._CP9\r
+#define IPCP5_CP8 ipcp5.bit._CP8\r
+#define IPCP5_CP7 ipcp5.bit._CP7\r
+#define IPCP5_CP6 ipcp5.bit._CP6\r
+#define IPCP5_CP5 ipcp5.bit._CP5\r
+#define IPCP5_CP4 ipcp5.bit._CP4\r
+#define IPCP5_CP3 ipcp5.bit._CP3\r
+#define IPCP5_CP2 ipcp5.bit._CP2\r
+#define IPCP5_CP1 ipcp5.bit._CP1\r
+#define IPCP5_CP0 ipcp5.bit._CP0\r
+__IO_EXTERN IPCP6STR ipcp6; \r
+#define IPCP6 ipcp6.word\r
+#define IPCP6_CP15 ipcp6.bit._CP15\r
+#define IPCP6_CP14 ipcp6.bit._CP14\r
+#define IPCP6_CP13 ipcp6.bit._CP13\r
+#define IPCP6_CP12 ipcp6.bit._CP12\r
+#define IPCP6_CP11 ipcp6.bit._CP11\r
+#define IPCP6_CP10 ipcp6.bit._CP10\r
+#define IPCP6_CP9 ipcp6.bit._CP9\r
+#define IPCP6_CP8 ipcp6.bit._CP8\r
+#define IPCP6_CP7 ipcp6.bit._CP7\r
+#define IPCP6_CP6 ipcp6.bit._CP6\r
+#define IPCP6_CP5 ipcp6.bit._CP5\r
+#define IPCP6_CP4 ipcp6.bit._CP4\r
+#define IPCP6_CP3 ipcp6.bit._CP3\r
+#define IPCP6_CP2 ipcp6.bit._CP2\r
+#define IPCP6_CP1 ipcp6.bit._CP1\r
+#define IPCP6_CP0 ipcp6.bit._CP0\r
+__IO_EXTERN IPCP7STR ipcp7; \r
+#define IPCP7 ipcp7.word\r
+#define IPCP7_CP15 ipcp7.bit._CP15\r
+#define IPCP7_CP14 ipcp7.bit._CP14\r
+#define IPCP7_CP13 ipcp7.bit._CP13\r
+#define IPCP7_CP12 ipcp7.bit._CP12\r
+#define IPCP7_CP11 ipcp7.bit._CP11\r
+#define IPCP7_CP10 ipcp7.bit._CP10\r
+#define IPCP7_CP9 ipcp7.bit._CP9\r
+#define IPCP7_CP8 ipcp7.bit._CP8\r
+#define IPCP7_CP7 ipcp7.bit._CP7\r
+#define IPCP7_CP6 ipcp7.bit._CP6\r
+#define IPCP7_CP5 ipcp7.bit._CP5\r
+#define IPCP7_CP4 ipcp7.bit._CP4\r
+#define IPCP7_CP3 ipcp7.bit._CP3\r
+#define IPCP7_CP2 ipcp7.bit._CP2\r
+#define IPCP7_CP1 ipcp7.bit._CP1\r
+#define IPCP7_CP0 ipcp7.bit._CP0\r
+__IO_EXTERN OCS45STR ocs45; /* Output Compare 4-7 */\r
+#define OCS45 ocs45.word\r
+#define OCS45_CMOD ocs45.bit._CMOD\r
+#define OCS45_OTD5 ocs45.bit._OTD5\r
+#define OCS45_OTD4 ocs45.bit._OTD4\r
+#define OCS45_ICP5 ocs45.bit._ICP5\r
+#define OCS45_ICP4 ocs45.bit._ICP4\r
+#define OCS45_ICE5 ocs45.bit._ICE5\r
+#define OCS45_ICE4 ocs45.bit._ICE4\r
+#define OCS45_CST5 ocs45.bit._CST5\r
+#define OCS45_CST4 ocs45.bit._CST4\r
+__IO_EXTERN OCS67STR ocs67; \r
+#define OCS67 ocs67.word\r
+#define OCS67_CMOD ocs67.bit._CMOD\r
+#define OCS67_OTD7 ocs67.bit._OTD7\r
+#define OCS67_OTD6 ocs67.bit._OTD6\r
+#define OCS67_ICP7 ocs67.bit._ICP7\r
+#define OCS67_ICP6 ocs67.bit._ICP6\r
+#define OCS67_ICE7 ocs67.bit._ICE7\r
+#define OCS67_ICE6 ocs67.bit._ICE6\r
+#define OCS67_CST7 ocs67.bit._CST7\r
+#define OCS67_CST6 ocs67.bit._CST6\r
+__IO_EXTERN OCCP4STR occp4; \r
+#define OCCP4 occp4.word\r
+#define OCCP4_C15 occp4.bit._C15\r
+#define OCCP4_C14 occp4.bit._C14\r
+#define OCCP4_C13 occp4.bit._C13\r
+#define OCCP4_C12 occp4.bit._C12\r
+#define OCCP4_C11 occp4.bit._C11\r
+#define OCCP4_C10 occp4.bit._C10\r
+#define OCCP4_C9 occp4.bit._C9\r
+#define OCCP4_C8 occp4.bit._C8\r
+#define OCCP4_C7 occp4.bit._C7\r
+#define OCCP4_C6 occp4.bit._C6\r
+#define OCCP4_C5 occp4.bit._C5\r
+#define OCCP4_C4 occp4.bit._C4\r
+#define OCCP4_C3 occp4.bit._C3\r
+#define OCCP4_C2 occp4.bit._C2\r
+#define OCCP4_C1 occp4.bit._C1\r
+#define OCCP4_C0 occp4.bit._C0\r
+__IO_EXTERN OCCP5STR occp5; \r
+#define OCCP5 occp5.word\r
+#define OCCP5_C15 occp5.bit._C15\r
+#define OCCP5_C14 occp5.bit._C14\r
+#define OCCP5_C13 occp5.bit._C13\r
+#define OCCP5_C12 occp5.bit._C12\r
+#define OCCP5_C11 occp5.bit._C11\r
+#define OCCP5_C10 occp5.bit._C10\r
+#define OCCP5_C9 occp5.bit._C9\r
+#define OCCP5_C8 occp5.bit._C8\r
+#define OCCP5_C7 occp5.bit._C7\r
+#define OCCP5_C6 occp5.bit._C6\r
+#define OCCP5_C5 occp5.bit._C5\r
+#define OCCP5_C4 occp5.bit._C4\r
+#define OCCP5_C3 occp5.bit._C3\r
+#define OCCP5_C2 occp5.bit._C2\r
+#define OCCP5_C1 occp5.bit._C1\r
+#define OCCP5_C0 occp5.bit._C0\r
+__IO_EXTERN OCCP6STR occp6; \r
+#define OCCP6 occp6.word\r
+#define OCCP6_C15 occp6.bit._C15\r
+#define OCCP6_C14 occp6.bit._C14\r
+#define OCCP6_C13 occp6.bit._C13\r
+#define OCCP6_C12 occp6.bit._C12\r
+#define OCCP6_C11 occp6.bit._C11\r
+#define OCCP6_C10 occp6.bit._C10\r
+#define OCCP6_C9 occp6.bit._C9\r
+#define OCCP6_C8 occp6.bit._C8\r
+#define OCCP6_C7 occp6.bit._C7\r
+#define OCCP6_C6 occp6.bit._C6\r
+#define OCCP6_C5 occp6.bit._C5\r
+#define OCCP6_C4 occp6.bit._C4\r
+#define OCCP6_C3 occp6.bit._C3\r
+#define OCCP6_C2 occp6.bit._C2\r
+#define OCCP6_C1 occp6.bit._C1\r
+#define OCCP6_C0 occp6.bit._C0\r
+__IO_EXTERN OCCP7STR occp7; \r
+#define OCCP7 occp7.word\r
+#define OCCP7_C15 occp7.bit._C15\r
+#define OCCP7_C14 occp7.bit._C14\r
+#define OCCP7_C13 occp7.bit._C13\r
+#define OCCP7_C12 occp7.bit._C12\r
+#define OCCP7_C11 occp7.bit._C11\r
+#define OCCP7_C10 occp7.bit._C10\r
+#define OCCP7_C9 occp7.bit._C9\r
+#define OCCP7_C8 occp7.bit._C8\r
+#define OCCP7_C7 occp7.bit._C7\r
+#define OCCP7_C6 occp7.bit._C6\r
+#define OCCP7_C5 occp7.bit._C5\r
+#define OCCP7_C4 occp7.bit._C4\r
+#define OCCP7_C3 occp7.bit._C3\r
+#define OCCP7_C2 occp7.bit._C2\r
+#define OCCP7_C1 occp7.bit._C1\r
+#define OCCP7_C0 occp7.bit._C0\r
+__IO_EXTERN TCDT4STR tcdt4; /* Free Running Timer4 */\r
+#define TCDT4 tcdt4.word\r
+#define TCDT4_T15 tcdt4.bit._T15\r
+#define TCDT4_T14 tcdt4.bit._T14\r
+#define TCDT4_T13 tcdt4.bit._T13\r
+#define TCDT4_T12 tcdt4.bit._T12\r
+#define TCDT4_T11 tcdt4.bit._T11\r
+#define TCDT4_T10 tcdt4.bit._T10\r
+#define TCDT4_T9 tcdt4.bit._T9\r
+#define TCDT4_T8 tcdt4.bit._T8\r
+#define TCDT4_T7 tcdt4.bit._T7\r
+#define TCDT4_T6 tcdt4.bit._T6\r
+#define TCDT4_T5 tcdt4.bit._T5\r
+#define TCDT4_T4 tcdt4.bit._T4\r
+#define TCDT4_T3 tcdt4.bit._T3\r
+#define TCDT4_T2 tcdt4.bit._T2\r
+#define TCDT4_T1 tcdt4.bit._T1\r
+#define TCDT4_T0 tcdt4.bit._T0\r
+__IO_EXTERN TCCS4STR tccs4; \r
+#define TCCS4 tccs4.byte\r
+#define TCCS4_ECLK tccs4.bit._ECLK\r
+#define TCCS4_IVF tccs4.bit._IVF\r
+#define TCCS4_IVFE tccs4.bit._IVFE\r
+#define TCCS4_STOP tccs4.bit._STOP\r
+#define TCCS4_MODE tccs4.bit._MODE\r
+#define TCCS4_CLR tccs4.bit._CLR\r
+#define TCCS4_CLK1 tccs4.bit._CLK1\r
+#define TCCS4_CLK0 tccs4.bit._CLK0\r
+#define TCCS4_CLK tccs4.bitc._CLK\r
+__IO_EXTERN TCDT5STR tcdt5; /* Free Running Timer5 */\r
+#define TCDT5 tcdt5.word\r
+#define TCDT5_T15 tcdt5.bit._T15\r
+#define TCDT5_T14 tcdt5.bit._T14\r
+#define TCDT5_T13 tcdt5.bit._T13\r
+#define TCDT5_T12 tcdt5.bit._T12\r
+#define TCDT5_T11 tcdt5.bit._T11\r
+#define TCDT5_T10 tcdt5.bit._T10\r
+#define TCDT5_T9 tcdt5.bit._T9\r
+#define TCDT5_T8 tcdt5.bit._T8\r
+#define TCDT5_T7 tcdt5.bit._T7\r
+#define TCDT5_T6 tcdt5.bit._T6\r
+#define TCDT5_T5 tcdt5.bit._T5\r
+#define TCDT5_T4 tcdt5.bit._T4\r
+#define TCDT5_T3 tcdt5.bit._T3\r
+#define TCDT5_T2 tcdt5.bit._T2\r
+#define TCDT5_T1 tcdt5.bit._T1\r
+#define TCDT5_T0 tcdt5.bit._T0\r
+__IO_EXTERN TCCS5STR tccs5; \r
+#define TCCS5 tccs5.byte\r
+#define TCCS5_ECLK tccs5.bit._ECLK\r
+#define TCCS5_IVF tccs5.bit._IVF\r
+#define TCCS5_IVFE tccs5.bit._IVFE\r
+#define TCCS5_STOP tccs5.bit._STOP\r
+#define TCCS5_MODE tccs5.bit._MODE\r
+#define TCCS5_CLR tccs5.bit._CLR\r
+#define TCCS5_CLK1 tccs5.bit._CLK1\r
+#define TCCS5_CLK0 tccs5.bit._CLK0\r
+#define TCCS5_CLK tccs5.bitc._CLK\r
+__IO_EXTERN TCDT6STR tcdt6; /* Free Running Timer6 */\r
+#define TCDT6 tcdt6.word\r
+#define TCDT6_T15 tcdt6.bit._T15\r
+#define TCDT6_T14 tcdt6.bit._T14\r
+#define TCDT6_T13 tcdt6.bit._T13\r
+#define TCDT6_T12 tcdt6.bit._T12\r
+#define TCDT6_T11 tcdt6.bit._T11\r
+#define TCDT6_T10 tcdt6.bit._T10\r
+#define TCDT6_T9 tcdt6.bit._T9\r
+#define TCDT6_T8 tcdt6.bit._T8\r
+#define TCDT6_T7 tcdt6.bit._T7\r
+#define TCDT6_T6 tcdt6.bit._T6\r
+#define TCDT6_T5 tcdt6.bit._T5\r
+#define TCDT6_T4 tcdt6.bit._T4\r
+#define TCDT6_T3 tcdt6.bit._T3\r
+#define TCDT6_T2 tcdt6.bit._T2\r
+#define TCDT6_T1 tcdt6.bit._T1\r
+#define TCDT6_T0 tcdt6.bit._T0\r
+__IO_EXTERN TCCS6STR tccs6; \r
+#define TCCS6 tccs6.byte\r
+#define TCCS6_ECLK tccs6.bit._ECLK\r
+#define TCCS6_IVF tccs6.bit._IVF\r
+#define TCCS6_IVFE tccs6.bit._IVFE\r
+#define TCCS6_STOP tccs6.bit._STOP\r
+#define TCCS6_MODE tccs6.bit._MODE\r
+#define TCCS6_CLR tccs6.bit._CLR\r
+#define TCCS6_CLK1 tccs6.bit._CLK1\r
+#define TCCS6_CLK0 tccs6.bit._CLK0\r
+#define TCCS6_CLK tccs6.bitc._CLK\r
+__IO_EXTERN TCDT7STR tcdt7; /* Free Running Timer7 */\r
+#define TCDT7 tcdt7.word\r
+#define TCDT7_T15 tcdt7.bit._T15\r
+#define TCDT7_T14 tcdt7.bit._T14\r
+#define TCDT7_T13 tcdt7.bit._T13\r
+#define TCDT7_T12 tcdt7.bit._T12\r
+#define TCDT7_T11 tcdt7.bit._T11\r
+#define TCDT7_T10 tcdt7.bit._T10\r
+#define TCDT7_T9 tcdt7.bit._T9\r
+#define TCDT7_T8 tcdt7.bit._T8\r
+#define TCDT7_T7 tcdt7.bit._T7\r
+#define TCDT7_T6 tcdt7.bit._T6\r
+#define TCDT7_T5 tcdt7.bit._T5\r
+#define TCDT7_T4 tcdt7.bit._T4\r
+#define TCDT7_T3 tcdt7.bit._T3\r
+#define TCDT7_T2 tcdt7.bit._T2\r
+#define TCDT7_T1 tcdt7.bit._T1\r
+#define TCDT7_T0 tcdt7.bit._T0\r
+__IO_EXTERN TCCS7STR tccs7; \r
+#define TCCS7 tccs7.byte\r
+#define TCCS7_ECLK tccs7.bit._ECLK\r
+#define TCCS7_IVF tccs7.bit._IVF\r
+#define TCCS7_IVFE tccs7.bit._IVFE\r
+#define TCCS7_STOP tccs7.bit._STOP\r
+#define TCCS7_MODE tccs7.bit._MODE\r
+#define TCCS7_CLR tccs7.bit._CLR\r
+#define TCCS7_CLK1 tccs7.bit._CLK1\r
+#define TCCS7_CLK0 tccs7.bit._CLK0\r
+#define TCCS7_CLK tccs7.bitc._CLK\r
+__IO_EXTERN ROMSSTR roms; /* ROM Select Register */\r
+#define ROMS roms.word\r
+#define ROMS_D15 roms.bit._D15\r
+#define ROMS_D14 roms.bit._D14\r
+#define ROMS_D13 roms.bit._D13\r
+#define ROMS_D12 roms.bit._D12\r
+#define ROMS_D11 roms.bit._D11\r
+#define ROMS_D10 roms.bit._D10\r
+#define ROMS_D9 roms.bit._D9\r
+#define ROMS_D8 roms.bit._D8\r
+#define ROMS_D7 roms.bit._D7\r
+#define ROMS_D6 roms.bit._D6\r
+#define ROMS_D5 roms.bit._D5\r
+#define ROMS_D4 roms.bit._D4\r
+#define ROMS_D3 roms.bit._D3\r
+#define ROMS_D2 roms.bit._D2\r
+#define ROMS_D1 roms.bit._D1\r
+#define ROMS_D0 roms.bit._D0\r
+__IO_EXTERN IO_LWORD bsd0; /* Bit Search Module */\r
+#define BSD0 bsd0\r
+__IO_EXTERN IO_LWORD bsd1; \r
+#define BSD1 bsd1\r
+__IO_EXTERN IO_LWORD bsdc; \r
+#define BSDC bsdc\r
+__IO_EXTERN IO_LWORD bsrr; \r
+#define BSRR bsrr\r
+__IO_EXTERN ICR00STR icr00; /* Interrupt Control Unit */\r
+#define ICR00 icr00.byte\r
+#define ICR00_ICR4 icr00.bit._ICR4\r
+#define ICR00_ICR3 icr00.bit._ICR3\r
+#define ICR00_ICR2 icr00.bit._ICR2\r
+#define ICR00_ICR1 icr00.bit._ICR1\r
+#define ICR00_ICR0 icr00.bit._ICR0\r
+__IO_EXTERN ICR01STR icr01; \r
+#define ICR01 icr01.byte\r
+#define ICR01_ICR4 icr01.bit._ICR4\r
+#define ICR01_ICR3 icr01.bit._ICR3\r
+#define ICR01_ICR2 icr01.bit._ICR2\r
+#define ICR01_ICR1 icr01.bit._ICR1\r
+#define ICR01_ICR0 icr01.bit._ICR0\r
+__IO_EXTERN ICR02STR icr02; \r
+#define ICR02 icr02.byte\r
+#define ICR02_ICR4 icr02.bit._ICR4\r
+#define ICR02_ICR3 icr02.bit._ICR3\r
+#define ICR02_ICR2 icr02.bit._ICR2\r
+#define ICR02_ICR1 icr02.bit._ICR1\r
+#define ICR02_ICR0 icr02.bit._ICR0\r
+__IO_EXTERN ICR03STR icr03; \r
+#define ICR03 icr03.byte\r
+#define ICR03_ICR4 icr03.bit._ICR4\r
+#define ICR03_ICR3 icr03.bit._ICR3\r
+#define ICR03_ICR2 icr03.bit._ICR2\r
+#define ICR03_ICR1 icr03.bit._ICR1\r
+#define ICR03_ICR0 icr03.bit._ICR0\r
+__IO_EXTERN ICR04STR icr04; \r
+#define ICR04 icr04.byte\r
+#define ICR04_ICR4 icr04.bit._ICR4\r
+#define ICR04_ICR3 icr04.bit._ICR3\r
+#define ICR04_ICR2 icr04.bit._ICR2\r
+#define ICR04_ICR1 icr04.bit._ICR1\r
+#define ICR04_ICR0 icr04.bit._ICR0\r
+__IO_EXTERN ICR05STR icr05; \r
+#define ICR05 icr05.byte\r
+#define ICR05_ICR4 icr05.bit._ICR4\r
+#define ICR05_ICR3 icr05.bit._ICR3\r
+#define ICR05_ICR2 icr05.bit._ICR2\r
+#define ICR05_ICR1 icr05.bit._ICR1\r
+#define ICR05_ICR0 icr05.bit._ICR0\r
+__IO_EXTERN ICR06STR icr06; \r
+#define ICR06 icr06.byte\r
+#define ICR06_ICR4 icr06.bit._ICR4\r
+#define ICR06_ICR3 icr06.bit._ICR3\r
+#define ICR06_ICR2 icr06.bit._ICR2\r
+#define ICR06_ICR1 icr06.bit._ICR1\r
+#define ICR06_ICR0 icr06.bit._ICR0\r
+__IO_EXTERN ICR07STR icr07; \r
+#define ICR07 icr07.byte\r
+#define ICR07_ICR4 icr07.bit._ICR4\r
+#define ICR07_ICR3 icr07.bit._ICR3\r
+#define ICR07_ICR2 icr07.bit._ICR2\r
+#define ICR07_ICR1 icr07.bit._ICR1\r
+#define ICR07_ICR0 icr07.bit._ICR0\r
+__IO_EXTERN ICR08STR icr08; \r
+#define ICR08 icr08.byte\r
+#define ICR08_ICR4 icr08.bit._ICR4\r
+#define ICR08_ICR3 icr08.bit._ICR3\r
+#define ICR08_ICR2 icr08.bit._ICR2\r
+#define ICR08_ICR1 icr08.bit._ICR1\r
+#define ICR08_ICR0 icr08.bit._ICR0\r
+__IO_EXTERN ICR09STR icr09; \r
+#define ICR09 icr09.byte\r
+#define ICR09_ICR4 icr09.bit._ICR4\r
+#define ICR09_ICR3 icr09.bit._ICR3\r
+#define ICR09_ICR2 icr09.bit._ICR2\r
+#define ICR09_ICR1 icr09.bit._ICR1\r
+#define ICR09_ICR0 icr09.bit._ICR0\r
+__IO_EXTERN ICR10STR icr10; \r
+#define ICR10 icr10.byte\r
+#define ICR10_ICR4 icr10.bit._ICR4\r
+#define ICR10_ICR3 icr10.bit._ICR3\r
+#define ICR10_ICR2 icr10.bit._ICR2\r
+#define ICR10_ICR1 icr10.bit._ICR1\r
+#define ICR10_ICR0 icr10.bit._ICR0\r
+__IO_EXTERN ICR11STR icr11; \r
+#define ICR11 icr11.byte\r
+#define ICR11_ICR4 icr11.bit._ICR4\r
+#define ICR11_ICR3 icr11.bit._ICR3\r
+#define ICR11_ICR2 icr11.bit._ICR2\r
+#define ICR11_ICR1 icr11.bit._ICR1\r
+#define ICR11_ICR0 icr11.bit._ICR0\r
+__IO_EXTERN ICR12STR icr12; \r
+#define ICR12 icr12.byte\r
+#define ICR12_ICR4 icr12.bit._ICR4\r
+#define ICR12_ICR3 icr12.bit._ICR3\r
+#define ICR12_ICR2 icr12.bit._ICR2\r
+#define ICR12_ICR1 icr12.bit._ICR1\r
+#define ICR12_ICR0 icr12.bit._ICR0\r
+__IO_EXTERN ICR13STR icr13; \r
+#define ICR13 icr13.byte\r
+#define ICR13_ICR4 icr13.bit._ICR4\r
+#define ICR13_ICR3 icr13.bit._ICR3\r
+#define ICR13_ICR2 icr13.bit._ICR2\r
+#define ICR13_ICR1 icr13.bit._ICR1\r
+#define ICR13_ICR0 icr13.bit._ICR0\r
+__IO_EXTERN ICR14STR icr14; \r
+#define ICR14 icr14.byte\r
+#define ICR14_ICR4 icr14.bit._ICR4\r
+#define ICR14_ICR3 icr14.bit._ICR3\r
+#define ICR14_ICR2 icr14.bit._ICR2\r
+#define ICR14_ICR1 icr14.bit._ICR1\r
+#define ICR14_ICR0 icr14.bit._ICR0\r
+__IO_EXTERN ICR15STR icr15; \r
+#define ICR15 icr15.byte\r
+#define ICR15_ICR4 icr15.bit._ICR4\r
+#define ICR15_ICR3 icr15.bit._ICR3\r
+#define ICR15_ICR2 icr15.bit._ICR2\r
+#define ICR15_ICR1 icr15.bit._ICR1\r
+#define ICR15_ICR0 icr15.bit._ICR0\r
+__IO_EXTERN ICR16STR icr16; \r
+#define ICR16 icr16.byte\r
+#define ICR16_ICR4 icr16.bit._ICR4\r
+#define ICR16_ICR3 icr16.bit._ICR3\r
+#define ICR16_ICR2 icr16.bit._ICR2\r
+#define ICR16_ICR1 icr16.bit._ICR1\r
+#define ICR16_ICR0 icr16.bit._ICR0\r
+__IO_EXTERN ICR17STR icr17; \r
+#define ICR17 icr17.byte\r
+#define ICR17_ICR4 icr17.bit._ICR4\r
+#define ICR17_ICR3 icr17.bit._ICR3\r
+#define ICR17_ICR2 icr17.bit._ICR2\r
+#define ICR17_ICR1 icr17.bit._ICR1\r
+#define ICR17_ICR0 icr17.bit._ICR0\r
+__IO_EXTERN ICR18STR icr18; \r
+#define ICR18 icr18.byte\r
+#define ICR18_ICR4 icr18.bit._ICR4\r
+#define ICR18_ICR3 icr18.bit._ICR3\r
+#define ICR18_ICR2 icr18.bit._ICR2\r
+#define ICR18_ICR1 icr18.bit._ICR1\r
+#define ICR18_ICR0 icr18.bit._ICR0\r
+__IO_EXTERN ICR19STR icr19; \r
+#define ICR19 icr19.byte\r
+#define ICR19_ICR4 icr19.bit._ICR4\r
+#define ICR19_ICR3 icr19.bit._ICR3\r
+#define ICR19_ICR2 icr19.bit._ICR2\r
+#define ICR19_ICR1 icr19.bit._ICR1\r
+#define ICR19_ICR0 icr19.bit._ICR0\r
+__IO_EXTERN ICR20STR icr20; \r
+#define ICR20 icr20.byte\r
+#define ICR20_ICR4 icr20.bit._ICR4\r
+#define ICR20_ICR3 icr20.bit._ICR3\r
+#define ICR20_ICR2 icr20.bit._ICR2\r
+#define ICR20_ICR1 icr20.bit._ICR1\r
+#define ICR20_ICR0 icr20.bit._ICR0\r
+__IO_EXTERN ICR21STR icr21; \r
+#define ICR21 icr21.byte\r
+#define ICR21_ICR4 icr21.bit._ICR4\r
+#define ICR21_ICR3 icr21.bit._ICR3\r
+#define ICR21_ICR2 icr21.bit._ICR2\r
+#define ICR21_ICR1 icr21.bit._ICR1\r
+#define ICR21_ICR0 icr21.bit._ICR0\r
+__IO_EXTERN ICR22STR icr22; \r
+#define ICR22 icr22.byte\r
+#define ICR22_ICR4 icr22.bit._ICR4\r
+#define ICR22_ICR3 icr22.bit._ICR3\r
+#define ICR22_ICR2 icr22.bit._ICR2\r
+#define ICR22_ICR1 icr22.bit._ICR1\r
+#define ICR22_ICR0 icr22.bit._ICR0\r
+__IO_EXTERN ICR23STR icr23; \r
+#define ICR23 icr23.byte\r
+#define ICR23_ICR4 icr23.bit._ICR4\r
+#define ICR23_ICR3 icr23.bit._ICR3\r
+#define ICR23_ICR2 icr23.bit._ICR2\r
+#define ICR23_ICR1 icr23.bit._ICR1\r
+#define ICR23_ICR0 icr23.bit._ICR0\r
+__IO_EXTERN ICR24STR icr24; \r
+#define ICR24 icr24.byte\r
+#define ICR24_ICR4 icr24.bit._ICR4\r
+#define ICR24_ICR3 icr24.bit._ICR3\r
+#define ICR24_ICR2 icr24.bit._ICR2\r
+#define ICR24_ICR1 icr24.bit._ICR1\r
+#define ICR24_ICR0 icr24.bit._ICR0\r
+__IO_EXTERN ICR25STR icr25; \r
+#define ICR25 icr25.byte\r
+#define ICR25_ICR4 icr25.bit._ICR4\r
+#define ICR25_ICR3 icr25.bit._ICR3\r
+#define ICR25_ICR2 icr25.bit._ICR2\r
+#define ICR25_ICR1 icr25.bit._ICR1\r
+#define ICR25_ICR0 icr25.bit._ICR0\r
+__IO_EXTERN ICR26STR icr26; \r
+#define ICR26 icr26.byte\r
+#define ICR26_ICR4 icr26.bit._ICR4\r
+#define ICR26_ICR3 icr26.bit._ICR3\r
+#define ICR26_ICR2 icr26.bit._ICR2\r
+#define ICR26_ICR1 icr26.bit._ICR1\r
+#define ICR26_ICR0 icr26.bit._ICR0\r
+__IO_EXTERN ICR27STR icr27; \r
+#define ICR27 icr27.byte\r
+#define ICR27_ICR4 icr27.bit._ICR4\r
+#define ICR27_ICR3 icr27.bit._ICR3\r
+#define ICR27_ICR2 icr27.bit._ICR2\r
+#define ICR27_ICR1 icr27.bit._ICR1\r
+#define ICR27_ICR0 icr27.bit._ICR0\r
+__IO_EXTERN ICR28STR icr28; \r
+#define ICR28 icr28.byte\r
+#define ICR28_ICR4 icr28.bit._ICR4\r
+#define ICR28_ICR3 icr28.bit._ICR3\r
+#define ICR28_ICR2 icr28.bit._ICR2\r
+#define ICR28_ICR1 icr28.bit._ICR1\r
+#define ICR28_ICR0 icr28.bit._ICR0\r
+__IO_EXTERN ICR29STR icr29; \r
+#define ICR29 icr29.byte\r
+#define ICR29_ICR4 icr29.bit._ICR4\r
+#define ICR29_ICR3 icr29.bit._ICR3\r
+#define ICR29_ICR2 icr29.bit._ICR2\r
+#define ICR29_ICR1 icr29.bit._ICR1\r
+#define ICR29_ICR0 icr29.bit._ICR0\r
+__IO_EXTERN ICR30STR icr30; \r
+#define ICR30 icr30.byte\r
+#define ICR30_ICR4 icr30.bit._ICR4\r
+#define ICR30_ICR3 icr30.bit._ICR3\r
+#define ICR30_ICR2 icr30.bit._ICR2\r
+#define ICR30_ICR1 icr30.bit._ICR1\r
+#define ICR30_ICR0 icr30.bit._ICR0\r
+__IO_EXTERN ICR31STR icr31; \r
+#define ICR31 icr31.byte\r
+#define ICR31_ICR4 icr31.bit._ICR4\r
+#define ICR31_ICR3 icr31.bit._ICR3\r
+#define ICR31_ICR2 icr31.bit._ICR2\r
+#define ICR31_ICR1 icr31.bit._ICR1\r
+#define ICR31_ICR0 icr31.bit._ICR0\r
+__IO_EXTERN ICR32STR icr32; \r
+#define ICR32 icr32.byte\r
+#define ICR32_ICR4 icr32.bit._ICR4\r
+#define ICR32_ICR3 icr32.bit._ICR3\r
+#define ICR32_ICR2 icr32.bit._ICR2\r
+#define ICR32_ICR1 icr32.bit._ICR1\r
+#define ICR32_ICR0 icr32.bit._ICR0\r
+__IO_EXTERN ICR33STR icr33; \r
+#define ICR33 icr33.byte\r
+#define ICR33_ICR4 icr33.bit._ICR4\r
+#define ICR33_ICR3 icr33.bit._ICR3\r
+#define ICR33_ICR2 icr33.bit._ICR2\r
+#define ICR33_ICR1 icr33.bit._ICR1\r
+#define ICR33_ICR0 icr33.bit._ICR0\r
+__IO_EXTERN ICR34STR icr34; \r
+#define ICR34 icr34.byte\r
+#define ICR34_ICR4 icr34.bit._ICR4\r
+#define ICR34_ICR3 icr34.bit._ICR3\r
+#define ICR34_ICR2 icr34.bit._ICR2\r
+#define ICR34_ICR1 icr34.bit._ICR1\r
+#define ICR34_ICR0 icr34.bit._ICR0\r
+__IO_EXTERN ICR35STR icr35; \r
+#define ICR35 icr35.byte\r
+#define ICR35_ICR4 icr35.bit._ICR4\r
+#define ICR35_ICR3 icr35.bit._ICR3\r
+#define ICR35_ICR2 icr35.bit._ICR2\r
+#define ICR35_ICR1 icr35.bit._ICR1\r
+#define ICR35_ICR0 icr35.bit._ICR0\r
+__IO_EXTERN ICR36STR icr36; \r
+#define ICR36 icr36.byte\r
+#define ICR36_ICR4 icr36.bit._ICR4\r
+#define ICR36_ICR3 icr36.bit._ICR3\r
+#define ICR36_ICR2 icr36.bit._ICR2\r
+#define ICR36_ICR1 icr36.bit._ICR1\r
+#define ICR36_ICR0 icr36.bit._ICR0\r
+__IO_EXTERN ICR37STR icr37; \r
+#define ICR37 icr37.byte\r
+#define ICR37_ICR4 icr37.bit._ICR4\r
+#define ICR37_ICR3 icr37.bit._ICR3\r
+#define ICR37_ICR2 icr37.bit._ICR2\r
+#define ICR37_ICR1 icr37.bit._ICR1\r
+#define ICR37_ICR0 icr37.bit._ICR0\r
+__IO_EXTERN ICR38STR icr38; \r
+#define ICR38 icr38.byte\r
+#define ICR38_ICR4 icr38.bit._ICR4\r
+#define ICR38_ICR3 icr38.bit._ICR3\r
+#define ICR38_ICR2 icr38.bit._ICR2\r
+#define ICR38_ICR1 icr38.bit._ICR1\r
+#define ICR38_ICR0 icr38.bit._ICR0\r
+__IO_EXTERN ICR39STR icr39; \r
+#define ICR39 icr39.byte\r
+#define ICR39_ICR4 icr39.bit._ICR4\r
+#define ICR39_ICR3 icr39.bit._ICR3\r
+#define ICR39_ICR2 icr39.bit._ICR2\r
+#define ICR39_ICR1 icr39.bit._ICR1\r
+#define ICR39_ICR0 icr39.bit._ICR0\r
+__IO_EXTERN ICR40STR icr40; \r
+#define ICR40 icr40.byte\r
+#define ICR40_ICR4 icr40.bit._ICR4\r
+#define ICR40_ICR3 icr40.bit._ICR3\r
+#define ICR40_ICR2 icr40.bit._ICR2\r
+#define ICR40_ICR1 icr40.bit._ICR1\r
+#define ICR40_ICR0 icr40.bit._ICR0\r
+__IO_EXTERN ICR41STR icr41; \r
+#define ICR41 icr41.byte\r
+#define ICR41_ICR4 icr41.bit._ICR4\r
+#define ICR41_ICR3 icr41.bit._ICR3\r
+#define ICR41_ICR2 icr41.bit._ICR2\r
+#define ICR41_ICR1 icr41.bit._ICR1\r
+#define ICR41_ICR0 icr41.bit._ICR0\r
+__IO_EXTERN ICR42STR icr42; \r
+#define ICR42 icr42.byte\r
+#define ICR42_ICR4 icr42.bit._ICR4\r
+#define ICR42_ICR3 icr42.bit._ICR3\r
+#define ICR42_ICR2 icr42.bit._ICR2\r
+#define ICR42_ICR1 icr42.bit._ICR1\r
+#define ICR42_ICR0 icr42.bit._ICR0\r
+__IO_EXTERN ICR43STR icr43; \r
+#define ICR43 icr43.byte\r
+#define ICR43_ICR4 icr43.bit._ICR4\r
+#define ICR43_ICR3 icr43.bit._ICR3\r
+#define ICR43_ICR2 icr43.bit._ICR2\r
+#define ICR43_ICR1 icr43.bit._ICR1\r
+#define ICR43_ICR0 icr43.bit._ICR0\r
+__IO_EXTERN ICR44STR icr44; \r
+#define ICR44 icr44.byte\r
+#define ICR44_ICR4 icr44.bit._ICR4\r
+#define ICR44_ICR3 icr44.bit._ICR3\r
+#define ICR44_ICR2 icr44.bit._ICR2\r
+#define ICR44_ICR1 icr44.bit._ICR1\r
+#define ICR44_ICR0 icr44.bit._ICR0\r
+__IO_EXTERN ICR45STR icr45; \r
+#define ICR45 icr45.byte\r
+#define ICR45_ICR4 icr45.bit._ICR4\r
+#define ICR45_ICR3 icr45.bit._ICR3\r
+#define ICR45_ICR2 icr45.bit._ICR2\r
+#define ICR45_ICR1 icr45.bit._ICR1\r
+#define ICR45_ICR0 icr45.bit._ICR0\r
+__IO_EXTERN ICR46STR icr46; \r
+#define ICR46 icr46.byte\r
+#define ICR46_ICR4 icr46.bit._ICR4\r
+#define ICR46_ICR3 icr46.bit._ICR3\r
+#define ICR46_ICR2 icr46.bit._ICR2\r
+#define ICR46_ICR1 icr46.bit._ICR1\r
+#define ICR46_ICR0 icr46.bit._ICR0\r
+__IO_EXTERN ICR47STR icr47; \r
+#define ICR47 icr47.byte\r
+#define ICR47_ICR4 icr47.bit._ICR4\r
+#define ICR47_ICR3 icr47.bit._ICR3\r
+#define ICR47_ICR2 icr47.bit._ICR2\r
+#define ICR47_ICR1 icr47.bit._ICR1\r
+#define ICR47_ICR0 icr47.bit._ICR0\r
+__IO_EXTERN ICR48STR icr48; \r
+#define ICR48 icr48.byte\r
+#define ICR48_ICR4 icr48.bit._ICR4\r
+#define ICR48_ICR3 icr48.bit._ICR3\r
+#define ICR48_ICR2 icr48.bit._ICR2\r
+#define ICR48_ICR1 icr48.bit._ICR1\r
+#define ICR48_ICR0 icr48.bit._ICR0\r
+__IO_EXTERN ICR49STR icr49; \r
+#define ICR49 icr49.byte\r
+#define ICR49_ICR4 icr49.bit._ICR4\r
+#define ICR49_ICR3 icr49.bit._ICR3\r
+#define ICR49_ICR2 icr49.bit._ICR2\r
+#define ICR49_ICR1 icr49.bit._ICR1\r
+#define ICR49_ICR0 icr49.bit._ICR0\r
+__IO_EXTERN ICR50STR icr50; \r
+#define ICR50 icr50.byte\r
+#define ICR50_ICR4 icr50.bit._ICR4\r
+#define ICR50_ICR3 icr50.bit._ICR3\r
+#define ICR50_ICR2 icr50.bit._ICR2\r
+#define ICR50_ICR1 icr50.bit._ICR1\r
+#define ICR50_ICR0 icr50.bit._ICR0\r
+__IO_EXTERN ICR51STR icr51; \r
+#define ICR51 icr51.byte\r
+#define ICR51_ICR4 icr51.bit._ICR4\r
+#define ICR51_ICR3 icr51.bit._ICR3\r
+#define ICR51_ICR2 icr51.bit._ICR2\r
+#define ICR51_ICR1 icr51.bit._ICR1\r
+#define ICR51_ICR0 icr51.bit._ICR0\r
+__IO_EXTERN ICR52STR icr52; \r
+#define ICR52 icr52.byte\r
+#define ICR52_ICR4 icr52.bit._ICR4\r
+#define ICR52_ICR3 icr52.bit._ICR3\r
+#define ICR52_ICR2 icr52.bit._ICR2\r
+#define ICR52_ICR1 icr52.bit._ICR1\r
+#define ICR52_ICR0 icr52.bit._ICR0\r
+__IO_EXTERN ICR53STR icr53; \r
+#define ICR53 icr53.byte\r
+#define ICR53_ICR4 icr53.bit._ICR4\r
+#define ICR53_ICR3 icr53.bit._ICR3\r
+#define ICR53_ICR2 icr53.bit._ICR2\r
+#define ICR53_ICR1 icr53.bit._ICR1\r
+#define ICR53_ICR0 icr53.bit._ICR0\r
+__IO_EXTERN ICR54STR icr54; \r
+#define ICR54 icr54.byte\r
+#define ICR54_ICR4 icr54.bit._ICR4\r
+#define ICR54_ICR3 icr54.bit._ICR3\r
+#define ICR54_ICR2 icr54.bit._ICR2\r
+#define ICR54_ICR1 icr54.bit._ICR1\r
+#define ICR54_ICR0 icr54.bit._ICR0\r
+__IO_EXTERN ICR55STR icr55; \r
+#define ICR55 icr55.byte\r
+#define ICR55_ICR4 icr55.bit._ICR4\r
+#define ICR55_ICR3 icr55.bit._ICR3\r
+#define ICR55_ICR2 icr55.bit._ICR2\r
+#define ICR55_ICR1 icr55.bit._ICR1\r
+#define ICR55_ICR0 icr55.bit._ICR0\r
+__IO_EXTERN ICR56STR icr56; \r
+#define ICR56 icr56.byte\r
+#define ICR56_ICR4 icr56.bit._ICR4\r
+#define ICR56_ICR3 icr56.bit._ICR3\r
+#define ICR56_ICR2 icr56.bit._ICR2\r
+#define ICR56_ICR1 icr56.bit._ICR1\r
+#define ICR56_ICR0 icr56.bit._ICR0\r
+__IO_EXTERN ICR57STR icr57; \r
+#define ICR57 icr57.byte\r
+#define ICR57_ICR4 icr57.bit._ICR4\r
+#define ICR57_ICR3 icr57.bit._ICR3\r
+#define ICR57_ICR2 icr57.bit._ICR2\r
+#define ICR57_ICR1 icr57.bit._ICR1\r
+#define ICR57_ICR0 icr57.bit._ICR0\r
+__IO_EXTERN ICR58STR icr58; \r
+#define ICR58 icr58.byte\r
+#define ICR58_ICR4 icr58.bit._ICR4\r
+#define ICR58_ICR3 icr58.bit._ICR3\r
+#define ICR58_ICR2 icr58.bit._ICR2\r
+#define ICR58_ICR1 icr58.bit._ICR1\r
+#define ICR58_ICR0 icr58.bit._ICR0\r
+__IO_EXTERN ICR59STR icr59; \r
+#define ICR59 icr59.byte\r
+#define ICR59_ICR4 icr59.bit._ICR4\r
+#define ICR59_ICR3 icr59.bit._ICR3\r
+#define ICR59_ICR2 icr59.bit._ICR2\r
+#define ICR59_ICR1 icr59.bit._ICR1\r
+#define ICR59_ICR0 icr59.bit._ICR0\r
+__IO_EXTERN ICR60STR icr60; \r
+#define ICR60 icr60.byte\r
+#define ICR60_ICR4 icr60.bit._ICR4\r
+#define ICR60_ICR3 icr60.bit._ICR3\r
+#define ICR60_ICR2 icr60.bit._ICR2\r
+#define ICR60_ICR1 icr60.bit._ICR1\r
+#define ICR60_ICR0 icr60.bit._ICR0\r
+__IO_EXTERN ICR61STR icr61; \r
+#define ICR61 icr61.byte\r
+#define ICR61_ICR4 icr61.bit._ICR4\r
+#define ICR61_ICR3 icr61.bit._ICR3\r
+#define ICR61_ICR2 icr61.bit._ICR2\r
+#define ICR61_ICR1 icr61.bit._ICR1\r
+#define ICR61_ICR0 icr61.bit._ICR0\r
+__IO_EXTERN ICR62STR icr62; \r
+#define ICR62 icr62.byte\r
+#define ICR62_ICR4 icr62.bit._ICR4\r
+#define ICR62_ICR3 icr62.bit._ICR3\r
+#define ICR62_ICR2 icr62.bit._ICR2\r
+#define ICR62_ICR1 icr62.bit._ICR1\r
+#define ICR62_ICR0 icr62.bit._ICR0\r
+__IO_EXTERN ICR63STR icr63; \r
+#define ICR63 icr63.byte\r
+#define ICR63_ICR4 icr63.bit._ICR4\r
+#define ICR63_ICR3 icr63.bit._ICR3\r
+#define ICR63_ICR2 icr63.bit._ICR2\r
+#define ICR63_ICR1 icr63.bit._ICR1\r
+#define ICR63_ICR0 icr63.bit._ICR0\r
+__IO_EXTERN RSRRSTR rsrr; /* Clock Control Unit */\r
+#define RSRR rsrr.byte\r
+#define RSRR_INIT rsrr.bit._INIT\r
+#define RSRR_HSTB rsrr.bit._HSTB\r
+#define RSRR_WDOG rsrr.bit._WDOG\r
+#define RSRR_ERST rsrr.bit._ERST\r
+#define RSRR_SRST rsrr.bit._SRST\r
+#define RSRR_LINIT rsrr.bit._LINIT\r
+#define RSRR_WT1 rsrr.bit._WT1\r
+#define RSRR_WT0 rsrr.bit._WT0\r
+#define RSRR_WT rsrr.bitc._WT\r
+__IO_EXTERN STCRSTR stcr; \r
+#define STCR stcr.byte\r
+#define STCR_STOP stcr.bit._STOP\r
+#define STCR_SLEEP stcr.bit._SLEEP\r
+#define STCR_HIZ stcr.bit._HIZ\r
+#define STCR_SRST stcr.bit._SRST\r
+#define STCR_OS1 stcr.bit._OS1\r
+#define STCR_OS0 stcr.bit._OS0\r
+#define STCR_OSCD2 stcr.bit._OSCD2\r
+#define STCR_OSCD1 stcr.bit._OSCD1\r
+#define STCR_OS stcr.bitc._OS\r
+#define STCR_OSCD stcr.bitc._OSCD\r
+__IO_EXTERN TBCRSTR tbcr; \r
+#define TBCR tbcr.byte\r
+#define TBCR_TBIF tbcr.bit._TBIF\r
+#define TBCR_TBIE tbcr.bit._TBIE\r
+#define TBCR_TBC2 tbcr.bit._TBC2\r
+#define TBCR_TBC1 tbcr.bit._TBC1\r
+#define TBCR_TBC0 tbcr.bit._TBC0\r
+#define TBCR_SYNCR tbcr.bit._SYNCR\r
+#define TBCR_SYNCS tbcr.bit._SYNCS\r
+#define TBCR_TBC tbcr.bitc._TBC\r
+__IO_EXTERN CTBRSTR ctbr; \r
+#define CTBR ctbr.byte\r
+#define CTBR_D7 ctbr.bit._D7\r
+#define CTBR_D6 ctbr.bit._D6\r
+#define CTBR_D5 ctbr.bit._D5\r
+#define CTBR_D4 ctbr.bit._D4\r
+#define CTBR_D3 ctbr.bit._D3\r
+#define CTBR_D2 ctbr.bit._D2\r
+#define CTBR_D1 ctbr.bit._D1\r
+#define CTBR_D0 ctbr.bit._D0\r
+__IO_EXTERN CLKRSTR clkr; \r
+#define CLKR clkr.byte\r
+#define CLKR_SCKEN clkr.bit._SCKEN\r
+#define CLKR_PLL1EN clkr.bit._PLL1EN\r
+#define CLKR_CLKS1 clkr.bit._CLKS1\r
+#define CLKR_CLKS0 clkr.bit._CLKS0\r
+#define CLKR_CLKS clkr.bitc._CLKS\r
+__IO_EXTERN WPRSTR wpr; \r
+#define WPR wpr.byte\r
+#define WPR_D7 wpr.bit._D7\r
+#define WPR_D6 wpr.bit._D6\r
+#define WPR_D5 wpr.bit._D5\r
+#define WPR_D4 wpr.bit._D4\r
+#define WPR_D3 wpr.bit._D3\r
+#define WPR_D2 wpr.bit._D2\r
+#define WPR_D1 wpr.bit._D1\r
+#define WPR_D0 wpr.bit._D0\r
+__IO_EXTERN DIVR0STR divr0; \r
+#define DIVR0 divr0.byte\r
+#define DIVR0_B3 divr0.bit._B3\r
+#define DIVR0_B2 divr0.bit._B2\r
+#define DIVR0_B1 divr0.bit._B1\r
+#define DIVR0_B0 divr0.bit._B0\r
+#define DIVR0_P3 divr0.bit._P3\r
+#define DIVR0_P2 divr0.bit._P2\r
+#define DIVR0_P1 divr0.bit._P1\r
+#define DIVR0_P0 divr0.bit._P0\r
+#define DIVR0_B divr0.bitc._B\r
+#define DIVR0_P divr0.bitc._P\r
+__IO_EXTERN DIVR1STR divr1; \r
+#define DIVR1 divr1.byte\r
+#define DIVR1_T3 divr1.bit._T3\r
+#define DIVR1_T2 divr1.bit._T2\r
+#define DIVR1_T1 divr1.bit._T1\r
+#define DIVR1_T0 divr1.bit._T0\r
+#define DIVR1_T divr1.bitc._T\r
+__IO_EXTERN PLLDIVMSTR plldivm; /* PLL - Clock Gear Unit: */\r
+#define PLLDIVM plldivm.byte\r
+#define PLLDIVM_DVM3 plldivm.bit._DVM3\r
+#define PLLDIVM_DVM2 plldivm.bit._DVM2\r
+#define PLLDIVM_DVM1 plldivm.bit._DVM1\r
+#define PLLDIVM_DVM0 plldivm.bit._DVM0\r
+#define PLLDIVM_DVM plldivm.bitc._DVM\r
+__IO_EXTERN PLLDIVNSTR plldivn; \r
+#define PLLDIVN plldivn.byte\r
+#define PLLDIVN_DVN5 plldivn.bit._DVN5\r
+#define PLLDIVN_DVN4 plldivn.bit._DVN4\r
+#define PLLDIVN_DVN3 plldivn.bit._DVN3\r
+#define PLLDIVN_DVN2 plldivn.bit._DVN2\r
+#define PLLDIVN_DVN1 plldivn.bit._DVN1\r
+#define PLLDIVN_DVN0 plldivn.bit._DVN0\r
+#define PLLDIVN_DVN plldivn.bitc._DVN\r
+__IO_EXTERN PLLDIVGSTR plldivg; \r
+#define PLLDIVG plldivg.byte\r
+#define PLLDIVG_DVG3 plldivg.bit._DVG3\r
+#define PLLDIVG_DVG2 plldivg.bit._DVG2\r
+#define PLLDIVG_DVG1 plldivg.bit._DVG1\r
+#define PLLDIVG_DVG0 plldivg.bit._DVG0\r
+#define PLLDIVG_DVG plldivg.bitc._DVG\r
+__IO_EXTERN PLLMULGSTR pllmulg; \r
+#define PLLMULG pllmulg.byte\r
+#define PLLMULG_MLG7 pllmulg.bit._MLG7\r
+#define PLLMULG_MLG6 pllmulg.bit._MLG6\r
+#define PLLMULG_MLG5 pllmulg.bit._MLG5\r
+#define PLLMULG_MLG4 pllmulg.bit._MLG4\r
+#define PLLMULG_MLG3 pllmulg.bit._MLG3\r
+#define PLLMULG_MLG2 pllmulg.bit._MLG2\r
+#define PLLMULG_MLG1 pllmulg.bit._MLG1\r
+#define PLLMULG_MLG0 pllmulg.bit._MLG0\r
+#define PLLMULG_MLG pllmulg.bitc._MLG\r
+__IO_EXTERN PLLCTRLSTR pllctrl; \r
+#define PLLCTRL pllctrl.byte\r
+#define PLLCTRL_IEDN pllctrl.bit._IEDN\r
+#define PLLCTRL_GRDN pllctrl.bit._GRDN\r
+#define PLLCTRL_IEUP pllctrl.bit._IEUP\r
+#define PLLCTRL_GRUP pllctrl.bit._GRUP\r
+__IO_EXTERN OSCC1STR oscc1; /* Main/Sub Oscillator Control */\r
+#define OSCC1 oscc1.byte\r
+#define OSCC1_FCI oscc1.bit._FCI\r
+#define OSCC1_RFBEN oscc1.bit._RFBEN\r
+#define OSCC1_OSCR oscc1.bit._OSCR\r
+__IO_EXTERN OSCS1STR oscs1; \r
+#define OSCS1 oscs1.byte\r
+#define OSCS1_OSCS7 oscs1.bit._OSCS7\r
+#define OSCS1_OSCS6 oscs1.bit._OSCS6\r
+#define OSCS1_OSCS5 oscs1.bit._OSCS5\r
+#define OSCS1_OSCS4 oscs1.bit._OSCS4\r
+#define OSCS1_OSCS3 oscs1.bit._OSCS3\r
+#define OSCS1_OSCS2 oscs1.bit._OSCS2\r
+#define OSCS1_OSCS1 oscs1.bit._OSCS1\r
+#define OSCS1_OSCS0 oscs1.bit._OSCS0\r
+__IO_EXTERN OSCC2STR oscc2; \r
+#define OSCC2 oscc2.byte\r
+#define OSCC2_FCI oscc2.bit._FCI\r
+#define OSCC2_RFBEN oscc2.bit._RFBEN\r
+#define OSCC2_OSCR oscc2.bit._OSCR\r
+__IO_EXTERN OSCS2STR oscs2; \r
+#define OSCS2 oscs2.byte\r
+#define OSCS2_OSCS7 oscs2.bit._OSCS7\r
+#define OSCS2_OSCS6 oscs2.bit._OSCS6\r
+#define OSCS2_OSCS5 oscs2.bit._OSCS5\r
+#define OSCS2_OSCS4 oscs2.bit._OSCS4\r
+#define OSCS2_OSCS3 oscs2.bit._OSCS3\r
+#define OSCS2_OSCS2 oscs2.bit._OSCS2\r
+#define OSCS2_OSCS1 oscs2.bit._OSCS1\r
+#define OSCS2_OSCS0 oscs2.bit._OSCS0\r
+__IO_EXTERN PORTENSTR porten; /* Port Input Enable Control */\r
+#define PORTEN porten.byte\r
+#define PORTEN_CPORTEN porten.bit._CPORTEN\r
+#define PORTEN_GPORTEN porten.bit._GPORTEN\r
+__IO_EXTERN WTCERSTR wtcer; /* Real Time Clock (Watch Timer) */\r
+#define WTCER wtcer.byte\r
+#define WTCER_INTE4 wtcer.bit._INTE4\r
+#define WTCER_INT4 wtcer.bit._INT4\r
+__IO_EXTERN WTCRSTR wtcr; \r
+#define WTCR wtcr.word\r
+#define WTCR_INTE3 wtcr.bit._INTE3\r
+#define WTCR_INT3 wtcr.bit._INT3\r
+#define WTCR_INTE2 wtcr.bit._INTE2\r
+#define WTCR_INT2 wtcr.bit._INT2\r
+#define WTCR_INTE1 wtcr.bit._INTE1\r
+#define WTCR_INT1 wtcr.bit._INT1\r
+#define WTCR_INTE0 wtcr.bit._INTE0\r
+#define WTCR_INT0 wtcr.bit._INT0\r
+#define WTCR_RUN wtcr.bit._RUN\r
+#define WTCR_UPDT wtcr.bit._UPDT\r
+#define WTCR_ST wtcr.bit._ST\r
+__IO_EXTERN WTBRSTR wtbr; \r
+#define WTBR wtbr.lword\r
+#define WTBR_D20 wtbr.bit._D20\r
+#define WTBR_D19 wtbr.bit._D19\r
+#define WTBR_D18 wtbr.bit._D18\r
+#define WTBR_D17 wtbr.bit._D17\r
+#define WTBR_D16 wtbr.bit._D16\r
+#define WTBR_D15 wtbr.bit._D15\r
+#define WTBR_D14 wtbr.bit._D14\r
+#define WTBR_D13 wtbr.bit._D13\r
+#define WTBR_D12 wtbr.bit._D12\r
+#define WTBR_D11 wtbr.bit._D11\r
+#define WTBR_D10 wtbr.bit._D10\r
+#define WTBR_D9 wtbr.bit._D9\r
+#define WTBR_D8 wtbr.bit._D8\r
+#define WTBR_D7 wtbr.bit._D7\r
+#define WTBR_D6 wtbr.bit._D6\r
+#define WTBR_D5 wtbr.bit._D5\r
+#define WTBR_D4 wtbr.bit._D4\r
+#define WTBR_D3 wtbr.bit._D3\r
+#define WTBR_D2 wtbr.bit._D2\r
+#define WTBR_D1 wtbr.bit._D1\r
+#define WTBR_D0 wtbr.bit._D0\r
+__IO_EXTERN WTHRSTR wthr; \r
+#define WTHR wthr.byte\r
+#define WTHR_H4 wthr.bit._H4\r
+#define WTHR_H3 wthr.bit._H3\r
+#define WTHR_H2 wthr.bit._H2\r
+#define WTHR_H1 wthr.bit._H1\r
+#define WTHR_H0 wthr.bit._H0\r
+__IO_EXTERN WTMRSTR wtmr; \r
+#define WTMR wtmr.byte\r
+#define WTMR_M5 wtmr.bit._M5\r
+#define WTMR_M4 wtmr.bit._M4\r
+#define WTMR_M3 wtmr.bit._M3\r
+#define WTMR_M2 wtmr.bit._M2\r
+#define WTMR_M1 wtmr.bit._M1\r
+#define WTMR_M0 wtmr.bit._M0\r
+__IO_EXTERN WTSRSTR wtsr; \r
+#define WTSR wtsr.byte\r
+#define WTSR_S5 wtsr.bit._S5\r
+#define WTSR_S4 wtsr.bit._S4\r
+#define WTSR_S3 wtsr.bit._S3\r
+#define WTSR_S2 wtsr.bit._S2\r
+#define WTSR_S1 wtsr.bit._S1\r
+#define WTSR_S0 wtsr.bit._S0\r
+__IO_EXTERN IO_BYTE csvtr; /* Clock-Supervisor / Selecor / Monitor */\r
+#define CSVTR csvtr\r
+__IO_EXTERN CSVCRSTR csvcr; \r
+#define CSVCR csvcr.byte\r
+#define CSVCR_SCKS csvcr.bit._SCKS\r
+#define CSVCR_MM csvcr.bit._MM\r
+#define CSVCR_SM csvcr.bit._SM\r
+#define CSVCR_RCE csvcr.bit._RCE\r
+#define CSVCR_MSVE csvcr.bit._MSVE\r
+#define CSVCR_SSVE csvcr.bit._SSVE\r
+#define CSVCR_SRST csvcr.bit._SRST\r
+#define CSVCR_OUTE csvcr.bit._OUTE\r
+__IO_EXTERN CSCFGSTR cscfg; \r
+#define CSCFG cscfg.byte\r
+#define CSCFG_EDSUEN cscfg.bit._EDSUEN\r
+#define CSCFG_PLLLOCK cscfg.bit._PLLLOCK\r
+#define CSCFG_RCSEL cscfg.bit._RCSEL\r
+#define CSCFG_MONCKI cscfg.bit._MONCKI\r
+#define CSCFG_CSC3 cscfg.bit._CSC3\r
+#define CSCFG_CSC2 cscfg.bit._CSC2\r
+#define CSCFG_CSC1 cscfg.bit._CSC1\r
+#define CSCFG_CSC0 cscfg.bit._CSC0\r
+#define CSCFG_CSC cscfg.bitc._CSC\r
+__IO_EXTERN CMCFGSTR cmcfg; \r
+#define CMCFG cmcfg.byte\r
+#define CMCFG_CMPRE3 cmcfg.bit._CMPRE3\r
+#define CMCFG_CMPRE2 cmcfg.bit._CMPRE2\r
+#define CMCFG_CMPRE1 cmcfg.bit._CMPRE1\r
+#define CMCFG_CMPRE0 cmcfg.bit._CMPRE0\r
+#define CMCFG_CMSEL3 cmcfg.bit._CMSEL3\r
+#define CMCFG_CMSEL2 cmcfg.bit._CMSEL2\r
+#define CMCFG_CMSEL1 cmcfg.bit._CMSEL1\r
+#define CMCFG_CMSEL0 cmcfg.bit._CMSEL0\r
+#define CMCFG_CMPRE cmcfg.bitc._CMPRE\r
+#define CMCFG_CMSEL cmcfg.bitc._CMSEL\r
+__IO_EXTERN CUCRSTR cucr; /* Calibration Unit of Sub Oszillation */\r
+#define CUCR cucr.word\r
+#define CUCR_STRT cucr.bit._STRT\r
+#define CUCR_INT cucr.bit._INT\r
+#define CUCR_INTEN cucr.bit._INTEN\r
+__IO_EXTERN CUTDSTR cutd; \r
+#define CUTD cutd.word\r
+#define CUTD_TDD15 cutd.bit._TDD15\r
+#define CUTD_TDD14 cutd.bit._TDD14\r
+#define CUTD_TDD13 cutd.bit._TDD13\r
+#define CUTD_TDD12 cutd.bit._TDD12\r
+#define CUTD_TDD11 cutd.bit._TDD11\r
+#define CUTD_TDD10 cutd.bit._TDD10\r
+#define CUTD_TDD9 cutd.bit._TDD9\r
+#define CUTD_TDD8 cutd.bit._TDD8\r
+#define CUTD_TDD7 cutd.bit._TDD7\r
+#define CUTD_TDD6 cutd.bit._TDD6\r
+#define CUTD_TDD5 cutd.bit._TDD5\r
+#define CUTD_TDD4 cutd.bit._TDD4\r
+#define CUTD_TDD3 cutd.bit._TDD3\r
+#define CUTD_TDD2 cutd.bit._TDD2\r
+#define CUTD_TDD1 cutd.bit._TDD1\r
+#define CUTD_TDD0 cutd.bit._TDD0\r
+__IO_EXTERN CUTR1STR cutr1; \r
+#define CUTR1 cutr1.word\r
+#define CUTR1_TDR23 cutr1.bit._TDR23\r
+#define CUTR1_TDR22 cutr1.bit._TDR22\r
+#define CUTR1_TDR21 cutr1.bit._TDR21\r
+#define CUTR1_TDR20 cutr1.bit._TDR20\r
+#define CUTR1_TDR19 cutr1.bit._TDR19\r
+#define CUTR1_TDR18 cutr1.bit._TDR18\r
+#define CUTR1_TDR17 cutr1.bit._TDR17\r
+#define CUTR1_TDR16 cutr1.bit._TDR16\r
+__IO_EXTERN CUTR2STR cutr2; \r
+#define CUTR2 cutr2.word\r
+#define CUTR2_TDR15 cutr2.bit._TDR15\r
+#define CUTR2_TDR14 cutr2.bit._TDR14\r
+#define CUTR2_TDR13 cutr2.bit._TDR13\r
+#define CUTR2_TDR12 cutr2.bit._TDR12\r
+#define CUTR2_TDR11 cutr2.bit._TDR11\r
+#define CUTR2_TDR10 cutr2.bit._TDR10\r
+#define CUTR2_TDR9 cutr2.bit._TDR9\r
+#define CUTR2_TDR8 cutr2.bit._TDR8\r
+#define CUTR2_TDR7 cutr2.bit._TDR7\r
+#define CUTR2_TDR6 cutr2.bit._TDR6\r
+#define CUTR2_TDR5 cutr2.bit._TDR5\r
+#define CUTR2_TDR4 cutr2.bit._TDR4\r
+#define CUTR2_TDR3 cutr2.bit._TDR3\r
+#define CUTR2_TDR2 cutr2.bit._TDR2\r
+#define CUTR2_TDR1 cutr2.bit._TDR1\r
+#define CUTR2_TDR0 cutr2.bit._TDR0\r
+__IO_EXTERN CMPRSTR cmpr; /* Clock Modulator */\r
+#define CMPR cmpr.word\r
+#define CMPR_MP13 cmpr.bit._MP13\r
+#define CMPR_MP12 cmpr.bit._MP12\r
+#define CMPR_MP11 cmpr.bit._MP11\r
+#define CMPR_MP10 cmpr.bit._MP10\r
+#define CMPR_MP9 cmpr.bit._MP9\r
+#define CMPR_MP8 cmpr.bit._MP8\r
+#define CMPR_MP7 cmpr.bit._MP7\r
+#define CMPR_MP6 cmpr.bit._MP6\r
+#define CMPR_MP5 cmpr.bit._MP5\r
+#define CMPR_MP4 cmpr.bit._MP4\r
+#define CMPR_MP3 cmpr.bit._MP3\r
+#define CMPR_MP2 cmpr.bit._MP2\r
+#define CMPR_MP1 cmpr.bit._MP1\r
+#define CMPR_MP0 cmpr.bit._MP0\r
+__IO_EXTERN CMCRSTR cmcr; \r
+#define CMCR cmcr.byte\r
+#define CMCR_FMODRUN cmcr.bit._FMODRUN\r
+#define CMCR_FMOD cmcr.bit._FMOD\r
+#define CMCR_PDX cmcr.bit._PDX\r
+__IO_EXTERN IO_WORD cmt1; \r
+#define CMT1 cmt1\r
+__IO_EXTERN IO_WORD cmt2; \r
+#define CMT2 cmt2\r
+__IO_EXTERN CANPRESTR canpre; /* CAN clock control */\r
+#define CANPRE canpre.byte\r
+#define CANPRE_CPCKS1 canpre.bit._CPCKS1\r
+#define CANPRE_CPCKS0 canpre.bit._CPCKS0\r
+#define CANPRE_DVC3 canpre.bit._DVC3\r
+#define CANPRE_DVC2 canpre.bit._DVC2\r
+#define CANPRE_DVC1 canpre.bit._DVC1\r
+#define CANPRE_DVC0 canpre.bit._DVC0\r
+#define CANPRE_CPCKS canpre.bitc._CPCKS\r
+#define CANPRE_DVC canpre.bitc._DVC\r
+__IO_EXTERN CANCKDSTR canckd; \r
+#define CANCKD canckd.byte\r
+#define CANCKD_CANCKD5 canckd.bit._CANCKD5\r
+#define CANCKD_CANCKD4 canckd.bit._CANCKD4\r
+#define CANCKD_CANCKD3 canckd.bit._CANCKD3\r
+#define CANCKD_CANCKD2 canckd.bit._CANCKD2\r
+#define CANCKD_CANCKD1 canckd.bit._CANCKD1\r
+#define CANCKD_CANCKD0 canckd.bit._CANCKD0\r
+__IO_EXTERN LVSELSTR lvsel; /* LV Detection / Hardware-Watchdog */\r
+#define LVSEL lvsel.byte\r
+#define LVSEL_LVESEL3 lvsel.bit._LVESEL3\r
+#define LVSEL_LVESEL2 lvsel.bit._LVESEL2\r
+#define LVSEL_LVESEL1 lvsel.bit._LVESEL1\r
+#define LVSEL_LVESEL0 lvsel.bit._LVESEL0\r
+#define LVSEL_LVISEL3 lvsel.bit._LVISEL3\r
+#define LVSEL_LVISEL2 lvsel.bit._LVISEL2\r
+#define LVSEL_LVISEL1 lvsel.bit._LVISEL1\r
+#define LVSEL_LVISEL0 lvsel.bit._LVISEL0\r
+#define LVSEL_LVESEL lvsel.bitc._LVESEL\r
+#define LVSEL_LVISEL lvsel.bitc._LVISEL\r
+__IO_EXTERN LVDETSTR lvdet; \r
+#define LVDET lvdet.byte\r
+#define LVDET_LVSEL lvdet.bit._LVSEL\r
+#define LVDET_LVEPD lvdet.bit._LVEPD\r
+#define LVDET_LVIPD lvdet.bit._LVIPD\r
+#define LVDET_LVREN lvdet.bit._LVREN\r
+#define LVDET_LVIEN lvdet.bit._LVIEN\r
+#define LVDET_LVIRQ lvdet.bit._LVIRQ\r
+__IO_EXTERN HWWDESTR hwwde; \r
+#define HWWDE hwwde.byte\r
+#define HWWDE_ED1 hwwde.bit._ED1\r
+#define HWWDE_ED0 hwwde.bit._ED0\r
+#define HWWDE_ED hwwde.bitc._ED\r
+__IO_EXTERN HWWDSTR hwwd; \r
+#define HWWD hwwd.byte\r
+#define HWWD_CL hwwd.bit._CL\r
+#define HWWD_CPUF hwwd.bit._CPUF\r
+__IO_EXTERN OSCRHSTR oscrh; /* Main-/Sub-Oscillatio Stabilization Timer */\r
+#define OSCRH oscrh.byte\r
+#define OSCRH_WIF oscrh.bit._WIF\r
+#define OSCRH_WIE oscrh.bit._WIE\r
+#define OSCRH_WEN oscrh.bit._WEN\r
+#define OSCRH_WS1 oscrh.bit._WS1\r
+#define OSCRH_WS0 oscrh.bit._WS0\r
+#define OSCRH_WCL oscrh.bit._WCL\r
+#define OSCRH_WS oscrh.bitc._WS\r
+__IO_EXTERN IO_BYTE oscrl; \r
+#define OSCRL oscrl\r
+__IO_EXTERN WPCRHSTR wpcrh; \r
+#define WPCRH wpcrh.byte\r
+#define WPCRH_WIF wpcrh.bit._WIF\r
+#define WPCRH_WIE wpcrh.bit._WIE\r
+#define WPCRH_WEN wpcrh.bit._WEN\r
+#define WPCRH_WS1 wpcrh.bit._WS1\r
+#define WPCRH_WS0 wpcrh.bit._WS0\r
+#define WPCRH_WCL wpcrh.bit._WCL\r
+#define WPCRH_WS wpcrh.bitc._WS\r
+__IO_EXTERN IO_BYTE wpcrl; \r
+#define WPCRL wpcrl\r
+__IO_EXTERN OSCCRSTR osccr; /* Main-/Sub-Oscillatio Standby Control */\r
+#define OSCCR osccr.byte\r
+#define OSCCR_OSCDS1 osccr.bit._OSCDS1\r
+__IO_EXTERN REGSELSTR regsel; \r
+#define REGSEL regsel.byte\r
+#define REGSEL_FLASHSEL regsel.bit._FLASHSEL\r
+#define REGSEL_MAINSEL regsel.bit._MAINSEL\r
+#define REGSEL_SUBSEL3 regsel.bit._SUBSEL3\r
+#define REGSEL_SUBSEL2 regsel.bit._SUBSEL2\r
+#define REGSEL_SUBSEL1 regsel.bit._SUBSEL1\r
+#define REGSEL_SUBSEL0 regsel.bit._SUBSEL0\r
+#define REGSEL_SUBSEL regsel.bitc._SUBSEL\r
+__IO_EXTERN REGCTRSTR regctr; \r
+#define REGCTR regctr.byte\r
+#define REGCTR_MSTBO regctr.bit._MSTBO\r
+#define REGCTR_MAINKPEN regctr.bit._MAINKPEN\r
+#define REGCTR_MAINDSBL regctr.bit._MAINDSBL\r
+__IO_EXTERN MODRSTR modr; /* Mode Register */\r
+#define MODR modr.byte\r
+#define MODR_ROMA modr.bit._ROMA\r
+#define MODR_WTH1 modr.bit._WTH1\r
+#define MODR_WTH0 modr.bit._WTH0\r
+#define MODR_WTH modr.bitc._WTH\r
+__IO_EXTERN PDRD14STR pdrd14; /* R-bus Port Data Direct Read Register */\r
+#define PDRD14 pdrd14.byte\r
+#define PDRD14_D7 pdrd14.bit._D7\r
+#define PDRD14_D6 pdrd14.bit._D6\r
+#define PDRD14_D5 pdrd14.bit._D5\r
+#define PDRD14_D4 pdrd14.bit._D4\r
+#define PDRD14_D3 pdrd14.bit._D3\r
+#define PDRD14_D2 pdrd14.bit._D2\r
+#define PDRD14_D1 pdrd14.bit._D1\r
+#define PDRD14_D0 pdrd14.bit._D0\r
+__IO_EXTERN PDRD15STR pdrd15; \r
+#define PDRD15 pdrd15.byte\r
+#define PDRD15_D7 pdrd15.bit._D7\r
+#define PDRD15_D6 pdrd15.bit._D6\r
+#define PDRD15_D5 pdrd15.bit._D5\r
+#define PDRD15_D4 pdrd15.bit._D4\r
+#define PDRD15_D3 pdrd15.bit._D3\r
+#define PDRD15_D2 pdrd15.bit._D2\r
+#define PDRD15_D1 pdrd15.bit._D1\r
+#define PDRD15_D0 pdrd15.bit._D0\r
+__IO_EXTERN PDRD16STR pdrd16; \r
+#define PDRD16 pdrd16.byte\r
+#define PDRD16_D7 pdrd16.bit._D7\r
+#define PDRD16_D6 pdrd16.bit._D6\r
+#define PDRD16_D5 pdrd16.bit._D5\r
+#define PDRD16_D4 pdrd16.bit._D4\r
+#define PDRD16_D3 pdrd16.bit._D3\r
+#define PDRD16_D2 pdrd16.bit._D2\r
+#define PDRD16_D1 pdrd16.bit._D1\r
+#define PDRD16_D0 pdrd16.bit._D0\r
+__IO_EXTERN PDRD17STR pdrd17; \r
+#define PDRD17 pdrd17.byte\r
+#define PDRD17_D7 pdrd17.bit._D7\r
+#define PDRD17_D6 pdrd17.bit._D6\r
+#define PDRD17_D5 pdrd17.bit._D5\r
+#define PDRD17_D4 pdrd17.bit._D4\r
+#define PDRD17_D3 pdrd17.bit._D3\r
+#define PDRD17_D2 pdrd17.bit._D2\r
+#define PDRD17_D1 pdrd17.bit._D1\r
+#define PDRD17_D0 pdrd17.bit._D0\r
+__IO_EXTERN PDRD18STR pdrd18; \r
+#define PDRD18 pdrd18.byte\r
+#define PDRD18_D6 pdrd18.bit._D6\r
+#define PDRD18_D2 pdrd18.bit._D2\r
+__IO_EXTERN PDRD19STR pdrd19; \r
+#define PDRD19 pdrd19.byte\r
+#define PDRD19_D6 pdrd19.bit._D6\r
+#define PDRD19_D2 pdrd19.bit._D2\r
+#define PDRD19_D1 pdrd19.bit._D1\r
+#define PDRD19_D0 pdrd19.bit._D0\r
+__IO_EXTERN PDRD20STR pdrd20; \r
+#define PDRD20 pdrd20.byte\r
+#define PDRD20_D7 pdrd20.bit._D7\r
+#define PDRD20_D6 pdrd20.bit._D6\r
+#define PDRD20_D5 pdrd20.bit._D5\r
+#define PDRD20_D4 pdrd20.bit._D4\r
+#define PDRD20_D3 pdrd20.bit._D3\r
+#define PDRD20_D2 pdrd20.bit._D2\r
+#define PDRD20_D1 pdrd20.bit._D1\r
+#define PDRD20_D0 pdrd20.bit._D0\r
+__IO_EXTERN PDRD21STR pdrd21; \r
+#define PDRD21 pdrd21.byte\r
+#define PDRD21_D7 pdrd21.bit._D7\r
+#define PDRD21_D6 pdrd21.bit._D6\r
+#define PDRD21_D5 pdrd21.bit._D5\r
+#define PDRD21_D4 pdrd21.bit._D4\r
+#define PDRD21_D3 pdrd21.bit._D3\r
+#define PDRD21_D2 pdrd21.bit._D2\r
+#define PDRD21_D1 pdrd21.bit._D1\r
+#define PDRD21_D0 pdrd21.bit._D0\r
+__IO_EXTERN PDRD22STR pdrd22; \r
+#define PDRD22 pdrd22.byte\r
+#define PDRD22_D5 pdrd22.bit._D5\r
+#define PDRD22_D4 pdrd22.bit._D4\r
+#define PDRD22_D1 pdrd22.bit._D1\r
+#define PDRD22_D0 pdrd22.bit._D0\r
+__IO_EXTERN PDRD24STR pdrd24; \r
+#define PDRD24 pdrd24.byte\r
+#define PDRD24_D7 pdrd24.bit._D7\r
+#define PDRD24_D6 pdrd24.bit._D6\r
+#define PDRD24_D5 pdrd24.bit._D5\r
+#define PDRD24_D4 pdrd24.bit._D4\r
+#define PDRD24_D3 pdrd24.bit._D3\r
+#define PDRD24_D2 pdrd24.bit._D2\r
+#define PDRD24_D1 pdrd24.bit._D1\r
+#define PDRD24_D0 pdrd24.bit._D0\r
+__IO_EXTERN PDRD26STR pdrd26; \r
+#define PDRD26 pdrd26.byte\r
+#define PDRD26_D1 pdrd26.bit._D1\r
+#define PDRD26_D0 pdrd26.bit._D0\r
+__IO_EXTERN PDRD27STR pdrd27; \r
+#define PDRD27 pdrd27.byte\r
+#define PDRD27_D7 pdrd27.bit._D7\r
+#define PDRD27_D6 pdrd27.bit._D6\r
+#define PDRD27_D5 pdrd27.bit._D5\r
+#define PDRD27_D4 pdrd27.bit._D4\r
+#define PDRD27_D3 pdrd27.bit._D3\r
+#define PDRD27_D2 pdrd27.bit._D2\r
+#define PDRD27_D1 pdrd27.bit._D1\r
+#define PDRD27_D0 pdrd27.bit._D0\r
+__IO_EXTERN PDRD28STR pdrd28; \r
+#define PDRD28 pdrd28.byte\r
+#define PDRD28_D7 pdrd28.bit._D7\r
+#define PDRD28_D6 pdrd28.bit._D6\r
+#define PDRD28_D5 pdrd28.bit._D5\r
+#define PDRD28_D4 pdrd28.bit._D4\r
+#define PDRD28_D3 pdrd28.bit._D3\r
+#define PDRD28_D2 pdrd28.bit._D2\r
+#define PDRD28_D1 pdrd28.bit._D1\r
+#define PDRD28_D0 pdrd28.bit._D0\r
+__IO_EXTERN PDRD29STR pdrd29; \r
+#define PDRD29 pdrd29.byte\r
+#define PDRD29_D7 pdrd29.bit._D7\r
+#define PDRD29_D6 pdrd29.bit._D6\r
+#define PDRD29_D5 pdrd29.bit._D5\r
+#define PDRD29_D4 pdrd29.bit._D4\r
+#define PDRD29_D3 pdrd29.bit._D3\r
+#define PDRD29_D2 pdrd29.bit._D2\r
+#define PDRD29_D1 pdrd29.bit._D1\r
+#define PDRD29_D0 pdrd29.bit._D0\r
+__IO_EXTERN DDR14STR ddr14; /* R-bus Port Direction Register */\r
+#define DDR14 ddr14.byte\r
+#define DDR14_D7 ddr14.bit._D7\r
+#define DDR14_D6 ddr14.bit._D6\r
+#define DDR14_D5 ddr14.bit._D5\r
+#define DDR14_D4 ddr14.bit._D4\r
+#define DDR14_D3 ddr14.bit._D3\r
+#define DDR14_D2 ddr14.bit._D2\r
+#define DDR14_D1 ddr14.bit._D1\r
+#define DDR14_D0 ddr14.bit._D0\r
+__IO_EXTERN DDR15STR ddr15; \r
+#define DDR15 ddr15.byte\r
+#define DDR15_D7 ddr15.bit._D7\r
+#define DDR15_D6 ddr15.bit._D6\r
+#define DDR15_D5 ddr15.bit._D5\r
+#define DDR15_D4 ddr15.bit._D4\r
+#define DDR15_D3 ddr15.bit._D3\r
+#define DDR15_D2 ddr15.bit._D2\r
+#define DDR15_D1 ddr15.bit._D1\r
+#define DDR15_D0 ddr15.bit._D0\r
+__IO_EXTERN DDR16STR ddr16; \r
+#define DDR16 ddr16.byte\r
+#define DDR16_D7 ddr16.bit._D7\r
+#define DDR16_D6 ddr16.bit._D6\r
+#define DDR16_D5 ddr16.bit._D5\r
+#define DDR16_D4 ddr16.bit._D4\r
+#define DDR16_D3 ddr16.bit._D3\r
+#define DDR16_D2 ddr16.bit._D2\r
+#define DDR16_D1 ddr16.bit._D1\r
+#define DDR16_D0 ddr16.bit._D0\r
+__IO_EXTERN DDR17STR ddr17; \r
+#define DDR17 ddr17.byte\r
+#define DDR17_D7 ddr17.bit._D7\r
+#define DDR17_D6 ddr17.bit._D6\r
+#define DDR17_D5 ddr17.bit._D5\r
+#define DDR17_D4 ddr17.bit._D4\r
+#define DDR17_D3 ddr17.bit._D3\r
+#define DDR17_D2 ddr17.bit._D2\r
+#define DDR17_D1 ddr17.bit._D1\r
+#define DDR17_D0 ddr17.bit._D0\r
+__IO_EXTERN DDR18STR ddr18; \r
+#define DDR18 ddr18.byte\r
+#define DDR18_D6 ddr18.bit._D6\r
+#define DDR18_D2 ddr18.bit._D2\r
+__IO_EXTERN DDR19STR ddr19; \r
+#define DDR19 ddr19.byte\r
+#define DDR19_D6 ddr19.bit._D6\r
+#define DDR19_D2 ddr19.bit._D2\r
+#define DDR19_D1 ddr19.bit._D1\r
+#define DDR19_D0 ddr19.bit._D0\r
+__IO_EXTERN DDR20STR ddr20; \r
+#define DDR20 ddr20.byte\r
+#define DDR20_D7 ddr20.bit._D7\r
+#define DDR20_D6 ddr20.bit._D6\r
+#define DDR20_D5 ddr20.bit._D5\r
+#define DDR20_D4 ddr20.bit._D4\r
+#define DDR20_D3 ddr20.bit._D3\r
+#define DDR20_D2 ddr20.bit._D2\r
+#define DDR20_D1 ddr20.bit._D1\r
+#define DDR20_D0 ddr20.bit._D0\r
+__IO_EXTERN DDR21STR ddr21; \r
+#define DDR21 ddr21.byte\r
+#define DDR21_D7 ddr21.bit._D7\r
+#define DDR21_D6 ddr21.bit._D6\r
+#define DDR21_D5 ddr21.bit._D5\r
+#define DDR21_D4 ddr21.bit._D4\r
+#define DDR21_D3 ddr21.bit._D3\r
+#define DDR21_D2 ddr21.bit._D2\r
+#define DDR21_D1 ddr21.bit._D1\r
+#define DDR21_D0 ddr21.bit._D0\r
+__IO_EXTERN DDR22STR ddr22; \r
+#define DDR22 ddr22.byte\r
+#define DDR22_D5 ddr22.bit._D5\r
+#define DDR22_D4 ddr22.bit._D4\r
+#define DDR22_D1 ddr22.bit._D1\r
+#define DDR22_D0 ddr22.bit._D0\r
+__IO_EXTERN DDR24STR ddr24; \r
+#define DDR24 ddr24.byte\r
+#define DDR24_D7 ddr24.bit._D7\r
+#define DDR24_D6 ddr24.bit._D6\r
+#define DDR24_D5 ddr24.bit._D5\r
+#define DDR24_D4 ddr24.bit._D4\r
+#define DDR24_D3 ddr24.bit._D3\r
+#define DDR24_D2 ddr24.bit._D2\r
+#define DDR24_D1 ddr24.bit._D1\r
+#define DDR24_D0 ddr24.bit._D0\r
+__IO_EXTERN DDR26STR ddr26; \r
+#define DDR26 ddr26.byte\r
+#define DDR26_D1 ddr26.bit._D1\r
+#define DDR26_D0 ddr26.bit._D0\r
+__IO_EXTERN DDR27STR ddr27; \r
+#define DDR27 ddr27.byte\r
+#define DDR27_D7 ddr27.bit._D7\r
+#define DDR27_D6 ddr27.bit._D6\r
+#define DDR27_D5 ddr27.bit._D5\r
+#define DDR27_D4 ddr27.bit._D4\r
+#define DDR27_D3 ddr27.bit._D3\r
+#define DDR27_D2 ddr27.bit._D2\r
+#define DDR27_D1 ddr27.bit._D1\r
+#define DDR27_D0 ddr27.bit._D0\r
+__IO_EXTERN DDR28STR ddr28; \r
+#define DDR28 ddr28.byte\r
+#define DDR28_D7 ddr28.bit._D7\r
+#define DDR28_D6 ddr28.bit._D6\r
+#define DDR28_D5 ddr28.bit._D5\r
+#define DDR28_D4 ddr28.bit._D4\r
+#define DDR28_D3 ddr28.bit._D3\r
+#define DDR28_D2 ddr28.bit._D2\r
+#define DDR28_D1 ddr28.bit._D1\r
+#define DDR28_D0 ddr28.bit._D0\r
+__IO_EXTERN DDR29STR ddr29; \r
+#define DDR29 ddr29.byte\r
+#define DDR29_D7 ddr29.bit._D7\r
+#define DDR29_D6 ddr29.bit._D6\r
+#define DDR29_D5 ddr29.bit._D5\r
+#define DDR29_D4 ddr29.bit._D4\r
+#define DDR29_D3 ddr29.bit._D3\r
+#define DDR29_D2 ddr29.bit._D2\r
+#define DDR29_D1 ddr29.bit._D1\r
+#define DDR29_D0 ddr29.bit._D0\r
+__IO_EXTERN PFR14STR pfr14; /* R-bus Port Function Register */\r
+#define PFR14 pfr14.byte\r
+#define PFR14_D7 pfr14.bit._D7\r
+#define PFR14_D6 pfr14.bit._D6\r
+#define PFR14_D5 pfr14.bit._D5\r
+#define PFR14_D4 pfr14.bit._D4\r
+#define PFR14_D3 pfr14.bit._D3\r
+#define PFR14_D2 pfr14.bit._D2\r
+#define PFR14_D1 pfr14.bit._D1\r
+#define PFR14_D0 pfr14.bit._D0\r
+__IO_EXTERN PFR15STR pfr15; \r
+#define PFR15 pfr15.byte\r
+#define PFR15_D7 pfr15.bit._D7\r
+#define PFR15_D6 pfr15.bit._D6\r
+#define PFR15_D5 pfr15.bit._D5\r
+#define PFR15_D4 pfr15.bit._D4\r
+#define PFR15_D3 pfr15.bit._D3\r
+#define PFR15_D2 pfr15.bit._D2\r
+#define PFR15_D1 pfr15.bit._D1\r
+#define PFR15_D0 pfr15.bit._D0\r
+__IO_EXTERN PFR16STR pfr16; \r
+#define PFR16 pfr16.byte\r
+#define PFR16_D7 pfr16.bit._D7\r
+#define PFR16_D6 pfr16.bit._D6\r
+#define PFR16_D5 pfr16.bit._D5\r
+#define PFR16_D4 pfr16.bit._D4\r
+#define PFR16_D3 pfr16.bit._D3\r
+#define PFR16_D2 pfr16.bit._D2\r
+#define PFR16_D1 pfr16.bit._D1\r
+#define PFR16_D0 pfr16.bit._D0\r
+__IO_EXTERN PFR17STR pfr17; \r
+#define PFR17 pfr17.byte\r
+#define PFR17_D7 pfr17.bit._D7\r
+#define PFR17_D6 pfr17.bit._D6\r
+#define PFR17_D5 pfr17.bit._D5\r
+#define PFR17_D4 pfr17.bit._D4\r
+#define PFR17_D3 pfr17.bit._D3\r
+#define PFR17_D2 pfr17.bit._D2\r
+#define PFR17_D1 pfr17.bit._D1\r
+#define PFR17_D0 pfr17.bit._D0\r
+__IO_EXTERN PFR18STR pfr18; \r
+#define PFR18 pfr18.byte\r
+#define PFR18_D6 pfr18.bit._D6\r
+#define PFR18_D2 pfr18.bit._D2\r
+__IO_EXTERN PFR19STR pfr19; \r
+#define PFR19 pfr19.byte\r
+#define PFR19_D6 pfr19.bit._D6\r
+#define PFR19_D2 pfr19.bit._D2\r
+#define PFR19_D1 pfr19.bit._D1\r
+#define PFR19_D0 pfr19.bit._D0\r
+__IO_EXTERN PFR20STR pfr20; \r
+#define PFR20 pfr20.byte\r
+#define PFR20_D7 pfr20.bit._D7\r
+#define PFR20_D6 pfr20.bit._D6\r
+#define PFR20_D5 pfr20.bit._D5\r
+#define PFR20_D4 pfr20.bit._D4\r
+#define PFR20_D3 pfr20.bit._D3\r
+#define PFR20_D2 pfr20.bit._D2\r
+#define PFR20_D1 pfr20.bit._D1\r
+#define PFR20_D0 pfr20.bit._D0\r
+__IO_EXTERN PFR21STR pfr21; \r
+#define PFR21 pfr21.byte\r
+#define PFR21_D7 pfr21.bit._D7\r
+#define PFR21_D6 pfr21.bit._D6\r
+#define PFR21_D5 pfr21.bit._D5\r
+#define PFR21_D4 pfr21.bit._D4\r
+#define PFR21_D3 pfr21.bit._D3\r
+#define PFR21_D2 pfr21.bit._D2\r
+#define PFR21_D1 pfr21.bit._D1\r
+#define PFR21_D0 pfr21.bit._D0\r
+__IO_EXTERN PFR22STR pfr22; \r
+#define PFR22 pfr22.byte\r
+#define PFR22_D5 pfr22.bit._D5\r
+#define PFR22_D4 pfr22.bit._D4\r
+#define PFR22_D1 pfr22.bit._D1\r
+#define PFR22_D0 pfr22.bit._D0\r
+__IO_EXTERN PFR24STR pfr24; \r
+#define PFR24 pfr24.byte\r
+#define PFR24_D7 pfr24.bit._D7\r
+#define PFR24_D6 pfr24.bit._D6\r
+#define PFR24_D5 pfr24.bit._D5\r
+#define PFR24_D4 pfr24.bit._D4\r
+#define PFR24_D3 pfr24.bit._D3\r
+#define PFR24_D2 pfr24.bit._D2\r
+#define PFR24_D1 pfr24.bit._D1\r
+#define PFR24_D0 pfr24.bit._D0\r
+__IO_EXTERN PFR26STR pfr26; \r
+#define PFR26 pfr26.byte\r
+#define PFR26_D1 pfr26.bit._D1\r
+#define PFR26_D0 pfr26.bit._D0\r
+__IO_EXTERN PFR27STR pfr27; \r
+#define PFR27 pfr27.byte\r
+#define PFR27_D7 pfr27.bit._D7\r
+#define PFR27_D6 pfr27.bit._D6\r
+#define PFR27_D5 pfr27.bit._D5\r
+#define PFR27_D4 pfr27.bit._D4\r
+#define PFR27_D3 pfr27.bit._D3\r
+#define PFR27_D2 pfr27.bit._D2\r
+#define PFR27_D1 pfr27.bit._D1\r
+#define PFR27_D0 pfr27.bit._D0\r
+__IO_EXTERN PFR28STR pfr28; \r
+#define PFR28 pfr28.byte\r
+#define PFR28_D7 pfr28.bit._D7\r
+#define PFR28_D6 pfr28.bit._D6\r
+#define PFR28_D5 pfr28.bit._D5\r
+#define PFR28_D4 pfr28.bit._D4\r
+#define PFR28_D3 pfr28.bit._D3\r
+#define PFR28_D2 pfr28.bit._D2\r
+#define PFR28_D1 pfr28.bit._D1\r
+#define PFR28_D0 pfr28.bit._D0\r
+__IO_EXTERN PFR29STR pfr29; \r
+#define PFR29 pfr29.byte\r
+#define PFR29_D7 pfr29.bit._D7\r
+#define PFR29_D6 pfr29.bit._D6\r
+#define PFR29_D5 pfr29.bit._D5\r
+#define PFR29_D4 pfr29.bit._D4\r
+#define PFR29_D3 pfr29.bit._D3\r
+#define PFR29_D2 pfr29.bit._D2\r
+#define PFR29_D1 pfr29.bit._D1\r
+#define PFR29_D0 pfr29.bit._D0\r
+__IO_EXTERN EPFR14STR epfr14; /* R-bus Port Extra Function Register */\r
+#define EPFR14 epfr14.byte\r
+#define EPFR14_D7 epfr14.bit._D7\r
+#define EPFR14_D6 epfr14.bit._D6\r
+#define EPFR14_D5 epfr14.bit._D5\r
+#define EPFR14_D4 epfr14.bit._D4\r
+#define EPFR14_D3 epfr14.bit._D3\r
+#define EPFR14_D2 epfr14.bit._D2\r
+#define EPFR14_D1 epfr14.bit._D1\r
+#define EPFR14_D0 epfr14.bit._D0\r
+__IO_EXTERN EPFR15STR epfr15; \r
+#define EPFR15 epfr15.byte\r
+#define EPFR15_D7 epfr15.bit._D7\r
+#define EPFR15_D6 epfr15.bit._D6\r
+#define EPFR15_D5 epfr15.bit._D5\r
+#define EPFR15_D4 epfr15.bit._D4\r
+#define EPFR15_D3 epfr15.bit._D3\r
+#define EPFR15_D2 epfr15.bit._D2\r
+#define EPFR15_D1 epfr15.bit._D1\r
+#define EPFR15_D0 epfr15.bit._D0\r
+__IO_EXTERN EPFR16STR epfr16; \r
+#define EPFR16 epfr16.byte\r
+#define EPFR16_D7 epfr16.bit._D7\r
+__IO_EXTERN IO_BYTE epfr17; \r
+#define EPFR17 epfr17\r
+__IO_EXTERN EPFR18STR epfr18; \r
+#define EPFR18 epfr18.byte\r
+#define EPFR18_D6 epfr18.bit._D6\r
+#define EPFR18_D2 epfr18.bit._D2\r
+__IO_EXTERN EPFR19STR epfr19; \r
+#define EPFR19 epfr19.byte\r
+#define EPFR19_D6 epfr19.bit._D6\r
+#define EPFR19_D2 epfr19.bit._D2\r
+__IO_EXTERN EPFR20STR epfr20; \r
+#define EPFR20 epfr20.byte\r
+#define EPFR20_D6 epfr20.bit._D6\r
+#define EPFR20_D2 epfr20.bit._D2\r
+__IO_EXTERN EPFR21STR epfr21; \r
+#define EPFR21 epfr21.byte\r
+#define EPFR21_D6 epfr21.bit._D6\r
+#define EPFR21_D2 epfr21.bit._D2\r
+__IO_EXTERN IO_BYTE epfr22; \r
+#define EPFR22 epfr22\r
+__IO_EXTERN IO_BYTE epfr24; \r
+#define EPFR24 epfr24\r
+__IO_EXTERN EPFR26STR epfr26; \r
+#define EPFR26 epfr26.byte\r
+#define EPFR26_D1 epfr26.bit._D1\r
+#define EPFR26_D0 epfr26.bit._D0\r
+__IO_EXTERN EPFR27STR epfr27; \r
+#define EPFR27 epfr27.byte\r
+#define EPFR27_D7 epfr27.bit._D7\r
+#define EPFR27_D6 epfr27.bit._D6\r
+#define EPFR27_D5 epfr27.bit._D5\r
+#define EPFR27_D4 epfr27.bit._D4\r
+#define EPFR27_D3 epfr27.bit._D3\r
+#define EPFR27_D2 epfr27.bit._D2\r
+#define EPFR27_D1 epfr27.bit._D1\r
+#define EPFR27_D0 epfr27.bit._D0\r
+__IO_EXTERN IO_BYTE epfr29; \r
+#define EPFR29 epfr29\r
+__IO_EXTERN PODR14STR podr14; /* R-bus Port Output Drive Select Register */\r
+#define PODR14 podr14.byte\r
+#define PODR14_D7 podr14.bit._D7\r
+#define PODR14_D6 podr14.bit._D6\r
+#define PODR14_D5 podr14.bit._D5\r
+#define PODR14_D4 podr14.bit._D4\r
+#define PODR14_D3 podr14.bit._D3\r
+#define PODR14_D2 podr14.bit._D2\r
+#define PODR14_D1 podr14.bit._D1\r
+#define PODR14_D0 podr14.bit._D0\r
+__IO_EXTERN PODR15STR podr15; \r
+#define PODR15 podr15.byte\r
+#define PODR15_D7 podr15.bit._D7\r
+#define PODR15_D6 podr15.bit._D6\r
+#define PODR15_D5 podr15.bit._D5\r
+#define PODR15_D4 podr15.bit._D4\r
+#define PODR15_D3 podr15.bit._D3\r
+#define PODR15_D2 podr15.bit._D2\r
+#define PODR15_D1 podr15.bit._D1\r
+#define PODR15_D0 podr15.bit._D0\r
+__IO_EXTERN PODR16STR podr16; \r
+#define PODR16 podr16.byte\r
+#define PODR16_D7 podr16.bit._D7\r
+#define PODR16_D6 podr16.bit._D6\r
+#define PODR16_D5 podr16.bit._D5\r
+#define PODR16_D4 podr16.bit._D4\r
+#define PODR16_D3 podr16.bit._D3\r
+#define PODR16_D2 podr16.bit._D2\r
+#define PODR16_D1 podr16.bit._D1\r
+#define PODR16_D0 podr16.bit._D0\r
+__IO_EXTERN PODR17STR podr17; \r
+#define PODR17 podr17.byte\r
+#define PODR17_D7 podr17.bit._D7\r
+#define PODR17_D6 podr17.bit._D6\r
+#define PODR17_D5 podr17.bit._D5\r
+#define PODR17_D4 podr17.bit._D4\r
+#define PODR17_D3 podr17.bit._D3\r
+#define PODR17_D2 podr17.bit._D2\r
+#define PODR17_D1 podr17.bit._D1\r
+#define PODR17_D0 podr17.bit._D0\r
+__IO_EXTERN PODR18STR podr18; \r
+#define PODR18 podr18.byte\r
+#define PODR18_D6 podr18.bit._D6\r
+#define PODR18_D2 podr18.bit._D2\r
+__IO_EXTERN PODR19STR podr19; \r
+#define PODR19 podr19.byte\r
+#define PODR19_D6 podr19.bit._D6\r
+#define PODR19_D2 podr19.bit._D2\r
+#define PODR19_D1 podr19.bit._D1\r
+#define PODR19_D0 podr19.bit._D0\r
+__IO_EXTERN PODR20STR podr20; \r
+#define PODR20 podr20.byte\r
+#define PODR20_D7 podr20.bit._D7\r
+#define PODR20_D6 podr20.bit._D6\r
+#define PODR20_D5 podr20.bit._D5\r
+#define PODR20_D4 podr20.bit._D4\r
+#define PODR20_D3 podr20.bit._D3\r
+#define PODR20_D2 podr20.bit._D2\r
+#define PODR20_D1 podr20.bit._D1\r
+#define PODR20_D0 podr20.bit._D0\r
+__IO_EXTERN PODR21STR podr21; \r
+#define PODR21 podr21.byte\r
+#define PODR21_D7 podr21.bit._D7\r
+#define PODR21_D6 podr21.bit._D6\r
+#define PODR21_D5 podr21.bit._D5\r
+#define PODR21_D4 podr21.bit._D4\r
+#define PODR21_D3 podr21.bit._D3\r
+#define PODR21_D2 podr21.bit._D2\r
+#define PODR21_D1 podr21.bit._D1\r
+#define PODR21_D0 podr21.bit._D0\r
+__IO_EXTERN PODR22STR podr22; \r
+#define PODR22 podr22.byte\r
+#define PODR22_D5 podr22.bit._D5\r
+#define PODR22_D4 podr22.bit._D4\r
+#define PODR22_D1 podr22.bit._D1\r
+#define PODR22_D0 podr22.bit._D0\r
+__IO_EXTERN PODR24STR podr24; \r
+#define PODR24 podr24.byte\r
+#define PODR24_D7 podr24.bit._D7\r
+#define PODR24_D6 podr24.bit._D6\r
+#define PODR24_D5 podr24.bit._D5\r
+#define PODR24_D4 podr24.bit._D4\r
+#define PODR24_D3 podr24.bit._D3\r
+#define PODR24_D2 podr24.bit._D2\r
+#define PODR24_D1 podr24.bit._D1\r
+#define PODR24_D0 podr24.bit._D0\r
+__IO_EXTERN PODR26STR podr26; \r
+#define PODR26 podr26.byte\r
+#define PODR26_D1 podr26.bit._D1\r
+#define PODR26_D0 podr26.bit._D0\r
+__IO_EXTERN PODR27STR podr27; \r
+#define PODR27 podr27.byte\r
+#define PODR27_D7 podr27.bit._D7\r
+#define PODR27_D6 podr27.bit._D6\r
+#define PODR27_D5 podr27.bit._D5\r
+#define PODR27_D4 podr27.bit._D4\r
+#define PODR27_D3 podr27.bit._D3\r
+#define PODR27_D2 podr27.bit._D2\r
+#define PODR27_D1 podr27.bit._D1\r
+#define PODR27_D0 podr27.bit._D0\r
+__IO_EXTERN PODR28STR podr28; \r
+#define PODR28 podr28.byte\r
+#define PODR28_D7 podr28.bit._D7\r
+#define PODR28_D6 podr28.bit._D6\r
+#define PODR28_D5 podr28.bit._D5\r
+#define PODR28_D4 podr28.bit._D4\r
+#define PODR28_D3 podr28.bit._D3\r
+#define PODR28_D2 podr28.bit._D2\r
+#define PODR28_D1 podr28.bit._D1\r
+#define PODR28_D0 podr28.bit._D0\r
+__IO_EXTERN PODR29STR podr29; \r
+#define PODR29 podr29.byte\r
+#define PODR29_D7 podr29.bit._D7\r
+#define PODR29_D6 podr29.bit._D6\r
+#define PODR29_D5 podr29.bit._D5\r
+#define PODR29_D4 podr29.bit._D4\r
+#define PODR29_D3 podr29.bit._D3\r
+#define PODR29_D2 podr29.bit._D2\r
+#define PODR29_D1 podr29.bit._D1\r
+#define PODR29_D0 podr29.bit._D0\r
+__IO_EXTERN PILR14STR pilr14; /* R-bus Port Input Level Select Register */\r
+#define PILR14 pilr14.byte\r
+#define PILR14_D7 pilr14.bit._D7\r
+#define PILR14_D6 pilr14.bit._D6\r
+#define PILR14_D5 pilr14.bit._D5\r
+#define PILR14_D4 pilr14.bit._D4\r
+#define PILR14_D3 pilr14.bit._D3\r
+#define PILR14_D2 pilr14.bit._D2\r
+#define PILR14_D1 pilr14.bit._D1\r
+#define PILR14_D0 pilr14.bit._D0\r
+__IO_EXTERN PILR15STR pilr15; \r
+#define PILR15 pilr15.byte\r
+#define PILR15_D7 pilr15.bit._D7\r
+#define PILR15_D6 pilr15.bit._D6\r
+#define PILR15_D5 pilr15.bit._D5\r
+#define PILR15_D4 pilr15.bit._D4\r
+#define PILR15_D3 pilr15.bit._D3\r
+#define PILR15_D2 pilr15.bit._D2\r
+#define PILR15_D1 pilr15.bit._D1\r
+#define PILR15_D0 pilr15.bit._D0\r
+__IO_EXTERN PILR16STR pilr16; \r
+#define PILR16 pilr16.byte\r
+#define PILR16_D7 pilr16.bit._D7\r
+#define PILR16_D6 pilr16.bit._D6\r
+#define PILR16_D5 pilr16.bit._D5\r
+#define PILR16_D4 pilr16.bit._D4\r
+#define PILR16_D3 pilr16.bit._D3\r
+#define PILR16_D2 pilr16.bit._D2\r
+#define PILR16_D1 pilr16.bit._D1\r
+#define PILR16_D0 pilr16.bit._D0\r
+__IO_EXTERN PILR17STR pilr17; \r
+#define PILR17 pilr17.byte\r
+#define PILR17_D7 pilr17.bit._D7\r
+#define PILR17_D6 pilr17.bit._D6\r
+#define PILR17_D5 pilr17.bit._D5\r
+#define PILR17_D4 pilr17.bit._D4\r
+#define PILR17_D3 pilr17.bit._D3\r
+#define PILR17_D2 pilr17.bit._D2\r
+#define PILR17_D1 pilr17.bit._D1\r
+#define PILR17_D0 pilr17.bit._D0\r
+__IO_EXTERN PILR18STR pilr18; \r
+#define PILR18 pilr18.byte\r
+#define PILR18_D6 pilr18.bit._D6\r
+#define PILR18_D2 pilr18.bit._D2\r
+__IO_EXTERN PILR19STR pilr19; \r
+#define PILR19 pilr19.byte\r
+#define PILR19_D6 pilr19.bit._D6\r
+#define PILR19_D2 pilr19.bit._D2\r
+#define PILR19_D1 pilr19.bit._D1\r
+#define PILR19_D0 pilr19.bit._D0\r
+__IO_EXTERN PILR20STR pilr20; \r
+#define PILR20 pilr20.byte\r
+#define PILR20_D7 pilr20.bit._D7\r
+#define PILR20_D6 pilr20.bit._D6\r
+#define PILR20_D5 pilr20.bit._D5\r
+#define PILR20_D4 pilr20.bit._D4\r
+#define PILR20_D3 pilr20.bit._D3\r
+#define PILR20_D2 pilr20.bit._D2\r
+#define PILR20_D1 pilr20.bit._D1\r
+#define PILR20_D0 pilr20.bit._D0\r
+__IO_EXTERN PILR21STR pilr21; \r
+#define PILR21 pilr21.byte\r
+#define PILR21_D7 pilr21.bit._D7\r
+#define PILR21_D6 pilr21.bit._D6\r
+#define PILR21_D5 pilr21.bit._D5\r
+#define PILR21_D4 pilr21.bit._D4\r
+#define PILR21_D3 pilr21.bit._D3\r
+#define PILR21_D2 pilr21.bit._D2\r
+#define PILR21_D1 pilr21.bit._D1\r
+#define PILR21_D0 pilr21.bit._D0\r
+__IO_EXTERN PILR22STR pilr22; \r
+#define PILR22 pilr22.byte\r
+#define PILR22_D5 pilr22.bit._D5\r
+#define PILR22_D4 pilr22.bit._D4\r
+#define PILR22_D1 pilr22.bit._D1\r
+#define PILR22_D0 pilr22.bit._D0\r
+__IO_EXTERN PILR24STR pilr24; \r
+#define PILR24 pilr24.byte\r
+#define PILR24_D7 pilr24.bit._D7\r
+#define PILR24_D6 pilr24.bit._D6\r
+#define PILR24_D5 pilr24.bit._D5\r
+#define PILR24_D4 pilr24.bit._D4\r
+#define PILR24_D3 pilr24.bit._D3\r
+#define PILR24_D2 pilr24.bit._D2\r
+#define PILR24_D1 pilr24.bit._D1\r
+#define PILR24_D0 pilr24.bit._D0\r
+__IO_EXTERN PILR26STR pilr26; \r
+#define PILR26 pilr26.byte\r
+#define PILR26_D1 pilr26.bit._D1\r
+#define PILR26_D0 pilr26.bit._D0\r
+__IO_EXTERN PILR27STR pilr27; \r
+#define PILR27 pilr27.byte\r
+#define PILR27_D7 pilr27.bit._D7\r
+#define PILR27_D6 pilr27.bit._D6\r
+#define PILR27_D5 pilr27.bit._D5\r
+#define PILR27_D4 pilr27.bit._D4\r
+#define PILR27_D3 pilr27.bit._D3\r
+#define PILR27_D2 pilr27.bit._D2\r
+#define PILR27_D1 pilr27.bit._D1\r
+#define PILR27_D0 pilr27.bit._D0\r
+__IO_EXTERN PILR28STR pilr28; \r
+#define PILR28 pilr28.byte\r
+#define PILR28_D7 pilr28.bit._D7\r
+#define PILR28_D6 pilr28.bit._D6\r
+#define PILR28_D5 pilr28.bit._D5\r
+#define PILR28_D4 pilr28.bit._D4\r
+#define PILR28_D3 pilr28.bit._D3\r
+#define PILR28_D2 pilr28.bit._D2\r
+#define PILR28_D1 pilr28.bit._D1\r
+#define PILR28_D0 pilr28.bit._D0\r
+__IO_EXTERN PILR29STR pilr29; \r
+#define PILR29 pilr29.byte\r
+#define PILR29_D7 pilr29.bit._D7\r
+#define PILR29_D6 pilr29.bit._D6\r
+#define PILR29_D5 pilr29.bit._D5\r
+#define PILR29_D4 pilr29.bit._D4\r
+#define PILR29_D3 pilr29.bit._D3\r
+#define PILR29_D2 pilr29.bit._D2\r
+#define PILR29_D1 pilr29.bit._D1\r
+#define PILR29_D0 pilr29.bit._D0\r
+__IO_EXTERN EPILR14STR epilr14; /* R-bus Port Extra Input Level Select Register */\r
+#define EPILR14 epilr14.byte\r
+#define EPILR14_D7 epilr14.bit._D7\r
+#define EPILR14_D6 epilr14.bit._D6\r
+#define EPILR14_D5 epilr14.bit._D5\r
+#define EPILR14_D4 epilr14.bit._D4\r
+#define EPILR14_D3 epilr14.bit._D3\r
+#define EPILR14_D2 epilr14.bit._D2\r
+#define EPILR14_D1 epilr14.bit._D1\r
+#define EPILR14_D0 epilr14.bit._D0\r
+__IO_EXTERN EPILR15STR epilr15; \r
+#define EPILR15 epilr15.byte\r
+#define EPILR15_D7 epilr15.bit._D7\r
+#define EPILR15_D6 epilr15.bit._D6\r
+#define EPILR15_D5 epilr15.bit._D5\r
+#define EPILR15_D4 epilr15.bit._D4\r
+#define EPILR15_D3 epilr15.bit._D3\r
+#define EPILR15_D2 epilr15.bit._D2\r
+#define EPILR15_D1 epilr15.bit._D1\r
+#define EPILR15_D0 epilr15.bit._D0\r
+__IO_EXTERN EPILR16STR epilr16; \r
+#define EPILR16 epilr16.byte\r
+#define EPILR16_D7 epilr16.bit._D7\r
+#define EPILR16_D6 epilr16.bit._D6\r
+#define EPILR16_D5 epilr16.bit._D5\r
+#define EPILR16_D4 epilr16.bit._D4\r
+#define EPILR16_D3 epilr16.bit._D3\r
+#define EPILR16_D2 epilr16.bit._D2\r
+#define EPILR16_D1 epilr16.bit._D1\r
+#define EPILR16_D0 epilr16.bit._D0\r
+__IO_EXTERN EPILR17STR epilr17; \r
+#define EPILR17 epilr17.byte\r
+#define EPILR17_D7 epilr17.bit._D7\r
+#define EPILR17_D6 epilr17.bit._D6\r
+#define EPILR17_D5 epilr17.bit._D5\r
+#define EPILR17_D4 epilr17.bit._D4\r
+#define EPILR17_D3 epilr17.bit._D3\r
+#define EPILR17_D2 epilr17.bit._D2\r
+#define EPILR17_D1 epilr17.bit._D1\r
+#define EPILR17_D0 epilr17.bit._D0\r
+__IO_EXTERN EPILR18STR epilr18; \r
+#define EPILR18 epilr18.byte\r
+#define EPILR18_D6 epilr18.bit._D6\r
+#define EPILR18_D2 epilr18.bit._D2\r
+__IO_EXTERN EPILR19STR epilr19; \r
+#define EPILR19 epilr19.byte\r
+#define EPILR19_D6 epilr19.bit._D6\r
+#define EPILR19_D2 epilr19.bit._D2\r
+#define EPILR19_D1 epilr19.bit._D1\r
+#define EPILR19_D0 epilr19.bit._D0\r
+__IO_EXTERN EPILR20STR epilr20; \r
+#define EPILR20 epilr20.byte\r
+#define EPILR20_D7 epilr20.bit._D7\r
+#define EPILR20_D6 epilr20.bit._D6\r
+#define EPILR20_D5 epilr20.bit._D5\r
+#define EPILR20_D4 epilr20.bit._D4\r
+#define EPILR20_D3 epilr20.bit._D3\r
+#define EPILR20_D2 epilr20.bit._D2\r
+#define EPILR20_D1 epilr20.bit._D1\r
+#define EPILR20_D0 epilr20.bit._D0\r
+__IO_EXTERN EPILR21STR epilr21; \r
+#define EPILR21 epilr21.byte\r
+#define EPILR21_D7 epilr21.bit._D7\r
+#define EPILR21_D6 epilr21.bit._D6\r
+#define EPILR21_D5 epilr21.bit._D5\r
+#define EPILR21_D4 epilr21.bit._D4\r
+#define EPILR21_D3 epilr21.bit._D3\r
+#define EPILR21_D2 epilr21.bit._D2\r
+#define EPILR21_D1 epilr21.bit._D1\r
+#define EPILR21_D0 epilr21.bit._D0\r
+__IO_EXTERN EPILR22STR epilr22; \r
+#define EPILR22 epilr22.byte\r
+#define EPILR22_D5 epilr22.bit._D5\r
+#define EPILR22_D4 epilr22.bit._D4\r
+#define EPILR22_D1 epilr22.bit._D1\r
+#define EPILR22_D0 epilr22.bit._D0\r
+__IO_EXTERN EPILR24STR epilr24; \r
+#define EPILR24 epilr24.byte\r
+#define EPILR24_D7 epilr24.bit._D7\r
+#define EPILR24_D6 epilr24.bit._D6\r
+#define EPILR24_D5 epilr24.bit._D5\r
+#define EPILR24_D4 epilr24.bit._D4\r
+#define EPILR24_D3 epilr24.bit._D3\r
+#define EPILR24_D2 epilr24.bit._D2\r
+#define EPILR24_D1 epilr24.bit._D1\r
+#define EPILR24_D0 epilr24.bit._D0\r
+__IO_EXTERN EPILR26STR epilr26; \r
+#define EPILR26 epilr26.byte\r
+#define EPILR26_D1 epilr26.bit._D1\r
+#define EPILR26_D0 epilr26.bit._D0\r
+__IO_EXTERN EPILR27STR epilr27; \r
+#define EPILR27 epilr27.byte\r
+#define EPILR27_D7 epilr27.bit._D7\r
+#define EPILR27_D6 epilr27.bit._D6\r
+#define EPILR27_D5 epilr27.bit._D5\r
+#define EPILR27_D4 epilr27.bit._D4\r
+#define EPILR27_D3 epilr27.bit._D3\r
+#define EPILR27_D2 epilr27.bit._D2\r
+#define EPILR27_D1 epilr27.bit._D1\r
+#define EPILR27_D0 epilr27.bit._D0\r
+__IO_EXTERN EPILR28STR epilr28; \r
+#define EPILR28 epilr28.byte\r
+#define EPILR28_D7 epilr28.bit._D7\r
+#define EPILR28_D6 epilr28.bit._D6\r
+#define EPILR28_D5 epilr28.bit._D5\r
+#define EPILR28_D4 epilr28.bit._D4\r
+#define EPILR28_D3 epilr28.bit._D3\r
+#define EPILR28_D2 epilr28.bit._D2\r
+#define EPILR28_D1 epilr28.bit._D1\r
+#define EPILR28_D0 epilr28.bit._D0\r
+__IO_EXTERN EPILR29STR epilr29; \r
+#define EPILR29 epilr29.byte\r
+#define EPILR29_D7 epilr29.bit._D7\r
+#define EPILR29_D6 epilr29.bit._D6\r
+#define EPILR29_D5 epilr29.bit._D5\r
+#define EPILR29_D4 epilr29.bit._D4\r
+#define EPILR29_D3 epilr29.bit._D3\r
+#define EPILR29_D2 epilr29.bit._D2\r
+#define EPILR29_D1 epilr29.bit._D1\r
+#define EPILR29_D0 epilr29.bit._D0\r
+__IO_EXTERN PPER14STR pper14; /* R-bus Port Pull-Up/Down Enable Register */\r
+#define PPER14 pper14.byte\r
+#define PPER14_D7 pper14.bit._D7\r
+#define PPER14_D6 pper14.bit._D6\r
+#define PPER14_D5 pper14.bit._D5\r
+#define PPER14_D4 pper14.bit._D4\r
+#define PPER14_D3 pper14.bit._D3\r
+#define PPER14_D2 pper14.bit._D2\r
+#define PPER14_D1 pper14.bit._D1\r
+#define PPER14_D0 pper14.bit._D0\r
+__IO_EXTERN PPER15STR pper15; \r
+#define PPER15 pper15.byte\r
+#define PPER15_D7 pper15.bit._D7\r
+#define PPER15_D6 pper15.bit._D6\r
+#define PPER15_D5 pper15.bit._D5\r
+#define PPER15_D4 pper15.bit._D4\r
+#define PPER15_D3 pper15.bit._D3\r
+#define PPER15_D2 pper15.bit._D2\r
+#define PPER15_D1 pper15.bit._D1\r
+#define PPER15_D0 pper15.bit._D0\r
+__IO_EXTERN PPER16STR pper16; \r
+#define PPER16 pper16.byte\r
+#define PPER16_D7 pper16.bit._D7\r
+#define PPER16_D6 pper16.bit._D6\r
+#define PPER16_D5 pper16.bit._D5\r
+#define PPER16_D4 pper16.bit._D4\r
+#define PPER16_D3 pper16.bit._D3\r
+#define PPER16_D2 pper16.bit._D2\r
+#define PPER16_D1 pper16.bit._D1\r
+#define PPER16_D0 pper16.bit._D0\r
+__IO_EXTERN PPER17STR pper17; \r
+#define PPER17 pper17.byte\r
+#define PPER17_D7 pper17.bit._D7\r
+#define PPER17_D6 pper17.bit._D6\r
+#define PPER17_D5 pper17.bit._D5\r
+#define PPER17_D4 pper17.bit._D4\r
+#define PPER17_D3 pper17.bit._D3\r
+#define PPER17_D2 pper17.bit._D2\r
+#define PPER17_D1 pper17.bit._D1\r
+#define PPER17_D0 pper17.bit._D0\r
+__IO_EXTERN PPER18STR pper18; \r
+#define PPER18 pper18.byte\r
+#define PPER18_D6 pper18.bit._D6\r
+#define PPER18_D2 pper18.bit._D2\r
+__IO_EXTERN PPER19STR pper19; \r
+#define PPER19 pper19.byte\r
+#define PPER19_D6 pper19.bit._D6\r
+#define PPER19_D2 pper19.bit._D2\r
+#define PPER19_D1 pper19.bit._D1\r
+#define PPER19_D0 pper19.bit._D0\r
+__IO_EXTERN PPER20STR pper20; \r
+#define PPER20 pper20.byte\r
+#define PPER20_D7 pper20.bit._D7\r
+#define PPER20_D6 pper20.bit._D6\r
+#define PPER20_D5 pper20.bit._D5\r
+#define PPER20_D4 pper20.bit._D4\r
+#define PPER20_D3 pper20.bit._D3\r
+#define PPER20_D2 pper20.bit._D2\r
+#define PPER20_D1 pper20.bit._D1\r
+#define PPER20_D0 pper20.bit._D0\r
+__IO_EXTERN PPER21STR pper21; \r
+#define PPER21 pper21.byte\r
+#define PPER21_D7 pper21.bit._D7\r
+#define PPER21_D6 pper21.bit._D6\r
+#define PPER21_D5 pper21.bit._D5\r
+#define PPER21_D4 pper21.bit._D4\r
+#define PPER21_D3 pper21.bit._D3\r
+#define PPER21_D2 pper21.bit._D2\r
+#define PPER21_D1 pper21.bit._D1\r
+#define PPER21_D0 pper21.bit._D0\r
+__IO_EXTERN PPER22STR pper22; \r
+#define PPER22 pper22.byte\r
+#define PPER22_D5 pper22.bit._D5\r
+#define PPER22_D4 pper22.bit._D4\r
+#define PPER22_D1 pper22.bit._D1\r
+#define PPER22_D0 pper22.bit._D0\r
+__IO_EXTERN PPER24STR pper24; \r
+#define PPER24 pper24.byte\r
+#define PPER24_D7 pper24.bit._D7\r
+#define PPER24_D6 pper24.bit._D6\r
+#define PPER24_D5 pper24.bit._D5\r
+#define PPER24_D4 pper24.bit._D4\r
+#define PPER24_D3 pper24.bit._D3\r
+#define PPER24_D2 pper24.bit._D2\r
+#define PPER24_D1 pper24.bit._D1\r
+#define PPER24_D0 pper24.bit._D0\r
+__IO_EXTERN PPER26STR pper26; \r
+#define PPER26 pper26.byte\r
+#define PPER26_D1 pper26.bit._D1\r
+#define PPER26_D0 pper26.bit._D0\r
+__IO_EXTERN PPER27STR pper27; \r
+#define PPER27 pper27.byte\r
+#define PPER27_D7 pper27.bit._D7\r
+#define PPER27_D6 pper27.bit._D6\r
+#define PPER27_D5 pper27.bit._D5\r
+#define PPER27_D4 pper27.bit._D4\r
+#define PPER27_D3 pper27.bit._D3\r
+#define PPER27_D2 pper27.bit._D2\r
+#define PPER27_D1 pper27.bit._D1\r
+#define PPER27_D0 pper27.bit._D0\r
+__IO_EXTERN PPER28STR pper28; \r
+#define PPER28 pper28.byte\r
+#define PPER28_D7 pper28.bit._D7\r
+#define PPER28_D6 pper28.bit._D6\r
+#define PPER28_D5 pper28.bit._D5\r
+#define PPER28_D4 pper28.bit._D4\r
+#define PPER28_D3 pper28.bit._D3\r
+#define PPER28_D2 pper28.bit._D2\r
+#define PPER28_D1 pper28.bit._D1\r
+#define PPER28_D0 pper28.bit._D0\r
+__IO_EXTERN PPER29STR pper29; \r
+#define PPER29 pper29.byte\r
+#define PPER29_D7 pper29.bit._D7\r
+#define PPER29_D6 pper29.bit._D6\r
+#define PPER29_D5 pper29.bit._D5\r
+#define PPER29_D4 pper29.bit._D4\r
+#define PPER29_D3 pper29.bit._D3\r
+#define PPER29_D2 pper29.bit._D2\r
+#define PPER29_D1 pper29.bit._D1\r
+#define PPER29_D0 pper29.bit._D0\r
+__IO_EXTERN PPCR14STR ppcr14; /* R-bus Port Pull-Up/Down Control Register */\r
+#define PPCR14 ppcr14.byte\r
+#define PPCR14_D7 ppcr14.bit._D7\r
+#define PPCR14_D6 ppcr14.bit._D6\r
+#define PPCR14_D5 ppcr14.bit._D5\r
+#define PPCR14_D4 ppcr14.bit._D4\r
+#define PPCR14_D3 ppcr14.bit._D3\r
+#define PPCR14_D2 ppcr14.bit._D2\r
+#define PPCR14_D1 ppcr14.bit._D1\r
+#define PPCR14_D0 ppcr14.bit._D0\r
+__IO_EXTERN PPCR15STR ppcr15; \r
+#define PPCR15 ppcr15.byte\r
+#define PPCR15_D7 ppcr15.bit._D7\r
+#define PPCR15_D6 ppcr15.bit._D6\r
+#define PPCR15_D5 ppcr15.bit._D5\r
+#define PPCR15_D4 ppcr15.bit._D4\r
+#define PPCR15_D3 ppcr15.bit._D3\r
+#define PPCR15_D2 ppcr15.bit._D2\r
+#define PPCR15_D1 ppcr15.bit._D1\r
+#define PPCR15_D0 ppcr15.bit._D0\r
+__IO_EXTERN PPCR16STR ppcr16; \r
+#define PPCR16 ppcr16.byte\r
+#define PPCR16_D7 ppcr16.bit._D7\r
+#define PPCR16_D6 ppcr16.bit._D6\r
+#define PPCR16_D5 ppcr16.bit._D5\r
+#define PPCR16_D4 ppcr16.bit._D4\r
+#define PPCR16_D3 ppcr16.bit._D3\r
+#define PPCR16_D2 ppcr16.bit._D2\r
+#define PPCR16_D1 ppcr16.bit._D1\r
+#define PPCR16_D0 ppcr16.bit._D0\r
+__IO_EXTERN PPCR17STR ppcr17; \r
+#define PPCR17 ppcr17.byte\r
+#define PPCR17_D7 ppcr17.bit._D7\r
+#define PPCR17_D6 ppcr17.bit._D6\r
+#define PPCR17_D5 ppcr17.bit._D5\r
+#define PPCR17_D4 ppcr17.bit._D4\r
+#define PPCR17_D3 ppcr17.bit._D3\r
+#define PPCR17_D2 ppcr17.bit._D2\r
+#define PPCR17_D1 ppcr17.bit._D1\r
+#define PPCR17_D0 ppcr17.bit._D0\r
+__IO_EXTERN PPCR18STR ppcr18; \r
+#define PPCR18 ppcr18.byte\r
+#define PPCR18_D6 ppcr18.bit._D6\r
+#define PPCR18_D2 ppcr18.bit._D2\r
+__IO_EXTERN PPCR19STR ppcr19; \r
+#define PPCR19 ppcr19.byte\r
+#define PPCR19_D6 ppcr19.bit._D6\r
+#define PPCR19_D2 ppcr19.bit._D2\r
+#define PPCR19_D1 ppcr19.bit._D1\r
+#define PPCR19_D0 ppcr19.bit._D0\r
+__IO_EXTERN PPCR20STR ppcr20; \r
+#define PPCR20 ppcr20.byte\r
+#define PPCR20_D7 ppcr20.bit._D7\r
+#define PPCR20_D6 ppcr20.bit._D6\r
+#define PPCR20_D5 ppcr20.bit._D5\r
+#define PPCR20_D4 ppcr20.bit._D4\r
+#define PPCR20_D3 ppcr20.bit._D3\r
+#define PPCR20_D2 ppcr20.bit._D2\r
+#define PPCR20_D1 ppcr20.bit._D1\r
+#define PPCR20_D0 ppcr20.bit._D0\r
+__IO_EXTERN PPCR21STR ppcr21; \r
+#define PPCR21 ppcr21.byte\r
+#define PPCR21_D7 ppcr21.bit._D7\r
+#define PPCR21_D6 ppcr21.bit._D6\r
+#define PPCR21_D5 ppcr21.bit._D5\r
+#define PPCR21_D4 ppcr21.bit._D4\r
+#define PPCR21_D3 ppcr21.bit._D3\r
+#define PPCR21_D2 ppcr21.bit._D2\r
+#define PPCR21_D1 ppcr21.bit._D1\r
+#define PPCR21_D0 ppcr21.bit._D0\r
+__IO_EXTERN PPCR22STR ppcr22; \r
+#define PPCR22 ppcr22.byte\r
+#define PPCR22_D5 ppcr22.bit._D5\r
+#define PPCR22_D4 ppcr22.bit._D4\r
+#define PPCR22_D1 ppcr22.bit._D1\r
+#define PPCR22_D0 ppcr22.bit._D0\r
+__IO_EXTERN PPCR24STR ppcr24; \r
+#define PPCR24 ppcr24.byte\r
+#define PPCR24_D7 ppcr24.bit._D7\r
+#define PPCR24_D6 ppcr24.bit._D6\r
+#define PPCR24_D5 ppcr24.bit._D5\r
+#define PPCR24_D4 ppcr24.bit._D4\r
+#define PPCR24_D3 ppcr24.bit._D3\r
+#define PPCR24_D2 ppcr24.bit._D2\r
+#define PPCR24_D1 ppcr24.bit._D1\r
+#define PPCR24_D0 ppcr24.bit._D0\r
+__IO_EXTERN PPCR26STR ppcr26; \r
+#define PPCR26 ppcr26.byte\r
+#define PPCR26_D1 ppcr26.bit._D1\r
+#define PPCR26_D0 ppcr26.bit._D0\r
+__IO_EXTERN PPCR27STR ppcr27; \r
+#define PPCR27 ppcr27.byte\r
+#define PPCR27_D7 ppcr27.bit._D7\r
+#define PPCR27_D6 ppcr27.bit._D6\r
+#define PPCR27_D5 ppcr27.bit._D5\r
+#define PPCR27_D4 ppcr27.bit._D4\r
+#define PPCR27_D3 ppcr27.bit._D3\r
+#define PPCR27_D2 ppcr27.bit._D2\r
+#define PPCR27_D1 ppcr27.bit._D1\r
+#define PPCR27_D0 ppcr27.bit._D0\r
+__IO_EXTERN PPCR28STR ppcr28; \r
+#define PPCR28 ppcr28.byte\r
+#define PPCR28_D7 ppcr28.bit._D7\r
+#define PPCR28_D6 ppcr28.bit._D6\r
+#define PPCR28_D5 ppcr28.bit._D5\r
+#define PPCR28_D4 ppcr28.bit._D4\r
+#define PPCR28_D3 ppcr28.bit._D3\r
+#define PPCR28_D2 ppcr28.bit._D2\r
+#define PPCR28_D1 ppcr28.bit._D1\r
+#define PPCR28_D0 ppcr28.bit._D0\r
+__IO_EXTERN PPCR29STR ppcr29; \r
+#define PPCR29 ppcr29.byte\r
+#define PPCR29_D7 ppcr29.bit._D7\r
+#define PPCR29_D6 ppcr29.bit._D6\r
+#define PPCR29_D5 ppcr29.bit._D5\r
+#define PPCR29_D4 ppcr29.bit._D4\r
+#define PPCR29_D3 ppcr29.bit._D3\r
+#define PPCR29_D2 ppcr29.bit._D2\r
+#define PPCR29_D1 ppcr29.bit._D1\r
+#define PPCR29_D0 ppcr29.bit._D0\r
+__IO_EXTERN IO_LWORD dmasa0; /* DMAC */\r
+#define DMASA0 dmasa0\r
+__IO_EXTERN IO_LWORD dmada0; \r
+#define DMADA0 dmada0\r
+__IO_EXTERN IO_LWORD dmasa1; \r
+#define DMASA1 dmasa1\r
+__IO_EXTERN IO_LWORD dmada1; \r
+#define DMADA1 dmada1\r
+__IO_EXTERN IO_LWORD dmasa2; \r
+#define DMASA2 dmasa2\r
+__IO_EXTERN IO_LWORD dmada2; \r
+#define DMADA2 dmada2\r
+__IO_EXTERN IO_LWORD dmasa3; \r
+#define DMASA3 dmasa3\r
+__IO_EXTERN IO_LWORD dmada3; \r
+#define DMADA3 dmada3\r
+__IO_EXTERN IO_LWORD dmasa4; \r
+#define DMASA4 dmasa4\r
+__IO_EXTERN IO_LWORD dmada4; \r
+#define DMADA4 dmada4\r
+__IO_EXTERN FMCSSTR fmcs; /* Flash Memory/I-Cache Control Register */\r
+#define FMCS fmcs.byte\r
+#define FMCS_ASYNC fmcs.bit._ASYNC\r
+#define FMCS_FIXE fmcs.bit._FIXE\r
+#define FMCS_BIRE fmcs.bit._BIRE\r
+#define FMCS_RDYEG fmcs.bit._RDYEG\r
+#define FMCS_RDY fmcs.bit._RDY\r
+#define FMCS_RDYI fmcs.bit._RDYI\r
+#define FMCS_RW16 fmcs.bit._RW16\r
+#define FMCS_LPM fmcs.bit._LPM\r
+__IO_EXTERN FMCRSTR fmcr; \r
+#define FMCR fmcr.byte\r
+#define FMCR_LOCK fmcr.bit._LOCK\r
+#define FMCR_PHASE fmcr.bit._PHASE\r
+#define FMCR_PF2I fmcr.bit._PF2I\r
+#define FMCR_RD64 fmcr.bit._RD64\r
+__IO_EXTERN FCHCRSTR fchcr; \r
+#define FCHCR fchcr.word\r
+#define FCHCR_REN fchcr.bit._REN\r
+#define FCHCR_TAGE fchcr.bit._TAGE\r
+#define FCHCR_FLUSH fchcr.bit._FLUSH\r
+#define FCHCR_DBEN fchcr.bit._DBEN\r
+#define FCHCR_PFEN fchcr.bit._PFEN\r
+#define FCHCR_PFMC fchcr.bit._PFMC\r
+#define FCHCR_LOCK fchcr.bit._LOCK\r
+#define FCHCR_ENAB fchcr.bit._ENAB\r
+#define FCHCR_SIZE1 fchcr.bit._SIZE1\r
+#define FCHCR_SIZE0 fchcr.bit._SIZE0\r
+#define FCHCR_SIZE fchcr.bitc._SIZE\r
+__IO_EXTERN FMWTSTR fmwt; \r
+#define FMWT fmwt.word\r
+#define FMWT_WTP1 fmwt.bit._WTP1\r
+#define FMWT_WTP0 fmwt.bit._WTP0\r
+#define FMWT_WEXH1 fmwt.bit._WEXH1\r
+#define FMWT_WEXH0 fmwt.bit._WEXH0\r
+#define FMWT_WTC3 fmwt.bit._WTC3\r
+#define FMWT_WTC2 fmwt.bit._WTC2\r
+#define FMWT_WTC1 fmwt.bit._WTC1\r
+#define FMWT_WTC0 fmwt.bit._WTC0\r
+#define FMWT_FRAM fmwt.bit._FRAM\r
+#define FMWT_ATD2 fmwt.bit._ATD2\r
+#define FMWT_ATD1 fmwt.bit._ATD1\r
+#define FMWT_ATD0 fmwt.bit._ATD0\r
+#define FMWT_EQ3 fmwt.bit._EQ3\r
+#define FMWT_EQ2 fmwt.bit._EQ2\r
+#define FMWT_EQ1 fmwt.bit._EQ1\r
+#define FMWT_EQ0 fmwt.bit._EQ0\r
+#define FMWT_WTP fmwt.bitc._WTP\r
+#define FMWT_WEXH fmwt.bitc._WEXH\r
+#define FMWT_WTC fmwt.bitc._WTC\r
+#define FMWT_ATD fmwt.bitc._ATD\r
+#define FMWT_EQ fmwt.bitc._EQ\r
+__IO_EXTERN FMWT2STR fmwt2; \r
+#define FMWT2 fmwt2.byte\r
+#define FMWT2_ALEH2 fmwt2.bit._ALEH2\r
+#define FMWT2_ALEH1 fmwt2.bit._ALEH1\r
+#define FMWT2_ALEH0 fmwt2.bit._ALEH0\r
+#define FMWT2_ALEH fmwt2.bitc._ALEH\r
+__IO_EXTERN FMPSSTR fmps; \r
+#define FMPS fmps.byte\r
+#define FMPS_PS2 fmps.bit._PS2\r
+#define FMPS_PS1 fmps.bit._PS1\r
+#define FMPS_PS0 fmps.bit._PS0\r
+#define FMPS_PS fmps.bitc._PS\r
+__IO_EXTERN IO_LWORD fmac; \r
+#define FMAC fmac\r
+__IO_EXTERN IO_LWORD fcha0; /* I_Cache Nonchachable area settings Register */\r
+#define FCHA0 fcha0\r
+__IO_EXTERN IO_LWORD fcha1; \r
+#define FCHA1 fcha1\r
+__IO_EXTERN FSCR0STR fscr0; /* Flash Security Control Register */\r
+#define FSCR0 fscr0.lword\r
+#define FSCR0_CRC31 fscr0.bit._CRC31\r
+#define FSCR0_CRC30 fscr0.bit._CRC30\r
+#define FSCR0_CRC29 fscr0.bit._CRC29\r
+#define FSCR0_CRC28 fscr0.bit._CRC28\r
+#define FSCR0_CRC27 fscr0.bit._CRC27\r
+#define FSCR0_CRC26 fscr0.bit._CRC26\r
+#define FSCR0_CRC25 fscr0.bit._CRC25\r
+#define FSCR0_CRC24 fscr0.bit._CRC24\r
+#define FSCR0_CRC23 fscr0.bit._CRC23\r
+#define FSCR0_CRC22 fscr0.bit._CRC22\r
+#define FSCR0_CRC21 fscr0.bit._CRC21\r
+#define FSCR0_CRC20 fscr0.bit._CRC20\r
+#define FSCR0_CRC19 fscr0.bit._CRC19\r
+#define FSCR0_CRC18 fscr0.bit._CRC18\r
+#define FSCR0_CRC17 fscr0.bit._CRC17\r
+#define FSCR0_CRC16 fscr0.bit._CRC16\r
+#define FSCR0_CRC15 fscr0.bit._CRC15\r
+#define FSCR0_CRC14 fscr0.bit._CRC14\r
+#define FSCR0_CRC13 fscr0.bit._CRC13\r
+#define FSCR0_CRC12 fscr0.bit._CRC12\r
+#define FSCR0_CRC11 fscr0.bit._CRC11\r
+#define FSCR0_CRC10 fscr0.bit._CRC10\r
+#define FSCR0_CRC9 fscr0.bit._CRC9\r
+#define FSCR0_CRC8 fscr0.bit._CRC8\r
+#define FSCR0_CRC7 fscr0.bit._CRC7\r
+#define FSCR0_CRC6 fscr0.bit._CRC6\r
+#define FSCR0_CRC5 fscr0.bit._CRC5\r
+#define FSCR0_CRC4 fscr0.bit._CRC4\r
+#define FSCR0_CRC3 fscr0.bit._CRC3\r
+#define FSCR0_CRC2 fscr0.bit._CRC2\r
+#define FSCR0_CRC1 fscr0.bit._CRC1\r
+#define FSCR0_CRC0 fscr0.bit._CRC0\r
+__IO_EXTERN FSCR1STR fscr1; \r
+#define FSCR1 fscr1.lword\r
+#define FSCR1_RDY fscr1.bit._RDY\r
+#define FSCR1_CSZ3 fscr1.bit._CSZ3\r
+#define FSCR1_CSZ2 fscr1.bit._CSZ2\r
+#define FSCR1_CSZ1 fscr1.bit._CSZ1\r
+#define FSCR1_CSZ0 fscr1.bit._CSZ0\r
+#define FSCR1_CSA15 fscr1.bit._CSA15\r
+#define FSCR1_CSA14 fscr1.bit._CSA14\r
+#define FSCR1_CSA13 fscr1.bit._CSA13\r
+#define FSCR1_CSA12 fscr1.bit._CSA12\r
+#define FSCR1_CSA11 fscr1.bit._CSA11\r
+#define FSCR1_CSA10 fscr1.bit._CSA10\r
+#define FSCR1_CSA9 fscr1.bit._CSA9\r
+#define FSCR1_CSA8 fscr1.bit._CSA8\r
+#define FSCR1_CSA7 fscr1.bit._CSA7\r
+#define FSCR1_CSA6 fscr1.bit._CSA6\r
+#define FSCR1_CSA5 fscr1.bit._CSA5\r
+#define FSCR1_CSA4 fscr1.bit._CSA4\r
+#define FSCR1_CSA3 fscr1.bit._CSA3\r
+#define FSCR1_CSA2 fscr1.bit._CSA2\r
+#define FSCR1_CSA1 fscr1.bit._CSA1\r
+#define FSCR1_CSA0 fscr1.bit._CSA0\r
+#define FSCR1_CSZ fscr1.bitc._CSZ\r
+__IO_EXTERN CTRLR4STR ctrlr4; /* CAN 4 Control Register */\r
+#define CTRLR4 ctrlr4.word\r
+#define CTRLR4_Test ctrlr4.bit._Test\r
+#define CTRLR4_CCE ctrlr4.bit._CCE\r
+#define CTRLR4_DAR ctrlr4.bit._DAR\r
+#define CTRLR4_EIE ctrlr4.bit._EIE\r
+#define CTRLR4_SIE ctrlr4.bit._SIE\r
+#define CTRLR4_IE ctrlr4.bit._IE\r
+#define CTRLR4_Init ctrlr4.bit._Init\r
+__IO_EXTERN STATR4STR statr4; \r
+#define STATR4 statr4.word\r
+#define STATR4_BOff statr4.bit._BOff\r
+#define STATR4_EWarn statr4.bit._EWarn\r
+#define STATR4_EPass statr4.bit._EPass\r
+#define STATR4_RxOK statr4.bit._RxOK\r
+#define STATR4_TxOK statr4.bit._TxOK\r
+#define STATR4_LEC2 statr4.bit._LEC2\r
+#define STATR4_LEC1 statr4.bit._LEC1\r
+#define STATR4_LEC0 statr4.bit._LEC0\r
+#define STATR4_LEC statr4.bitc._LEC\r
+__IO_EXTERN ERRCNT4STR errcnt4; \r
+#define ERRCNT4 errcnt4.word\r
+#define ERRCNT4_RP errcnt4.bit._RP\r
+#define ERRCNT4_REC6 errcnt4.bit._REC6\r
+#define ERRCNT4_REC5 errcnt4.bit._REC5\r
+#define ERRCNT4_REC4 errcnt4.bit._REC4\r
+#define ERRCNT4_REC3 errcnt4.bit._REC3\r
+#define ERRCNT4_REC2 errcnt4.bit._REC2\r
+#define ERRCNT4_REC1 errcnt4.bit._REC1\r
+#define ERRCNT4_REC0 errcnt4.bit._REC0\r
+#define ERRCNT4_TEC7 errcnt4.bit._TEC7\r
+#define ERRCNT4_TEC6 errcnt4.bit._TEC6\r
+#define ERRCNT4_TEC5 errcnt4.bit._TEC5\r
+#define ERRCNT4_TEC4 errcnt4.bit._TEC4\r
+#define ERRCNT4_TEC3 errcnt4.bit._TEC3\r
+#define ERRCNT4_TEC2 errcnt4.bit._TEC2\r
+#define ERRCNT4_TEC1 errcnt4.bit._TEC1\r
+#define ERRCNT4_TEC0 errcnt4.bit._TEC0\r
+#define ERRCNT4_REC errcnt4.bitc._REC\r
+#define ERRCNT4_TEC errcnt4.bitc._TEC\r
+__IO_EXTERN BTR4STR btr4; \r
+#define BTR4 btr4.word\r
+#define BTR4_Tseg22 btr4.bit._Tseg22\r
+#define BTR4_Tseg21 btr4.bit._Tseg21\r
+#define BTR4_Tseg20 btr4.bit._Tseg20\r
+#define BTR4_Tseg13 btr4.bit._Tseg13\r
+#define BTR4_Tseg12 btr4.bit._Tseg12\r
+#define BTR4_Tseg11 btr4.bit._Tseg11\r
+#define BTR4_Tseg10 btr4.bit._Tseg10\r
+#define BTR4_SJW1 btr4.bit._SJW1\r
+#define BTR4_SJW0 btr4.bit._SJW0\r
+#define BTR4_BRP5 btr4.bit._BRP5\r
+#define BTR4_BRP4 btr4.bit._BRP4\r
+#define BTR4_BRP3 btr4.bit._BRP3\r
+#define BTR4_BRP2 btr4.bit._BRP2\r
+#define BTR4_BRP1 btr4.bit._BRP1\r
+#define BTR4_BRP0 btr4.bit._BRP0\r
+#define BTR4_Tseg2 btr4.bitc._Tseg2\r
+#define BTR4_Tseg1 btr4.bitc._Tseg1\r
+#define BTR4_SJW btr4.bitc._SJW\r
+#define BTR4_BRP btr4.bitc._BRP\r
+__IO_EXTERN IO_WORD intr4; \r
+#define INTR4 intr4\r
+__IO_EXTERN TESTR4STR testr4; \r
+#define TESTR4 testr4.word\r
+#define TESTR4_Rx testr4.bit._Rx\r
+#define TESTR4_Tx1 testr4.bit._Tx1\r
+#define TESTR4_Tx0 testr4.bit._Tx0\r
+#define TESTR4_LBack testr4.bit._LBack\r
+#define TESTR4_Silent testr4.bit._Silent\r
+#define TESTR4_Basic testr4.bit._Basic\r
+#define TESTR4_Tx testr4.bitc._Tx\r
+__IO_EXTERN BRPER4STR brper4; \r
+#define BRPER4 brper4.word\r
+#define BRPER4_BRPE3 brper4.bit._BRPE3\r
+#define BRPER4_BRPE2 brper4.bit._BRPE2\r
+#define BRPER4_BRPE1 brper4.bit._BRPE1\r
+#define BRPER4_BRPE0 brper4.bit._BRPE0\r
+#define BRPER4_BRPE brper4.bitc._BRPE\r
+__IO_EXTERN BRPE4STR brpe4; \r
+#define BRPE4 brpe4.word\r
+__IO_EXTERN IF1CREQ4STR if1creq4; /* CAN 4 IF 1 */\r
+#define IF1CREQ4 if1creq4.word\r
+#define IF1CREQ4_Busy if1creq4.bit._Busy\r
+#define IF1CREQ4_MN5 if1creq4.bit._MN5\r
+#define IF1CREQ4_MN4 if1creq4.bit._MN4\r
+#define IF1CREQ4_MN3 if1creq4.bit._MN3\r
+#define IF1CREQ4_MN2 if1creq4.bit._MN2\r
+#define IF1CREQ4_MN1 if1creq4.bit._MN1\r
+#define IF1CREQ4_MN0 if1creq4.bit._MN0\r
+#define IF1CREQ4_MN if1creq4.bitc._MN\r
+__IO_EXTERN IF1CMSK4STR if1cmsk4; \r
+#define IF1CMSK4 if1cmsk4.word\r
+#define IF1CMSK4_WR if1cmsk4.bit._WR\r
+#define IF1CMSK4_Mask if1cmsk4.bit._Mask\r
+#define IF1CMSK4_Arb if1cmsk4.bit._Arb\r
+#define IF1CMSK4_Control if1cmsk4.bit._Control\r
+#define IF1CMSK4_CIP if1cmsk4.bit._CIP\r
+#define IF1CMSK4_TxReq if1cmsk4.bit._TxReq\r
+#define IF1CMSK4_DataA if1cmsk4.bit._DataA\r
+#define IF1CMSK4_DataB if1cmsk4.bit._DataB\r
+__IO_EXTERN IO_LWORD if1msk124; \r
+#define IF1MSK124 if1msk124\r
+__IO_EXTERN IF1MSK24STR if1msk24; \r
+#define IF1MSK24 if1msk24.word\r
+#define IF1MSK24_MXtd if1msk24.bit._MXtd\r
+#define IF1MSK24_MDir if1msk24.bit._MDir\r
+__IO_EXTERN IO_WORD if1msk14; \r
+#define IF1MSK14 if1msk14\r
+__IO_EXTERN IO_LWORD if1arb124; \r
+#define IF1ARB124 if1arb124\r
+__IO_EXTERN IF1ARB24STR if1arb24; \r
+#define IF1ARB24 if1arb24.word\r
+#define IF1ARB24_MsgVal if1arb24.bit._MsgVal\r
+#define IF1ARB24_Xtd if1arb24.bit._Xtd\r
+#define IF1ARB24_DIR if1arb24.bit._DIR\r
+__IO_EXTERN IO_WORD if1arb14; \r
+#define IF1ARB14 if1arb14\r
+__IO_EXTERN IF1MCTR4STR if1mctr4; \r
+#define IF1MCTR4 if1mctr4.word\r
+#define IF1MCTR4_NewDat if1mctr4.bit._NewDat\r
+#define IF1MCTR4_MsgLst if1mctr4.bit._MsgLst\r
+#define IF1MCTR4_IntPnd if1mctr4.bit._IntPnd\r
+#define IF1MCTR4_UMask if1mctr4.bit._UMask\r
+#define IF1MCTR4_TxIE if1mctr4.bit._TxIE\r
+#define IF1MCTR4_RxIE if1mctr4.bit._RxIE\r
+#define IF1MCTR4_RmtEn if1mctr4.bit._RmtEn\r
+#define IF1MCTR4_TxRqst if1mctr4.bit._TxRqst\r
+#define IF1MCTR4_EoB if1mctr4.bit._EoB\r
+#define IF1MCTR4_DLC3 if1mctr4.bit._DLC3\r
+#define IF1MCTR4_DLC2 if1mctr4.bit._DLC2\r
+#define IF1MCTR4_DLC1 if1mctr4.bit._DLC1\r
+#define IF1MCTR4_DLC0 if1mctr4.bit._DLC0\r
+#define IF1MCTR4_DLC if1mctr4.bitc._DLC\r
+__IO_EXTERN IO_LWORD if1dta124; \r
+#define IF1DTA124 if1dta124\r
+__IO_EXTERN IO_WORD if1dta14; \r
+#define IF1DTA14 if1dta14\r
+__IO_EXTERN IO_WORD if1dta24; \r
+#define IF1DTA24 if1dta24\r
+__IO_EXTERN IO_LWORD if1dtb124; \r
+#define IF1DTB124 if1dtb124\r
+__IO_EXTERN IO_WORD if1dtb14; \r
+#define IF1DTB14 if1dtb14\r
+__IO_EXTERN IO_WORD if1dtb24; \r
+#define IF1DTB24 if1dtb24\r
+__IO_EXTERN IO_LWORD if1dta_swp124; \r
+#define IF1DTA_SWP124 if1dta_swp124\r
+__IO_EXTERN IO_WORD if1dta_swp24; \r
+#define IF1DTA_SWP24 if1dta_swp24\r
+__IO_EXTERN IO_WORD if1dta_swp14; \r
+#define IF1DTA_SWP14 if1dta_swp14\r
+__IO_EXTERN IO_LWORD if1dtb_swp124; \r
+#define IF1DTB_SWP124 if1dtb_swp124\r
+__IO_EXTERN IO_WORD if1dtb_swp24; \r
+#define IF1DTB_SWP24 if1dtb_swp24\r
+__IO_EXTERN IO_WORD if1dtb_swp14; \r
+#define IF1DTB_SWP14 if1dtb_swp14\r
+__IO_EXTERN IF2CREQ4STR if2creq4; /* CAN 4 IF 2 */\r
+#define IF2CREQ4 if2creq4.word\r
+#define IF2CREQ4_Busy if2creq4.bit._Busy\r
+#define IF2CREQ4_MN5 if2creq4.bit._MN5\r
+#define IF2CREQ4_MN4 if2creq4.bit._MN4\r
+#define IF2CREQ4_MN3 if2creq4.bit._MN3\r
+#define IF2CREQ4_MN2 if2creq4.bit._MN2\r
+#define IF2CREQ4_MN1 if2creq4.bit._MN1\r
+#define IF2CREQ4_MN0 if2creq4.bit._MN0\r
+#define IF2CREQ4_MN if2creq4.bitc._MN\r
+__IO_EXTERN IF2CMSK4STR if2cmsk4; \r
+#define IF2CMSK4 if2cmsk4.word\r
+#define IF2CMSK4_WR if2cmsk4.bit._WR\r
+#define IF2CMSK4_Mask if2cmsk4.bit._Mask\r
+#define IF2CMSK4_Arb if2cmsk4.bit._Arb\r
+#define IF2CMSK4_Control if2cmsk4.bit._Control\r
+#define IF2CMSK4_CIP if2cmsk4.bit._CIP\r
+#define IF2CMSK4_TxReq if2cmsk4.bit._TxReq\r
+#define IF2CMSK4_DataA if2cmsk4.bit._DataA\r
+#define IF2CMSK4_DataB if2cmsk4.bit._DataB\r
+__IO_EXTERN IO_LWORD if2msk124; \r
+#define IF2MSK124 if2msk124\r
+__IO_EXTERN IF2MSK24STR if2msk24; \r
+#define IF2MSK24 if2msk24.word\r
+#define IF2MSK24_MXtd if2msk24.bit._MXtd\r
+#define IF2MSK24_MDir if2msk24.bit._MDir\r
+__IO_EXTERN IO_WORD if2msk14; \r
+#define IF2MSK14 if2msk14\r
+__IO_EXTERN IO_LWORD if2arb124; \r
+#define IF2ARB124 if2arb124\r
+__IO_EXTERN IF2ARB24STR if2arb24; \r
+#define IF2ARB24 if2arb24.word\r
+#define IF2ARB24_MsgVal if2arb24.bit._MsgVal\r
+#define IF2ARB24_Xtd if2arb24.bit._Xtd\r
+#define IF2ARB24_DIR if2arb24.bit._DIR\r
+__IO_EXTERN IO_WORD if2arb14; \r
+#define IF2ARB14 if2arb14\r
+__IO_EXTERN IF2MCTR4STR if2mctr4; \r
+#define IF2MCTR4 if2mctr4.word\r
+#define IF2MCTR4_NewDat if2mctr4.bit._NewDat\r
+#define IF2MCTR4_MsgLst if2mctr4.bit._MsgLst\r
+#define IF2MCTR4_IntPnd if2mctr4.bit._IntPnd\r
+#define IF2MCTR4_UMask if2mctr4.bit._UMask\r
+#define IF2MCTR4_TxIE if2mctr4.bit._TxIE\r
+#define IF2MCTR4_RxIE if2mctr4.bit._RxIE\r
+#define IF2MCTR4_RmtEn if2mctr4.bit._RmtEn\r
+#define IF2MCTR4_TxRqst if2mctr4.bit._TxRqst\r
+#define IF2MCTR4_EoB if2mctr4.bit._EoB\r
+#define IF2MCTR4_DLC3 if2mctr4.bit._DLC3\r
+#define IF2MCTR4_DLC2 if2mctr4.bit._DLC2\r
+#define IF2MCTR4_DLC1 if2mctr4.bit._DLC1\r
+#define IF2MCTR4_DLC0 if2mctr4.bit._DLC0\r
+#define IF2MCTR4_DLC if2mctr4.bitc._DLC\r
+__IO_EXTERN IO_LWORD if2dta124; \r
+#define IF2DTA124 if2dta124\r
+__IO_EXTERN IO_WORD if2dta14; \r
+#define IF2DTA14 if2dta14\r
+__IO_EXTERN IO_WORD if2dta24; \r
+#define IF2DTA24 if2dta24\r
+__IO_EXTERN IO_LWORD if2dtb124; \r
+#define IF2DTB124 if2dtb124\r
+__IO_EXTERN IO_WORD if2dtb14; \r
+#define IF2DTB14 if2dtb14\r
+__IO_EXTERN IO_WORD if2dtb24; \r
+#define IF2DTB24 if2dtb24\r
+__IO_EXTERN IO_LWORD if2dta_swp124; \r
+#define IF2DTA_SWP124 if2dta_swp124\r
+__IO_EXTERN IO_WORD if2dta_swp24; \r
+#define IF2DTA_SWP24 if2dta_swp24\r
+__IO_EXTERN IO_WORD if2dta_swp14; \r
+#define IF2DTA_SWP14 if2dta_swp14\r
+__IO_EXTERN IO_LWORD if2dtb_swp124; \r
+#define IF2DTB_SWP124 if2dtb_swp124\r
+__IO_EXTERN IO_WORD if2dtb_swp24; \r
+#define IF2DTB_SWP24 if2dtb_swp24\r
+__IO_EXTERN IO_WORD if2dtb_swp14; \r
+#define IF2DTB_SWP14 if2dtb_swp14\r
+__IO_EXTERN IO_LWORD treqr124; /* CAN 4 Status Flags */\r
+#define TREQR124 treqr124\r
+__IO_EXTERN IO_WORD treqr24; \r
+#define TREQR24 treqr24\r
+__IO_EXTERN IO_WORD treqr14; \r
+#define TREQR14 treqr14\r
+__IO_EXTERN IO_LWORD treqr344; \r
+#define TREQR344 treqr344\r
+__IO_EXTERN IO_LWORD newdt124; \r
+#define NEWDT124 newdt124\r
+__IO_EXTERN IO_WORD newdt24; \r
+#define NEWDT24 newdt24\r
+__IO_EXTERN IO_WORD newdt14; \r
+#define NEWDT14 newdt14\r
+__IO_EXTERN IO_LWORD intpnd124; \r
+#define INTPND124 intpnd124\r
+__IO_EXTERN IO_WORD intpnd24; \r
+#define INTPND24 intpnd24\r
+__IO_EXTERN IO_WORD intpnd14; \r
+#define INTPND14 intpnd14\r
+__IO_EXTERN IO_LWORD msgval124; \r
+#define MSGVAL124 msgval124\r
+__IO_EXTERN IO_WORD msgval24; \r
+#define MSGVAL24 msgval24\r
+__IO_EXTERN IO_WORD msgval14; \r
+#define MSGVAL14 msgval14\r
+__IO_EXTERN BCTRLSTR bctrl; /* EDSU/MPU Registers */\r
+#define BCTRL bctrl.lword\r
+#define BCTRL_SR bctrl.bit._SR\r
+#define BCTRL_SW bctrl.bit._SW\r
+#define BCTRL_SX bctrl.bit._SX\r
+#define BCTRL_UR bctrl.bit._UR\r
+#define BCTRL_UW bctrl.bit._UW\r
+#define BCTRL_UX bctrl.bit._UX\r
+#define BCTRL_FCPU bctrl.bit._FCPU\r
+#define BCTRL_FDMA bctrl.bit._FDMA\r
+#define BCTRL_EEMM bctrl.bit._EEMM\r
+#define BCTRL_PFD bctrl.bit._PFD\r
+#define BCTRL_SINT1 bctrl.bit._SINT1\r
+#define BCTRL_SINT0 bctrl.bit._SINT0\r
+#define BCTRL_EINT1 bctrl.bit._EINT1\r
+#define BCTRL_EINT0 bctrl.bit._EINT0\r
+#define BCTRL_EINTT bctrl.bit._EINTT\r
+#define BCTRL_EINTR bctrl.bit._EINTR\r
+#define BCTRL_SINT bctrl.bitc._SINT\r
+#define BCTRL_EINT bctrl.bitc._EINT\r
+__IO_EXTERN BSTATSTR bstat; \r
+#define BSTAT bstat.lword\r
+#define BSTAT_IDX4 bstat.bit._IDX4\r
+#define BSTAT_IDX3 bstat.bit._IDX3\r
+#define BSTAT_IDX2 bstat.bit._IDX2\r
+#define BSTAT_IDX1 bstat.bit._IDX1\r
+#define BSTAT_IDX0 bstat.bit._IDX0\r
+#define BSTAT_CDMA bstat.bit._CDMA\r
+#define BSTAT_CSZ1 bstat.bit._CSZ1\r
+#define BSTAT_CSZ0 bstat.bit._CSZ0\r
+#define BSTAT_CRW1 bstat.bit._CRW1\r
+#define BSTAT_CRW0 bstat.bit._CRW0\r
+#define BSTAT_PV bstat.bit._PV\r
+#define BSTAT_RST bstat.bit._RST\r
+#define BSTAT_INT1 bstat.bit._INT1\r
+#define BSTAT_INT0 bstat.bit._INT0\r
+#define BSTAT_INTT bstat.bit._INTT\r
+#define BSTAT_INTR bstat.bit._INTR\r
+#define BSTAT_IDX bstat.bitc._IDX\r
+#define BSTAT_CSZ bstat.bitc._CSZ\r
+#define BSTAT_CRW bstat.bitc._CRW\r
+#define BSTAT_INT bstat.bitc._INT\r
+__IO_EXTERN IO_LWORD biac; \r
+#define BIAC biac\r
+__IO_EXTERN IO_LWORD boac; \r
+#define BOAC boac\r
+__IO_EXTERN BIRQSTR birq; \r
+#define BIRQ birq.lword\r
+#define BIRQ_BD31 birq.bit._BD31\r
+#define BIRQ_BD30 birq.bit._BD30\r
+#define BIRQ_BD29 birq.bit._BD29\r
+#define BIRQ_BD28 birq.bit._BD28\r
+#define BIRQ_BD27 birq.bit._BD27\r
+#define BIRQ_BD26 birq.bit._BD26\r
+#define BIRQ_BD25 birq.bit._BD25\r
+#define BIRQ_BD24 birq.bit._BD24\r
+#define BIRQ_BD23 birq.bit._BD23\r
+#define BIRQ_BD22 birq.bit._BD22\r
+#define BIRQ_BD21 birq.bit._BD21\r
+#define BIRQ_BD20 birq.bit._BD20\r
+#define BIRQ_BD19 birq.bit._BD19\r
+#define BIRQ_BD18 birq.bit._BD18\r
+#define BIRQ_BD17 birq.bit._BD17\r
+#define BIRQ_BD16 birq.bit._BD16\r
+#define BIRQ_BD15 birq.bit._BD15\r
+#define BIRQ_BD14 birq.bit._BD14\r
+#define BIRQ_BD13 birq.bit._BD13\r
+#define BIRQ_BD12 birq.bit._BD12\r
+#define BIRQ_BD11 birq.bit._BD11\r
+#define BIRQ_BD10 birq.bit._BD10\r
+#define BIRQ_BD9 birq.bit._BD9\r
+#define BIRQ_BD8 birq.bit._BD8\r
+#define BIRQ_BD7 birq.bit._BD7\r
+#define BIRQ_BD6 birq.bit._BD6\r
+#define BIRQ_BD5 birq.bit._BD5\r
+#define BIRQ_BD4 birq.bit._BD4\r
+#define BIRQ_BD3 birq.bit._BD3\r
+#define BIRQ_BD2 birq.bit._BD2\r
+#define BIRQ_BD1 birq.bit._BD1\r
+#define BIRQ_BD0 birq.bit._BD0\r
+__IO_EXTERN BCR0STR bcr0; \r
+#define BCR0 bcr0.lword\r
+#define BCR0_SRX1 bcr0.bit._SRX1\r
+#define BCR0_SW1 bcr0.bit._SW1\r
+#define BCR0_SRX0 bcr0.bit._SRX0\r
+#define BCR0_SW0 bcr0.bit._SW0\r
+#define BCR0_URX1 bcr0.bit._URX1\r
+#define BCR0_UW1 bcr0.bit._UW1\r
+#define BCR0_URX0 bcr0.bit._URX0\r
+#define BCR0_UW0 bcr0.bit._UW0\r
+#define BCR0_MPE bcr0.bit._MPE\r
+#define BCR0_COMB bcr0.bit._COMB\r
+#define BCR0_CTC1 bcr0.bit._CTC1\r
+#define BCR0_CTC0 bcr0.bit._CTC0\r
+#define BCR0_OBS1 bcr0.bit._OBS1\r
+#define BCR0_OBS0 bcr0.bit._OBS0\r
+#define BCR0_OBT1 bcr0.bit._OBT1\r
+#define BCR0_OBT0 bcr0.bit._OBT0\r
+#define BCR0_EP3 bcr0.bit._EP3\r
+#define BCR0_EP2 bcr0.bit._EP2\r
+#define BCR0_EP1 bcr0.bit._EP1\r
+#define BCR0_EP0 bcr0.bit._EP0\r
+#define BCR0_EM1 bcr0.bit._EM1\r
+#define BCR0_EM0 bcr0.bit._EM0\r
+#define BCR0_ER1 bcr0.bit._ER1\r
+#define BCR0_ER0 bcr0.bit._ER0\r
+#define BCR0_CTC bcr0.bitc._CTC\r
+#define BCR0_OBS bcr0.bitc._OBS\r
+#define BCR0_OBT bcr0.bitc._OBT\r
+#define BCR0_EP bcr0.bitc._EP\r
+#define BCR0_EM bcr0.bitc._EM\r
+#define BCR0_ER bcr0.bitc._ER\r
+__IO_EXTERN BCR1STR bcr1; \r
+#define BCR1 bcr1.lword\r
+#define BCR1_SRX1 bcr1.bit._SRX1\r
+#define BCR1_SW1 bcr1.bit._SW1\r
+#define BCR1_SRX0 bcr1.bit._SRX0\r
+#define BCR1_SW0 bcr1.bit._SW0\r
+#define BCR1_URX1 bcr1.bit._URX1\r
+#define BCR1_UW1 bcr1.bit._UW1\r
+#define BCR1_URX0 bcr1.bit._URX0\r
+#define BCR1_UW0 bcr1.bit._UW0\r
+#define BCR1_MPE bcr1.bit._MPE\r
+#define BCR1_COMB bcr1.bit._COMB\r
+#define BCR1_CTC1 bcr1.bit._CTC1\r
+#define BCR1_CTC0 bcr1.bit._CTC0\r
+#define BCR1_OBS1 bcr1.bit._OBS1\r
+#define BCR1_OBS0 bcr1.bit._OBS0\r
+#define BCR1_OBT1 bcr1.bit._OBT1\r
+#define BCR1_OBT0 bcr1.bit._OBT0\r
+#define BCR1_EP3 bcr1.bit._EP3\r
+#define BCR1_EP2 bcr1.bit._EP2\r
+#define BCR1_EP1 bcr1.bit._EP1\r
+#define BCR1_EP0 bcr1.bit._EP0\r
+#define BCR1_EM1 bcr1.bit._EM1\r
+#define BCR1_EM0 bcr1.bit._EM0\r
+#define BCR1_ER1 bcr1.bit._ER1\r
+#define BCR1_ER0 bcr1.bit._ER0\r
+#define BCR1_CTC bcr1.bitc._CTC\r
+#define BCR1_OBS bcr1.bitc._OBS\r
+#define BCR1_OBT bcr1.bitc._OBT\r
+#define BCR1_EP bcr1.bitc._EP\r
+#define BCR1_EM bcr1.bitc._EM\r
+#define BCR1_ER bcr1.bitc._ER\r
+__IO_EXTERN IO_LWORD bad0; \r
+#define BAD0 bad0\r
+__IO_EXTERN IO_LWORD bad1; \r
+#define BAD1 bad1\r
+__IO_EXTERN IO_LWORD bad2; \r
+#define BAD2 bad2\r
+__IO_EXTERN IO_LWORD bad3; \r
+#define BAD3 bad3\r
+__IO_EXTERN IO_LWORD bad4; \r
+#define BAD4 bad4\r
+__IO_EXTERN IO_LWORD bad5; \r
+#define BAD5 bad5\r
+__IO_EXTERN IO_LWORD bad6; \r
+#define BAD6 bad6\r
+__IO_EXTERN IO_LWORD bad7; \r
+#define BAD7 bad7\r
+__IO_EXTERN IO_LWORD fsv1; /* FSV & BSV Registers */\r
+#define FSV1 fsv1\r
+__IO_EXTERN IO_LWORD bsv1; \r
+#define BSV1 bsv1\r
+__IO_EXTERN IO_LWORD fsv2; \r
+#define FSV2 fsv2\r
+__IO_EXTERN IO_LWORD bsv2; \r
+#define BSV2 bsv2\r
+/* include : INC465k_BSYNC.INC */\r
+/*-------------------------------------------------------------------*/\r
+/* INC465k.BSYNC : Macros Bus Sync*/\r
+\r
+#define RB_SYNC if(RBSYNC)\r
+#define CB_SYNC4 if(CBSYNC4)\r
+/*-------------------------------------------------------------------*/\r
+#endif /* __FASM__ */\r
+#endif /* __MB91XXX_H */\r
+#endif /* __IO_DEFINE */\r
--- /dev/null
+!_TAG_FILE_FORMAT 2 /extended format; --format=1 will not append ;" to lines/
+!_TAG_FILE_SORTED 1 /0=unsorted, 1=sorted, 2=foldcase/
+!_TAG_PROGRAM_AUTHOR Darren Hiebert /dhiebert@users.sourceforge.net/
+!_TAG_PROGRAM_NAME Exuberant Ctags //
+!_TAG_PROGRAM_URL http://ctags.sourceforge.net /official site/
+!_TAG_PROGRAM_VERSION 5.8 //
+AS Makefile /^AS = $(PREFIX)fasm911s$/;" m
+ASCII uart.c /^const char ASCII[] = "0123456789ABCDEF";$/;" v
+ASFLAGS Makefile /^ASFLAGS = -g -w 2 -O 0 -linf ON -lsrc ON -lsec ON$/;" m
+CC Makefile /^CC = $(PREFIX)fcc911s$/;" m
+CFLAGS Makefile /^CFLAGS = -g -w 1 -O 4 -B -K SPEED -K LONGADDRESS$/;" m
+CONV Makefile /^CONV = $(PREFIX)f2ms$/;" m
+CONVFLAGS Makefile /^CONVFLAGS = -cwno$/;" m
+CPUT Makefile /^CPUT = -cpu MB91F465K #TODO: change to X$/;" m
+DEFINES Makefile /^DEFINES =$/;" m
+DEPDIR Makefile /^DEPDIR = .deps$/;" m
+DPOLL Flash.h 17;" d
+DefaultIRQHandler vectors.c /^void DefaultIRQHandler (void)$/;" f
+Echo4 uart.c /^char Echo4(void) \/* Echo UART and return ch *\/$/;" f
+FLASH_CheckPendingInterrupt Flash.c /^unsigned char FLASH_CheckPendingInterrupt()$/;" f
+FLASH_PrepareReadMode Flash.c /^void FLASH_PrepareReadMode()$/;" f
+FLASH_PrepareWriteHalfWordMode Flash.c /^void FLASH_PrepareWriteHalfWordMode()$/;" f
+FLASH_ReadReset Flash.c /^unsigned char FLASH_ReadReset()$/;" f
+FLASH_ResumeSectorErase Flash.c /^unsigned char FLASH_ResumeSectorErase(unsigned int secaddr)$/;" f
+FLASH_SectorBlankCheck Flash.c /^unsigned char FLASH_SectorBlankCheck(unsigned int secaddr, unsigned int size)$/;" f
+FLASH_SectorErase Flash.c /^unsigned char FLASH_SectorErase(unsigned int secadr)$/;" f
+FLASH_WriteHalfWord Flash.c /^unsigned char FLASH_WriteHalfWord(unsigned int adr, unsigned short int data)$/;" f
+FMODwait Start91460.asm /^FMODwait: $/;" l
+Getch4 uart.c /^char Getch4(void) \/* waits for and returns incomming char *\/$/;" f
+IFlag Flash.c /^static unsigned int IFlag;$/;" v file:
+InitIrqLevels vectors.c /^void InitIrqLevels(void)$/;" f
+InitUart4 uart.c /^void InitUart4(void)$/;" f
+L0 Start91460.asm /^L0:$/;" l
+L1 Start91460.asm /^L1:$/;" l
+LD Makefile /^LD = $(PREFIX)flnk911s$/;" m
+LDFLAGS Makefile /^LDFLAGS = -g -AL 2$/;" m
+LDM0 Flash.c /^ LDM0 (R0)$/;" f
+LIBR Makefile /^LIBR = $(PREFIX)flibs$/;" m
+LIBRFLAGS Makefile /^LIBRFLAGS = -dt s,d,r,a -pl 60 -pw 132 -g -cwno $(CPUT)$/;" m
+NoMAINCSVreset Start91460.asm /^NoMAINCSVreset: $/;" l
+NoSUBCSVreset Start91460.asm /^NoSUBCSVreset: $/;" l
+OBJS Makefile /^OBJS = Flash.obj MAIN.obj RLT.obj uart.obj vectors.obj Start91460.obj mb91465k.obj$/;" m
+PLLwait Start91460.asm /^PLLwait: $/;" l
+PREFIX Makefile /^PREFIX = wine $(FUJDEV)\/Bin\/$/;" m
+PS Flash.c /^ MOV R0,PS ; Write back PS$/;" v
+Putch4 uart.c /^void Putch4(char ch) \/* sends a char *\/$/;" f
+Putdec4 uart.c /^void Putdec4(unsigned long x, int digits)$/;" f
+Puthex4 uart.c /^void Puthex4(unsigned long n, unsigned char digits)$/;" f
+Puts4 uart.c /^void Puts4(const char *Name2) \/* Puts a String to UART *\/$/;" f
+R0 Flash.c /^ MOV R0,PS ; Write back PS$/;" v
+R0 Flash.c /^ OR R4,R0 ; Set Flag as saved$/;" v
+R4 Flash.c /^ OR R4,R0 ; Set Flag as saved$/;" v
+RLT_CLOCKMODE_DIV128 RLT.h 21;" d
+RLT_CLOCKMODE_DIV2 RLT.h 16;" d
+RLT_CLOCKMODE_DIV32 RLT.h 18;" d
+RLT_CLOCKMODE_DIV64 RLT.h 20;" d
+RLT_CLOCKMODE_DIV8 RLT.h 17;" d
+RLT_CLOCKMODE_EXT RLT.h 19;" d
+RLT_Channel0_ISR RLT.c /^__interrupt void RLT_Channel0_ISR()$/;" f
+RLT_Channel1_ISR RLT.c /^__interrupt void RLT_Channel1_ISR()$/;" f
+RLT_Channel2_ISR RLT.c /^__interrupt void RLT_Channel2_ISR()$/;" f
+RLT_Channel3_ISR RLT.c /^__interrupt void RLT_Channel3_ISR()$/;" f
+RLT_Channel4_ISR RLT.c /^__interrupt void RLT_Channel4_ISR()$/;" f
+RLT_Channel5_ISR RLT.c /^__interrupt void RLT_Channel5_ISR()$/;" f
+RLT_Channel6_ISR RLT.c /^__interrupt void RLT_Channel6_ISR()$/;" f
+RLT_Channel7_ISR RLT.c /^__interrupt void RLT_Channel7_ISR()$/;" f
+RLT_EnableInterrupt RLT.c /^void RLT_EnableInterrupt(unsigned char channel)$/;" f
+RLT_InitializeTimer RLT.c /^void RLT_InitializeTimer(unsigned char channel, unsigned char runmode, unsigned char clockmode, unsigned char triggermode, unsigned char outputmode)$/;" f
+RLT_OUTOUTMODE_HIGHLEVEL RLT.h 28;" d
+RLT_OUTPUTMODE_LOWLEVEL RLT.h 29;" d
+RLT_RUMMODE_RELOAD RLT.h 14;" d
+RLT_RUNMODE_ONESHOT RLT.h 13;" d
+RLT_SetReloadValue RLT.c /^void RLT_SetReloadValue(unsigned char channel, unsigned short int value)$/;" f
+RLT_TRIGGER_BOTHEDGES RLT.h 26;" d
+RLT_TRIGGER_EXT_FALLINGEDGE RLT.h 24;" d
+RLT_TRIGGER_EXT_RISINGEDGE RLT.h 25;" d
+RLT_TRIGGER_SOFTWARE RLT.h 23;" d
+RLT_TriggerTimer RLT.c /^void RLT_TriggerTimer(unsigned char channel)$/;" f
+SETIMR Flash.h 19;" d
+TARGET Makefile /^TARGET = $(TNAME).abs$/;" m
+TARGET_MHX Makefile /^TARGET_MHX = $(TNAME).mhx$/;" m
+TLOVER Flash.h 18;" d
+TNAME Makefile /^TNAME = fuj$/;" m
+__FLASH_H__ Flash.h 9;" d
+__IO_DEFINE mb91465k.asm /^#define __IO_DEFINE$/;" d
+__IO_EXTERN mb91465k.h 33;" d
+__IO_EXTERN mb91465k.h 35;" d
+__RLT_H__ RLT.h 9;" d
+__abort Start91460.asm /^ __abort:$/;" l
+__exit Start91460.asm /^ __exit:$/;" l
+__start Start91460.asm /^__start: ; start point $/;" l
+__systemstack Start91460.asm /^ __systemstack:$/;" l
+__systemstack_top Start91460.asm /^ __systemstack_top: $/;" l
+__userstack Start91460.asm /^ __userstack:$/;" l
+__userstack_top Start91460.asm /^ __userstack_top:$/;" l
+_adcr0 mb91465k.h /^ .GLOBAL _adcs1, _adcs0, _adcs, _adcr1, _adcr0, _adcr$/;" v
+_adcr1 mb91465k.h /^ .GLOBAL _adcs1, _adcs0, _adcs, _adcr1, _adcr0, _adcr$/;" v
+_adcs mb91465k.h /^ .GLOBAL _adcs1, _adcs0, _adcs, _adcr1, _adcr0, _adcr$/;" v
+_adcs0 mb91465k.h /^ .GLOBAL _adcs1, _adcs0, _adcs, _adcr1, _adcr0, _adcr$/;" v
+_adct mb91465k.h /^ .GLOBAL _adct1, _adct0, _adct, _adsch, _adech, _tmrlr0$/;" v
+_adct0 mb91465k.h /^ .GLOBAL _adct1, _adct0, _adct, _adsch, _adech, _tmrlr0$/;" v
+_adech mb91465k.h /^ .GLOBAL _adct1, _adct0, _adct, _adsch, _adech, _tmrlr0$/;" v
+_aderh mb91465k.h /^ .GLOBAL _occp1, _occp2, _occp3, _aderh, _aderl, _ader$/;" v
+_aderl mb91465k.h /^ .GLOBAL _occp1, _occp2, _occp3, _aderh, _aderl, _ader$/;" v
+_adsch mb91465k.h /^ .GLOBAL _adct1, _adct0, _adct, _adsch, _adech, _tmrlr0$/;" v
+_bad2 mb91465k.h /^ .GLOBAL _bad1, _bad2, _bad3, _bad4, _bad5, _bad6$/;" v
+_bad3 mb91465k.h /^ .GLOBAL _bad1, _bad2, _bad3, _bad4, _bad5, _bad6$/;" v
+_bad4 mb91465k.h /^ .GLOBAL _bad1, _bad2, _bad3, _bad4, _bad5, _bad6$/;" v
+_bad5 mb91465k.h /^ .GLOBAL _bad1, _bad2, _bad3, _bad4, _bad5, _bad6$/;" v
+_bcr0 mb91465k.h /^ .GLOBAL _biac, _boac, _birq, _bcr0, _bcr1, _bad0$/;" v
+_bcr1 mb91465k.h /^ .GLOBAL _biac, _boac, _birq, _bcr0, _bcr1, _bad0$/;" v
+_bctrl mb91465k.h /^ .GLOBAL _intpnd14, _msgval124, _msgval24, _msgval14, _bctrl, _bstat$/;" v
+_bgr000 mb91465k.h /^ .GLOBAL _bgr00, _bgr100, _bgr000, _bgr01, _bgr101, _bgr001$/;" v
+_bgr002 mb91465k.h /^ .GLOBAL _bgr02, _bgr102, _bgr002, _bgr03, _bgr103, _bgr003$/;" v
+_bgr004 mb91465k.h /^ .GLOBAL _bgr04, _bgr104, _bgr004, _ibcr0, _ibsr0, _itba0$/;" v
+_bgr01 mb91465k.h /^ .GLOBAL _bgr00, _bgr100, _bgr000, _bgr01, _bgr101, _bgr001$/;" v
+_bgr03 mb91465k.h /^ .GLOBAL _bgr02, _bgr102, _bgr002, _bgr03, _bgr103, _bgr003$/;" v
+_bgr100 mb91465k.h /^ .GLOBAL _bgr00, _bgr100, _bgr000, _bgr01, _bgr101, _bgr001$/;" v
+_bgr101 mb91465k.h /^ .GLOBAL _bgr00, _bgr100, _bgr000, _bgr01, _bgr101, _bgr001$/;" v
+_bgr102 mb91465k.h /^ .GLOBAL _bgr02, _bgr102, _bgr002, _bgr03, _bgr103, _bgr003$/;" v
+_bgr103 mb91465k.h /^ .GLOBAL _bgr02, _bgr102, _bgr002, _bgr03, _bgr103, _bgr003$/;" v
+_bgr104 mb91465k.h /^ .GLOBAL _bgr04, _bgr104, _bgr004, _ibcr0, _ibsr0, _itba0$/;" v
+_birq mb91465k.h /^ .GLOBAL _biac, _boac, _birq, _bcr0, _bcr1, _bad0$/;" v
+_boac mb91465k.h /^ .GLOBAL _biac, _boac, _birq, _bcr0, _bcr1, _bad0$/;" v
+_brpe4 mb91465k.h /^ .GLOBAL _testr4, _brper4, _brpe4, _if1creq4, _if1cmsk4, _if1msk124$/;" v
+_brper4 mb91465k.h /^ .GLOBAL _testr4, _brper4, _brpe4, _if1creq4, _if1cmsk4, _if1msk124$/;" v
+_bsd0 mb91465k.h /^ .GLOBAL _roms, _bsd0, _bsd1, _bsdc, _bsrr, _icr00$/;" v
+_bsd1 mb91465k.h /^ .GLOBAL _roms, _bsd0, _bsd1, _bsdc, _bsrr, _icr00$/;" v
+_bsdc mb91465k.h /^ .GLOBAL _roms, _bsd0, _bsd1, _bsdc, _bsrr, _icr00$/;" v
+_bsrr mb91465k.h /^ .GLOBAL _roms, _bsd0, _bsd1, _bsdc, _bsrr, _icr00$/;" v
+_bsv1 mb91465k.h /^ .GLOBAL _bad7, _fsv1, _bsv1, _fsv2, _bsv2$/;" v
+_btr4 mb91465k.h /^ .GLOBAL _fscr1, _ctrlr4, _statr4, _errcnt4, _btr4, _intr4$/;" v
+_canckd mb91465k.h /^ .GLOBAL _cmcr, _cmt1, _cmt2, _canpre, _canckd, _lvsel$/;" v
+_canpre mb91465k.h /^ .GLOBAL _cmcr, _cmt1, _cmt2, _canpre, _canckd, _lvsel$/;" v
+_clkr mb91465k.h /^ .GLOBAL _ctbr, _clkr, _wpr, _divr0, _divr1, _plldivm$/;" v
+_cmt1 mb91465k.h /^ .GLOBAL _cmcr, _cmt1, _cmt2, _canpre, _canckd, _lvsel$/;" v
+_cmt2 mb91465k.h /^ .GLOBAL _cmcr, _cmt1, _cmt2, _canpre, _canckd, _lvsel$/;" v
+_csvcr mb91465k.h /^ .GLOBAL _wthr, _wtmr, _wtsr, _csvtr, _csvcr, _cscfg$/;" v
+_csvtr mb91465k.h /^ .GLOBAL _wthr, _wtmr, _wtsr, _csvtr, _csvcr, _cscfg$/;" v
+_ctrlr4 mb91465k.h /^ .GLOBAL _fscr1, _ctrlr4, _statr4, _errcnt4, _btr4, _intr4$/;" v
+_cucr mb91465k.h /^ .GLOBAL _cmcfg, _cucr, _cutd, _cutr1, _cutr2, _cmpr$/;" v
+_cutd mb91465k.h /^ .GLOBAL _cmcfg, _cucr, _cutd, _cutr1, _cutr2, _cmpr$/;" v
+_cutr1 mb91465k.h /^ .GLOBAL _cmcfg, _cucr, _cutd, _cutr1, _cutr2, _cmpr$/;" v
+_cutr2 mb91465k.h /^ .GLOBAL _cmcfg, _cucr, _cutd, _cutr1, _cutr2, _cmpr$/;" v
+_ddr14 mb91465k.h /^ .GLOBAL _pdrd29, _ddr14, _ddr15, _ddr16, _ddr17, _ddr18$/;" v
+_ddr15 mb91465k.h /^ .GLOBAL _pdrd29, _ddr14, _ddr15, _ddr16, _ddr17, _ddr18$/;" v
+_ddr16 mb91465k.h /^ .GLOBAL _pdrd29, _ddr14, _ddr15, _ddr16, _ddr17, _ddr18$/;" v
+_ddr17 mb91465k.h /^ .GLOBAL _pdrd29, _ddr14, _ddr15, _ddr16, _ddr17, _ddr18$/;" v
+_ddr20 mb91465k.h /^ .GLOBAL _ddr19, _ddr20, _ddr21, _ddr22, _ddr24, _ddr26$/;" v
+_ddr21 mb91465k.h /^ .GLOBAL _ddr19, _ddr20, _ddr21, _ddr22, _ddr24, _ddr26$/;" v
+_ddr22 mb91465k.h /^ .GLOBAL _ddr19, _ddr20, _ddr21, _ddr22, _ddr24, _ddr26$/;" v
+_ddr24 mb91465k.h /^ .GLOBAL _ddr19, _ddr20, _ddr21, _ddr22, _ddr24, _ddr26$/;" v
+_ddr28 mb91465k.h /^ .GLOBAL _ddr27, _ddr28, _ddr29, _pfr14, _pfr15, _pfr16$/;" v
+_ddr29 mb91465k.h /^ .GLOBAL _ddr27, _ddr28, _ddr29, _pfr14, _pfr15, _pfr16$/;" v
+_dicr mb91465k.h /^ .GLOBAL _enir1, _elvr1, _dicr, _hrcl, _rbsync, _scr00$/;" v
+_divr0 mb91465k.h /^ .GLOBAL _ctbr, _clkr, _wpr, _divr0, _divr1, _plldivm$/;" v
+_divr1 mb91465k.h /^ .GLOBAL _ctbr, _clkr, _wpr, _divr0, _divr1, _plldivm$/;" v
+_dmaca1 mb91465k.h /^ .GLOBAL _dmacb0, _dmaca1, _dmacb1, _dmaca2, _dmacb2, _dmaca3$/;" v
+_dmaca2 mb91465k.h /^ .GLOBAL _dmacb0, _dmaca1, _dmacb1, _dmaca2, _dmacb2, _dmaca3$/;" v
+_dmaca4 mb91465k.h /^ .GLOBAL _dmacb3, _dmaca4, _dmacb4, _dmacr, _ics45, _ics67$/;" v
+_dmacb1 mb91465k.h /^ .GLOBAL _dmacb0, _dmaca1, _dmacb1, _dmaca2, _dmacb2, _dmaca3$/;" v
+_dmacb2 mb91465k.h /^ .GLOBAL _dmacb0, _dmaca1, _dmacb1, _dmaca2, _dmacb2, _dmaca3$/;" v
+_dmacb4 mb91465k.h /^ .GLOBAL _dmacb3, _dmaca4, _dmacb4, _dmacr, _ics45, _ics67$/;" v
+_dmacr mb91465k.h /^ .GLOBAL _dmacb3, _dmaca4, _dmacb4, _dmacr, _ics45, _ics67$/;" v
+_dmada1 mb91465k.h /^ .GLOBAL _dmasa1, _dmada1, _dmasa2, _dmada2, _dmasa3, _dmada3$/;" v
+_dmada2 mb91465k.h /^ .GLOBAL _dmasa1, _dmada1, _dmasa2, _dmada2, _dmasa3, _dmada3$/;" v
+_dmada4 mb91465k.h /^ .GLOBAL _dmasa4, _dmada4, _fmcs, _fmcr, _fchcr, _fmwt$/;" v
+_dmasa0 mb91465k.h /^ .GLOBAL _ppcr26, _ppcr27, _ppcr28, _ppcr29, _dmasa0, _dmada0$/;" v
+_dmasa2 mb91465k.h /^ .GLOBAL _dmasa1, _dmada1, _dmasa2, _dmada2, _dmasa3, _dmada3$/;" v
+_dmasa3 mb91465k.h /^ .GLOBAL _dmasa1, _dmada1, _dmasa2, _dmada2, _dmasa3, _dmada3$/;" v
+_eccr02 mb91465k.h /^ .GLOBAL _escr02, _eccr02, _scr03, _smr03, _ssr03, _rdr03$/;" v
+_eccr03 mb91465k.h /^ .GLOBAL _tdr03, _escr03, _eccr03, _scr04, _smr04, _ssr04$/;" v
+_eccr04 mb91465k.h /^ .GLOBAL _rdr04, _tdr04, _escr04, _eccr04, _fsr04, _fcr04$/;" v
+_eirr0 mb91465k.h /^ .GLOBAL _pdr28, _pdr29, _eirr0, _enir0, _elvr0, _eirr1$/;" v
+_elvr0 mb91465k.h /^ .GLOBAL _pdr28, _pdr29, _eirr0, _enir0, _elvr0, _eirr1$/;" v
+_elvr1 mb91465k.h /^ .GLOBAL _enir1, _elvr1, _dicr, _hrcl, _rbsync, _scr00$/;" v
+_enir0 mb91465k.h /^ .GLOBAL _pdr28, _pdr29, _eirr0, _enir0, _elvr0, _eirr1$/;" v
+_epfr16 mb91465k.h /^ .GLOBAL _epfr15, _epfr16, _epfr17, _epfr18, _epfr19, _epfr20$/;" v
+_epfr17 mb91465k.h /^ .GLOBAL _epfr15, _epfr16, _epfr17, _epfr18, _epfr19, _epfr20$/;" v
+_epfr18 mb91465k.h /^ .GLOBAL _epfr15, _epfr16, _epfr17, _epfr18, _epfr19, _epfr20$/;" v
+_epfr19 mb91465k.h /^ .GLOBAL _epfr15, _epfr16, _epfr17, _epfr18, _epfr19, _epfr20$/;" v
+_epfr22 mb91465k.h /^ .GLOBAL _epfr21, _epfr22, _epfr24, _epfr26, _epfr27, _epfr29$/;" v
+_epfr24 mb91465k.h /^ .GLOBAL _epfr21, _epfr22, _epfr24, _epfr26, _epfr27, _epfr29$/;" v
+_epfr26 mb91465k.h /^ .GLOBAL _epfr21, _epfr22, _epfr24, _epfr26, _epfr27, _epfr29$/;" v
+_epfr27 mb91465k.h /^ .GLOBAL _epfr21, _epfr22, _epfr24, _epfr26, _epfr27, _epfr29$/;" v
+_epilr14 mb91465k.h /^ .GLOBAL _pilr26, _pilr27, _pilr28, _pilr29, _epilr14, _epilr15$/;" v
+_epilr17 mb91465k.h /^ .GLOBAL _epilr16, _epilr17, _epilr18, _epilr19, _epilr20, _epilr21$/;" v
+_epilr18 mb91465k.h /^ .GLOBAL _epilr16, _epilr17, _epilr18, _epilr19, _epilr20, _epilr21$/;" v
+_epilr19 mb91465k.h /^ .GLOBAL _epilr16, _epilr17, _epilr18, _epilr19, _epilr20, _epilr21$/;" v
+_epilr20 mb91465k.h /^ .GLOBAL _epilr16, _epilr17, _epilr18, _epilr19, _epilr20, _epilr21$/;" v
+_epilr24 mb91465k.h /^ .GLOBAL _epilr22, _epilr24, _epilr26, _epilr27, _epilr28, _epilr29$/;" v
+_epilr26 mb91465k.h /^ .GLOBAL _epilr22, _epilr24, _epilr26, _epilr27, _epilr28, _epilr29$/;" v
+_epilr27 mb91465k.h /^ .GLOBAL _epilr22, _epilr24, _epilr26, _epilr27, _epilr28, _epilr29$/;" v
+_epilr28 mb91465k.h /^ .GLOBAL _epilr22, _epilr24, _epilr26, _epilr27, _epilr28, _epilr29$/;" v
+_errcnt4 mb91465k.h /^ .GLOBAL _fscr1, _ctrlr4, _statr4, _errcnt4, _btr4, _intr4$/;" v
+_escr00 mb91465k.h /^ .GLOBAL _smr00, _ssr00, _rdr00, _tdr00, _escr00, _eccr00$/;" v
+_escr03 mb91465k.h /^ .GLOBAL _tdr03, _escr03, _eccr03, _scr04, _smr04, _ssr04$/;" v
+_escr04 mb91465k.h /^ .GLOBAL _rdr04, _tdr04, _escr04, _eccr04, _fsr04, _fcr04$/;" v
+_fcha0 mb91465k.h /^ .GLOBAL _fmwt2, _fmps, _fmac, _fcha0, _fcha1, _fscr0$/;" v
+_fcha1 mb91465k.h /^ .GLOBAL _fmwt2, _fmps, _fmac, _fcha0, _fcha1, _fscr0$/;" v
+_fchcr mb91465k.h /^ .GLOBAL _dmasa4, _dmada4, _fmcs, _fmcr, _fchcr, _fmwt$/;" v
+_fmac mb91465k.h /^ .GLOBAL _fmwt2, _fmps, _fmac, _fcha0, _fcha1, _fscr0$/;" v
+_fmcr mb91465k.h /^ .GLOBAL _dmasa4, _dmada4, _fmcs, _fmcr, _fchcr, _fmwt$/;" v
+_fmcs mb91465k.h /^ .GLOBAL _dmasa4, _dmada4, _fmcs, _fmcr, _fchcr, _fmwt$/;" v
+_fmps mb91465k.h /^ .GLOBAL _fmwt2, _fmps, _fmac, _fcha0, _fcha1, _fscr0$/;" v
+_fsr04 mb91465k.h /^ .GLOBAL _rdr04, _tdr04, _escr04, _eccr04, _fsr04, _fcr04$/;" v
+_fsv1 mb91465k.h /^ .GLOBAL _bad7, _fsv1, _bsv1, _fsv2, _bsv2$/;" v
+_fsv2 mb91465k.h /^ .GLOBAL _bad7, _fsv1, _bsv1, _fsv2, _bsv2$/;" v
+_gcn10 mb91465k.h /^ .GLOBAL _isba0, _idar0, _iccr0, _gcn10, _gcn20, _gcn11$/;" v
+_gcn12 mb91465k.h /^ .GLOBAL _gcn21, _gcn12, _gcn22, _ptmr00, _pcsr00, _pdut00$/;" v
+_gcn20 mb91465k.h /^ .GLOBAL _isba0, _idar0, _iccr0, _gcn10, _gcn20, _gcn11$/;" v
+_gcn22 mb91465k.h /^ .GLOBAL _gcn21, _gcn12, _gcn22, _ptmr00, _pcsr00, _pdut00$/;" v
+_hrcl mb91465k.h /^ .GLOBAL _enir1, _elvr1, _dicr, _hrcl, _rbsync, _scr00$/;" v
+_hwwd mb91465k.h /^ .GLOBAL _lvdet, _hwwde, _hwwd, _oscrh, _oscrl, _wpcrh$/;" v
+_hwwde mb91465k.h /^ .GLOBAL _lvdet, _hwwde, _hwwd, _oscrh, _oscrl, _wpcrh$/;" v
+_ibcr0 mb91465k.h /^ .GLOBAL _bgr04, _bgr104, _bgr004, _ibcr0, _ibsr0, _itba0$/;" v
+_ibsr0 mb91465k.h /^ .GLOBAL _bgr04, _bgr104, _bgr004, _ibcr0, _ibsr0, _itba0$/;" v
+_iccr0 mb91465k.h /^ .GLOBAL _isba0, _idar0, _iccr0, _gcn10, _gcn20, _gcn11$/;" v
+_icr02 mb91465k.h /^ .GLOBAL _icr01, _icr02, _icr03, _icr04, _icr05, _icr06$/;" v
+_icr03 mb91465k.h /^ .GLOBAL _icr01, _icr02, _icr03, _icr04, _icr05, _icr06$/;" v
+_icr04 mb91465k.h /^ .GLOBAL _icr01, _icr02, _icr03, _icr04, _icr05, _icr06$/;" v
+_icr05 mb91465k.h /^ .GLOBAL _icr01, _icr02, _icr03, _icr04, _icr05, _icr06$/;" v
+_icr08 mb91465k.h /^ .GLOBAL _icr07, _icr08, _icr09, _icr10, _icr11, _icr12$/;" v
+_icr09 mb91465k.h /^ .GLOBAL _icr07, _icr08, _icr09, _icr10, _icr11, _icr12$/;" v
+_icr10 mb91465k.h /^ .GLOBAL _icr07, _icr08, _icr09, _icr10, _icr11, _icr12$/;" v
+_icr11 mb91465k.h /^ .GLOBAL _icr07, _icr08, _icr09, _icr10, _icr11, _icr12$/;" v
+_icr14 mb91465k.h /^ .GLOBAL _icr13, _icr14, _icr15, _icr16, _icr17, _icr18$/;" v
+_icr15 mb91465k.h /^ .GLOBAL _icr13, _icr14, _icr15, _icr16, _icr17, _icr18$/;" v
+_icr16 mb91465k.h /^ .GLOBAL _icr13, _icr14, _icr15, _icr16, _icr17, _icr18$/;" v
+_icr17 mb91465k.h /^ .GLOBAL _icr13, _icr14, _icr15, _icr16, _icr17, _icr18$/;" v
+_icr20 mb91465k.h /^ .GLOBAL _icr19, _icr20, _icr21, _icr22, _icr23, _icr24$/;" v
+_icr21 mb91465k.h /^ .GLOBAL _icr19, _icr20, _icr21, _icr22, _icr23, _icr24$/;" v
+_icr22 mb91465k.h /^ .GLOBAL _icr19, _icr20, _icr21, _icr22, _icr23, _icr24$/;" v
+_icr23 mb91465k.h /^ .GLOBAL _icr19, _icr20, _icr21, _icr22, _icr23, _icr24$/;" v
+_icr26 mb91465k.h /^ .GLOBAL _icr25, _icr26, _icr27, _icr28, _icr29, _icr30$/;" v
+_icr27 mb91465k.h /^ .GLOBAL _icr25, _icr26, _icr27, _icr28, _icr29, _icr30$/;" v
+_icr28 mb91465k.h /^ .GLOBAL _icr25, _icr26, _icr27, _icr28, _icr29, _icr30$/;" v
+_icr29 mb91465k.h /^ .GLOBAL _icr25, _icr26, _icr27, _icr28, _icr29, _icr30$/;" v
+_icr32 mb91465k.h /^ .GLOBAL _icr31, _icr32, _icr33, _icr34, _icr35, _icr36$/;" v
+_icr33 mb91465k.h /^ .GLOBAL _icr31, _icr32, _icr33, _icr34, _icr35, _icr36$/;" v
+_icr34 mb91465k.h /^ .GLOBAL _icr31, _icr32, _icr33, _icr34, _icr35, _icr36$/;" v
+_icr35 mb91465k.h /^ .GLOBAL _icr31, _icr32, _icr33, _icr34, _icr35, _icr36$/;" v
+_icr38 mb91465k.h /^ .GLOBAL _icr37, _icr38, _icr39, _icr40, _icr41, _icr42$/;" v
+_icr39 mb91465k.h /^ .GLOBAL _icr37, _icr38, _icr39, _icr40, _icr41, _icr42$/;" v
+_icr40 mb91465k.h /^ .GLOBAL _icr37, _icr38, _icr39, _icr40, _icr41, _icr42$/;" v
+_icr41 mb91465k.h /^ .GLOBAL _icr37, _icr38, _icr39, _icr40, _icr41, _icr42$/;" v
+_icr44 mb91465k.h /^ .GLOBAL _icr43, _icr44, _icr45, _icr46, _icr47, _icr48$/;" v
+_icr45 mb91465k.h /^ .GLOBAL _icr43, _icr44, _icr45, _icr46, _icr47, _icr48$/;" v
+_icr46 mb91465k.h /^ .GLOBAL _icr43, _icr44, _icr45, _icr46, _icr47, _icr48$/;" v
+_icr47 mb91465k.h /^ .GLOBAL _icr43, _icr44, _icr45, _icr46, _icr47, _icr48$/;" v
+_icr50 mb91465k.h /^ .GLOBAL _icr49, _icr50, _icr51, _icr52, _icr53, _icr54$/;" v
+_icr51 mb91465k.h /^ .GLOBAL _icr49, _icr50, _icr51, _icr52, _icr53, _icr54$/;" v
+_icr52 mb91465k.h /^ .GLOBAL _icr49, _icr50, _icr51, _icr52, _icr53, _icr54$/;" v
+_icr53 mb91465k.h /^ .GLOBAL _icr49, _icr50, _icr51, _icr52, _icr53, _icr54$/;" v
+_icr56 mb91465k.h /^ .GLOBAL _icr55, _icr56, _icr57, _icr58, _icr59, _icr60$/;" v
+_icr57 mb91465k.h /^ .GLOBAL _icr55, _icr56, _icr57, _icr58, _icr59, _icr60$/;" v
+_icr58 mb91465k.h /^ .GLOBAL _icr55, _icr56, _icr57, _icr58, _icr59, _icr60$/;" v
+_icr59 mb91465k.h /^ .GLOBAL _icr55, _icr56, _icr57, _icr58, _icr59, _icr60$/;" v
+_icr62 mb91465k.h /^ .GLOBAL _icr61, _icr62, _icr63, _rsrr, _stcr, _tbcr$/;" v
+_icr63 mb91465k.h /^ .GLOBAL _icr61, _icr62, _icr63, _rsrr, _stcr, _tbcr$/;" v
+_ics01 mb91465k.h /^ .GLOBAL _pcn11, _pcnh11, _pcnl11, _ics01, _ics23, _ipcp0$/;" v
+_ics23 mb91465k.h /^ .GLOBAL _pcn11, _pcnh11, _pcnl11, _ics01, _ics23, _ipcp0$/;" v
+_ics45 mb91465k.h /^ .GLOBAL _dmacb3, _dmaca4, _dmacb4, _dmacr, _ics45, _ics67$/;" v
+_idar0 mb91465k.h /^ .GLOBAL _isba0, _idar0, _iccr0, _gcn10, _gcn20, _gcn11$/;" v
+_if1arb124 mb91465k.h /^ .GLOBAL _if1msk24, _if1msk14, _if1arb124, _if1arb24, _if1arb14, _if1mctr4$/;" v
+_if1arb14 mb91465k.h /^ .GLOBAL _if1msk24, _if1msk14, _if1arb124, _if1arb24, _if1arb14, _if1mctr4$/;" v
+_if1arb24 mb91465k.h /^ .GLOBAL _if1msk24, _if1msk14, _if1arb124, _if1arb24, _if1arb14, _if1mctr4$/;" v
+_if1cmsk4 mb91465k.h /^ .GLOBAL _testr4, _brper4, _brpe4, _if1creq4, _if1cmsk4, _if1msk124$/;" v
+_if1creq4 mb91465k.h /^ .GLOBAL _testr4, _brper4, _brpe4, _if1creq4, _if1cmsk4, _if1msk124$/;" v
+_if1dta14 mb91465k.h /^ .GLOBAL _if1dta124, _if1dta14, _if1dta24, _if1dtb124, _if1dtb14, _if1dtb24$/;" v
+_if1dta24 mb91465k.h /^ .GLOBAL _if1dta124, _if1dta14, _if1dta24, _if1dtb124, _if1dtb14, _if1dtb24$/;" v
+_if1dta_swp14 mb91465k.h /^ .GLOBAL _if1dta_swp124, _if1dta_swp24, _if1dta_swp14, _if1dtb_swp124, _if1dtb_swp24, _if1dtb_swp14$/;" v
+_if1dta_swp24 mb91465k.h /^ .GLOBAL _if1dta_swp124, _if1dta_swp24, _if1dta_swp14, _if1dtb_swp124, _if1dtb_swp24, _if1dtb_swp14$/;" v
+_if1dtb124 mb91465k.h /^ .GLOBAL _if1dta124, _if1dta14, _if1dta24, _if1dtb124, _if1dtb14, _if1dtb24$/;" v
+_if1dtb14 mb91465k.h /^ .GLOBAL _if1dta124, _if1dta14, _if1dta24, _if1dtb124, _if1dtb14, _if1dtb24$/;" v
+_if1dtb_swp124 mb91465k.h /^ .GLOBAL _if1dta_swp124, _if1dta_swp24, _if1dta_swp14, _if1dtb_swp124, _if1dtb_swp24, _if1dtb_swp14$/;" v
+_if1dtb_swp24 mb91465k.h /^ .GLOBAL _if1dta_swp124, _if1dta_swp24, _if1dta_swp14, _if1dtb_swp124, _if1dtb_swp24, _if1dtb_swp14$/;" v
+_if1msk14 mb91465k.h /^ .GLOBAL _if1msk24, _if1msk14, _if1arb124, _if1arb24, _if1arb14, _if1mctr4$/;" v
+_if2arb14 mb91465k.h /^ .GLOBAL _if2arb24, _if2arb14, _if2mctr4, _if2dta124, _if2dta14, _if2dta24$/;" v
+_if2cmsk4 mb91465k.h /^ .GLOBAL _if2creq4, _if2cmsk4, _if2msk124, _if2msk24, _if2msk14, _if2arb124$/;" v
+_if2dta124 mb91465k.h /^ .GLOBAL _if2arb24, _if2arb14, _if2mctr4, _if2dta124, _if2dta14, _if2dta24$/;" v
+_if2dta14 mb91465k.h /^ .GLOBAL _if2arb24, _if2arb14, _if2mctr4, _if2dta124, _if2dta14, _if2dta24$/;" v
+_if2dta_swp124 mb91465k.h /^ .GLOBAL _if2dtb124, _if2dtb14, _if2dtb24, _if2dta_swp124, _if2dta_swp24, _if2dta_swp14$/;" v
+_if2dta_swp24 mb91465k.h /^ .GLOBAL _if2dtb124, _if2dtb14, _if2dtb24, _if2dta_swp124, _if2dta_swp24, _if2dta_swp14$/;" v
+_if2dtb14 mb91465k.h /^ .GLOBAL _if2dtb124, _if2dtb14, _if2dtb24, _if2dta_swp124, _if2dta_swp24, _if2dta_swp14$/;" v
+_if2dtb24 mb91465k.h /^ .GLOBAL _if2dtb124, _if2dtb14, _if2dtb24, _if2dta_swp124, _if2dta_swp24, _if2dta_swp14$/;" v
+_if2dtb_swp14 mb91465k.h /^ .GLOBAL _if2dtb_swp124, _if2dtb_swp24, _if2dtb_swp14, _treqr124, _treqr24, _treqr14$/;" v
+_if2dtb_swp24 mb91465k.h /^ .GLOBAL _if2dtb_swp124, _if2dtb_swp24, _if2dtb_swp14, _treqr124, _treqr24, _treqr14$/;" v
+_if2mctr4 mb91465k.h /^ .GLOBAL _if2arb24, _if2arb14, _if2mctr4, _if2dta124, _if2dta14, _if2dta24$/;" v
+_if2msk124 mb91465k.h /^ .GLOBAL _if2creq4, _if2cmsk4, _if2msk124, _if2msk24, _if2msk14, _if2arb124$/;" v
+_if2msk14 mb91465k.h /^ .GLOBAL _if2creq4, _if2cmsk4, _if2msk124, _if2msk24, _if2msk14, _if2arb124$/;" v
+_if2msk24 mb91465k.h /^ .GLOBAL _if2creq4, _if2cmsk4, _if2msk124, _if2msk24, _if2msk14, _if2arb124$/;" v
+_intpnd124 mb91465k.h /^ .GLOBAL _treqr344, _newdt124, _newdt24, _newdt14, _intpnd124, _intpnd24$/;" v
+_ipcp2 mb91465k.h /^ .GLOBAL _ipcp1, _ipcp2, _ipcp3, _ocs01, _ocs23, _occp0$/;" v
+_ipcp3 mb91465k.h /^ .GLOBAL _ipcp1, _ipcp2, _ipcp3, _ocs01, _ocs23, _occp0$/;" v
+_ipcp5 mb91465k.h /^ .GLOBAL _ipcp4, _ipcp5, _ipcp6, _ipcp7, _ocs45, _ocs67$/;" v
+_ipcp6 mb91465k.h /^ .GLOBAL _ipcp4, _ipcp5, _ipcp6, _ipcp7, _ocs45, _ocs67$/;" v
+_ipcp7 mb91465k.h /^ .GLOBAL _ipcp4, _ipcp5, _ipcp6, _ipcp7, _ocs45, _ocs67$/;" v
+_itbal0 mb91465k.h /^ .GLOBAL _itbah0, _itbal0, _itmk0, _itmkh0, _itmkl0, _ismk0$/;" v
+_itmk0 mb91465k.h /^ .GLOBAL _itbah0, _itbal0, _itmk0, _itmkh0, _itmkl0, _ismk0$/;" v
+_itmkh0 mb91465k.h /^ .GLOBAL _itbah0, _itbal0, _itmk0, _itmkh0, _itmkl0, _ismk0$/;" v
+_itmkl0 mb91465k.h /^ .GLOBAL _itbah0, _itbal0, _itmk0, _itmkh0, _itmkl0, _ismk0$/;" v
+_modr mb91465k.h /^ .GLOBAL _wpcrl, _osccr, _regsel, _regctr, _modr, _pdrd14$/;" v
+_msgval124 mb91465k.h /^ .GLOBAL _intpnd14, _msgval124, _msgval24, _msgval14, _bctrl, _bstat$/;" v
+_msgval14 mb91465k.h /^ .GLOBAL _intpnd14, _msgval124, _msgval24, _msgval14, _bctrl, _bstat$/;" v
+_msgval24 mb91465k.h /^ .GLOBAL _intpnd14, _msgval124, _msgval24, _msgval14, _bctrl, _bstat$/;" v
+_newdt124 mb91465k.h /^ .GLOBAL _treqr344, _newdt124, _newdt24, _newdt14, _intpnd124, _intpnd24$/;" v
+_newdt14 mb91465k.h /^ .GLOBAL _treqr344, _newdt124, _newdt24, _newdt14, _intpnd124, _intpnd24$/;" v
+_newdt24 mb91465k.h /^ .GLOBAL _treqr344, _newdt124, _newdt24, _newdt14, _intpnd124, _intpnd24$/;" v
+_occp2 mb91465k.h /^ .GLOBAL _occp1, _occp2, _occp3, _aderh, _aderl, _ader$/;" v
+_occp3 mb91465k.h /^ .GLOBAL _occp1, _occp2, _occp3, _aderh, _aderl, _ader$/;" v
+_occp5 mb91465k.h /^ .GLOBAL _occp4, _occp5, _occp6, _occp7, _tcdt4, _tccs4$/;" v
+_occp6 mb91465k.h /^ .GLOBAL _occp4, _occp5, _occp6, _occp7, _tcdt4, _tccs4$/;" v
+_occp7 mb91465k.h /^ .GLOBAL _occp4, _occp5, _occp6, _occp7, _tcdt4, _tccs4$/;" v
+_ocs01 mb91465k.h /^ .GLOBAL _ipcp1, _ipcp2, _ipcp3, _ocs01, _ocs23, _occp0$/;" v
+_ocs23 mb91465k.h /^ .GLOBAL _ipcp1, _ipcp2, _ipcp3, _ocs01, _ocs23, _occp0$/;" v
+_ocs45 mb91465k.h /^ .GLOBAL _ipcp4, _ipcp5, _ipcp6, _ipcp7, _ocs45, _ocs67$/;" v
+_oscc1 mb91465k.h /^ .GLOBAL _plldivn, _plldivg, _pllmulg, _pllctrl, _oscc1, _oscs1$/;" v
+_osccr mb91465k.h /^ .GLOBAL _wpcrl, _osccr, _regsel, _regctr, _modr, _pdrd14$/;" v
+_oscrh mb91465k.h /^ .GLOBAL _lvdet, _hwwde, _hwwd, _oscrh, _oscrl, _wpcrh$/;" v
+_oscrl mb91465k.h /^ .GLOBAL _lvdet, _hwwde, _hwwd, _oscrh, _oscrl, _wpcrh$/;" v
+_oscs2 mb91465k.h /^ .GLOBAL _oscc2, _oscs2, _porten, _wtcer, _wtcr, _wtbr$/;" v
+_pcnh00 mb91465k.h /^ .GLOBAL _pcn00, _pcnh00, _pcnl00, _ptmr01, _pcsr01, _pdut01$/;" v
+_pcnh01 mb91465k.h /^ .GLOBAL _pcn01, _pcnh01, _pcnl01, _ptmr02, _pcsr02, _pdut02$/;" v
+_pcnh02 mb91465k.h /^ .GLOBAL _pcn02, _pcnh02, _pcnl02, _ptmr03, _pcsr03, _pdut03$/;" v
+_pcnh03 mb91465k.h /^ .GLOBAL _pcn03, _pcnh03, _pcnl03, _ptmr04, _pcsr04, _pdut04$/;" v
+_pcnh04 mb91465k.h /^ .GLOBAL _pcn04, _pcnh04, _pcnl04, _ptmr05, _pcsr05, _pdut05$/;" v
+_pcnh05 mb91465k.h /^ .GLOBAL _pcn05, _pcnh05, _pcnl05, _ptmr06, _pcsr06, _pdut06$/;" v
+_pcnh06 mb91465k.h /^ .GLOBAL _pcn06, _pcnh06, _pcnl06, _ptmr07, _pcsr07, _pdut07$/;" v
+_pcnh07 mb91465k.h /^ .GLOBAL _pcn07, _pcnh07, _pcnl07, _ptmr08, _pcsr08, _pdut08$/;" v
+_pcnh08 mb91465k.h /^ .GLOBAL _pcn08, _pcnh08, _pcnl08, _ptmr09, _pcsr09, _pdut09$/;" v
+_pcnh09 mb91465k.h /^ .GLOBAL _pcn09, _pcnh09, _pcnl09, _ptmr10, _pcsr10, _pdut10$/;" v
+_pcnh10 mb91465k.h /^ .GLOBAL _pcn10, _pcnh10, _pcnl10, _ptmr11, _pcsr11, _pdut11$/;" v
+_pcnh11 mb91465k.h /^ .GLOBAL _pcn11, _pcnh11, _pcnl11, _ics01, _ics23, _ipcp0$/;" v
+_pcnl00 mb91465k.h /^ .GLOBAL _pcn00, _pcnh00, _pcnl00, _ptmr01, _pcsr01, _pdut01$/;" v
+_pcnl01 mb91465k.h /^ .GLOBAL _pcn01, _pcnh01, _pcnl01, _ptmr02, _pcsr02, _pdut02$/;" v
+_pcnl02 mb91465k.h /^ .GLOBAL _pcn02, _pcnh02, _pcnl02, _ptmr03, _pcsr03, _pdut03$/;" v
+_pcnl03 mb91465k.h /^ .GLOBAL _pcn03, _pcnh03, _pcnl03, _ptmr04, _pcsr04, _pdut04$/;" v
+_pcnl04 mb91465k.h /^ .GLOBAL _pcn04, _pcnh04, _pcnl04, _ptmr05, _pcsr05, _pdut05$/;" v
+_pcnl05 mb91465k.h /^ .GLOBAL _pcn05, _pcnh05, _pcnl05, _ptmr06, _pcsr06, _pdut06$/;" v
+_pcnl06 mb91465k.h /^ .GLOBAL _pcn06, _pcnh06, _pcnl06, _ptmr07, _pcsr07, _pdut07$/;" v
+_pcnl07 mb91465k.h /^ .GLOBAL _pcn07, _pcnh07, _pcnl07, _ptmr08, _pcsr08, _pdut08$/;" v
+_pcnl08 mb91465k.h /^ .GLOBAL _pcn08, _pcnh08, _pcnl08, _ptmr09, _pcsr09, _pdut09$/;" v
+_pcnl09 mb91465k.h /^ .GLOBAL _pcn09, _pcnh09, _pcnl09, _ptmr10, _pcsr10, _pdut10$/;" v
+_pcnl10 mb91465k.h /^ .GLOBAL _pcn10, _pcnh10, _pcnl10, _ptmr11, _pcsr11, _pdut11$/;" v
+_pcnl11 mb91465k.h /^ .GLOBAL _pcn11, _pcnh11, _pcnl11, _ics01, _ics23, _ipcp0$/;" v
+_pcsr00 mb91465k.h /^ .GLOBAL _gcn21, _gcn12, _gcn22, _ptmr00, _pcsr00, _pdut00$/;" v
+_pcsr01 mb91465k.h /^ .GLOBAL _pcn00, _pcnh00, _pcnl00, _ptmr01, _pcsr01, _pdut01$/;" v
+_pcsr02 mb91465k.h /^ .GLOBAL _pcn01, _pcnh01, _pcnl01, _ptmr02, _pcsr02, _pdut02$/;" v
+_pcsr03 mb91465k.h /^ .GLOBAL _pcn02, _pcnh02, _pcnl02, _ptmr03, _pcsr03, _pdut03$/;" v
+_pcsr04 mb91465k.h /^ .GLOBAL _pcn03, _pcnh03, _pcnl03, _ptmr04, _pcsr04, _pdut04$/;" v
+_pcsr05 mb91465k.h /^ .GLOBAL _pcn04, _pcnh04, _pcnl04, _ptmr05, _pcsr05, _pdut05$/;" v
+_pcsr06 mb91465k.h /^ .GLOBAL _pcn05, _pcnh05, _pcnl05, _ptmr06, _pcsr06, _pdut06$/;" v
+_pcsr07 mb91465k.h /^ .GLOBAL _pcn06, _pcnh06, _pcnl06, _ptmr07, _pcsr07, _pdut07$/;" v
+_pcsr08 mb91465k.h /^ .GLOBAL _pcn07, _pcnh07, _pcnl07, _ptmr08, _pcsr08, _pdut08$/;" v
+_pcsr09 mb91465k.h /^ .GLOBAL _pcn08, _pcnh08, _pcnl08, _ptmr09, _pcsr09, _pdut09$/;" v
+_pcsr10 mb91465k.h /^ .GLOBAL _pcn09, _pcnh09, _pcnl09, _ptmr10, _pcsr10, _pdut10$/;" v
+_pcsr11 mb91465k.h /^ .GLOBAL _pcn10, _pcnh10, _pcnl10, _ptmr11, _pcsr11, _pdut11$/;" v
+_pdr15 mb91465k.h /^ .GLOBAL _pdr14, _pdr15, _pdr16, _pdr17, _pdr18, _pdr19$/;" v
+_pdr16 mb91465k.h /^ .GLOBAL _pdr14, _pdr15, _pdr16, _pdr17, _pdr18, _pdr19$/;" v
+_pdr17 mb91465k.h /^ .GLOBAL _pdr14, _pdr15, _pdr16, _pdr17, _pdr18, _pdr19$/;" v
+_pdr18 mb91465k.h /^ .GLOBAL _pdr14, _pdr15, _pdr16, _pdr17, _pdr18, _pdr19$/;" v
+_pdr21 mb91465k.h /^ .GLOBAL _pdr20, _pdr21, _pdr22, _pdr24, _pdr26, _pdr27$/;" v
+_pdr22 mb91465k.h /^ .GLOBAL _pdr20, _pdr21, _pdr22, _pdr24, _pdr26, _pdr27$/;" v
+_pdr24 mb91465k.h /^ .GLOBAL _pdr20, _pdr21, _pdr22, _pdr24, _pdr26, _pdr27$/;" v
+_pdr26 mb91465k.h /^ .GLOBAL _pdr20, _pdr21, _pdr22, _pdr24, _pdr26, _pdr27$/;" v
+_pdr29 mb91465k.h /^ .GLOBAL _pdr28, _pdr29, _eirr0, _enir0, _elvr0, _eirr1$/;" v
+_pdrd16 mb91465k.h /^ .GLOBAL _pdrd15, _pdrd16, _pdrd17, _pdrd18, _pdrd19, _pdrd20$/;" v
+_pdrd17 mb91465k.h /^ .GLOBAL _pdrd15, _pdrd16, _pdrd17, _pdrd18, _pdrd19, _pdrd20$/;" v
+_pdrd18 mb91465k.h /^ .GLOBAL _pdrd15, _pdrd16, _pdrd17, _pdrd18, _pdrd19, _pdrd20$/;" v
+_pdrd19 mb91465k.h /^ .GLOBAL _pdrd15, _pdrd16, _pdrd17, _pdrd18, _pdrd19, _pdrd20$/;" v
+_pdrd22 mb91465k.h /^ .GLOBAL _pdrd21, _pdrd22, _pdrd24, _pdrd26, _pdrd27, _pdrd28$/;" v
+_pdrd24 mb91465k.h /^ .GLOBAL _pdrd21, _pdrd22, _pdrd24, _pdrd26, _pdrd27, _pdrd28$/;" v
+_pdrd26 mb91465k.h /^ .GLOBAL _pdrd21, _pdrd22, _pdrd24, _pdrd26, _pdrd27, _pdrd28$/;" v
+_pdrd27 mb91465k.h /^ .GLOBAL _pdrd21, _pdrd22, _pdrd24, _pdrd26, _pdrd27, _pdrd28$/;" v
+_pfr14 mb91465k.h /^ .GLOBAL _ddr27, _ddr28, _ddr29, _pfr14, _pfr15, _pfr16$/;" v
+_pfr15 mb91465k.h /^ .GLOBAL _ddr27, _ddr28, _ddr29, _pfr14, _pfr15, _pfr16$/;" v
+_pfr18 mb91465k.h /^ .GLOBAL _pfr17, _pfr18, _pfr19, _pfr20, _pfr21, _pfr22$/;" v
+_pfr19 mb91465k.h /^ .GLOBAL _pfr17, _pfr18, _pfr19, _pfr20, _pfr21, _pfr22$/;" v
+_pfr20 mb91465k.h /^ .GLOBAL _pfr17, _pfr18, _pfr19, _pfr20, _pfr21, _pfr22$/;" v
+_pfr21 mb91465k.h /^ .GLOBAL _pfr17, _pfr18, _pfr19, _pfr20, _pfr21, _pfr22$/;" v
+_pfr26 mb91465k.h /^ .GLOBAL _pfr24, _pfr26, _pfr27, _pfr28, _pfr29, _epfr14$/;" v
+_pfr27 mb91465k.h /^ .GLOBAL _pfr24, _pfr26, _pfr27, _pfr28, _pfr29, _epfr14$/;" v
+_pfr28 mb91465k.h /^ .GLOBAL _pfr24, _pfr26, _pfr27, _pfr28, _pfr29, _epfr14$/;" v
+_pfr29 mb91465k.h /^ .GLOBAL _pfr24, _pfr26, _pfr27, _pfr28, _pfr29, _epfr14$/;" v
+_pilr14 mb91465k.h /^ .GLOBAL _podr28, _podr29, _pilr14, _pilr15, _pilr16, _pilr17$/;" v
+_pilr15 mb91465k.h /^ .GLOBAL _podr28, _podr29, _pilr14, _pilr15, _pilr16, _pilr17$/;" v
+_pilr16 mb91465k.h /^ .GLOBAL _podr28, _podr29, _pilr14, _pilr15, _pilr16, _pilr17$/;" v
+_pilr19 mb91465k.h /^ .GLOBAL _pilr18, _pilr19, _pilr20, _pilr21, _pilr22, _pilr24$/;" v
+_pilr20 mb91465k.h /^ .GLOBAL _pilr18, _pilr19, _pilr20, _pilr21, _pilr22, _pilr24$/;" v
+_pilr21 mb91465k.h /^ .GLOBAL _pilr18, _pilr19, _pilr20, _pilr21, _pilr22, _pilr24$/;" v
+_pilr22 mb91465k.h /^ .GLOBAL _pilr18, _pilr19, _pilr20, _pilr21, _pilr22, _pilr24$/;" v
+_pilr27 mb91465k.h /^ .GLOBAL _pilr26, _pilr27, _pilr28, _pilr29, _epilr14, _epilr15$/;" v
+_pilr28 mb91465k.h /^ .GLOBAL _pilr26, _pilr27, _pilr28, _pilr29, _epilr14, _epilr15$/;" v
+_pilr29 mb91465k.h /^ .GLOBAL _pilr26, _pilr27, _pilr28, _pilr29, _epilr14, _epilr15$/;" v
+_pllctrl mb91465k.h /^ .GLOBAL _plldivn, _plldivg, _pllmulg, _pllctrl, _oscc1, _oscs1$/;" v
+_plldivg mb91465k.h /^ .GLOBAL _plldivn, _plldivg, _pllmulg, _pllctrl, _oscc1, _oscs1$/;" v
+_pllmulg mb91465k.h /^ .GLOBAL _plldivn, _plldivg, _pllmulg, _pllctrl, _oscc1, _oscs1$/;" v
+_podr15 mb91465k.h /^ .GLOBAL _podr14, _podr15, _podr16, _podr17, _podr18, _podr19$/;" v
+_podr16 mb91465k.h /^ .GLOBAL _podr14, _podr15, _podr16, _podr17, _podr18, _podr19$/;" v
+_podr17 mb91465k.h /^ .GLOBAL _podr14, _podr15, _podr16, _podr17, _podr18, _podr19$/;" v
+_podr18 mb91465k.h /^ .GLOBAL _podr14, _podr15, _podr16, _podr17, _podr18, _podr19$/;" v
+_podr21 mb91465k.h /^ .GLOBAL _podr20, _podr21, _podr22, _podr24, _podr26, _podr27$/;" v
+_podr22 mb91465k.h /^ .GLOBAL _podr20, _podr21, _podr22, _podr24, _podr26, _podr27$/;" v
+_podr24 mb91465k.h /^ .GLOBAL _podr20, _podr21, _podr22, _podr24, _podr26, _podr27$/;" v
+_podr26 mb91465k.h /^ .GLOBAL _podr20, _podr21, _podr22, _podr24, _podr26, _podr27$/;" v
+_podr29 mb91465k.h /^ .GLOBAL _podr28, _podr29, _pilr14, _pilr15, _pilr16, _pilr17$/;" v
+_porten mb91465k.h /^ .GLOBAL _oscc2, _oscs2, _porten, _wtcer, _wtcr, _wtbr$/;" v
+_ppcr14 mb91465k.h /^ .GLOBAL _pper28, _pper29, _ppcr14, _ppcr15, _ppcr16, _ppcr17$/;" v
+_ppcr15 mb91465k.h /^ .GLOBAL _pper28, _pper29, _ppcr14, _ppcr15, _ppcr16, _ppcr17$/;" v
+_ppcr16 mb91465k.h /^ .GLOBAL _pper28, _pper29, _ppcr14, _ppcr15, _ppcr16, _ppcr17$/;" v
+_ppcr19 mb91465k.h /^ .GLOBAL _ppcr18, _ppcr19, _ppcr20, _ppcr21, _ppcr22, _ppcr24$/;" v
+_ppcr20 mb91465k.h /^ .GLOBAL _ppcr18, _ppcr19, _ppcr20, _ppcr21, _ppcr22, _ppcr24$/;" v
+_ppcr21 mb91465k.h /^ .GLOBAL _ppcr18, _ppcr19, _ppcr20, _ppcr21, _ppcr22, _ppcr24$/;" v
+_ppcr22 mb91465k.h /^ .GLOBAL _ppcr18, _ppcr19, _ppcr20, _ppcr21, _ppcr22, _ppcr24$/;" v
+_ppcr27 mb91465k.h /^ .GLOBAL _ppcr26, _ppcr27, _ppcr28, _ppcr29, _dmasa0, _dmada0$/;" v
+_ppcr28 mb91465k.h /^ .GLOBAL _ppcr26, _ppcr27, _ppcr28, _ppcr29, _dmasa0, _dmada0$/;" v
+_ppcr29 mb91465k.h /^ .GLOBAL _ppcr26, _ppcr27, _ppcr28, _ppcr29, _dmasa0, _dmada0$/;" v
+_pper15 mb91465k.h /^ .GLOBAL _pper14, _pper15, _pper16, _pper17, _pper18, _pper19$/;" v
+_pper16 mb91465k.h /^ .GLOBAL _pper14, _pper15, _pper16, _pper17, _pper18, _pper19$/;" v
+_pper17 mb91465k.h /^ .GLOBAL _pper14, _pper15, _pper16, _pper17, _pper18, _pper19$/;" v
+_pper18 mb91465k.h /^ .GLOBAL _pper14, _pper15, _pper16, _pper17, _pper18, _pper19$/;" v
+_pper21 mb91465k.h /^ .GLOBAL _pper20, _pper21, _pper22, _pper24, _pper26, _pper27$/;" v
+_pper22 mb91465k.h /^ .GLOBAL _pper20, _pper21, _pper22, _pper24, _pper26, _pper27$/;" v
+_pper24 mb91465k.h /^ .GLOBAL _pper20, _pper21, _pper22, _pper24, _pper26, _pper27$/;" v
+_pper26 mb91465k.h /^ .GLOBAL _pper20, _pper21, _pper22, _pper24, _pper26, _pper27$/;" v
+_pper29 mb91465k.h /^ .GLOBAL _pper28, _pper29, _ppcr14, _ppcr15, _ppcr16, _ppcr17$/;" v
+_ptmr00 mb91465k.h /^ .GLOBAL _gcn21, _gcn12, _gcn22, _ptmr00, _pcsr00, _pdut00$/;" v
+_ptmr01 mb91465k.h /^ .GLOBAL _pcn00, _pcnh00, _pcnl00, _ptmr01, _pcsr01, _pdut01$/;" v
+_ptmr02 mb91465k.h /^ .GLOBAL _pcn01, _pcnh01, _pcnl01, _ptmr02, _pcsr02, _pdut02$/;" v
+_ptmr03 mb91465k.h /^ .GLOBAL _pcn02, _pcnh02, _pcnl02, _ptmr03, _pcsr03, _pdut03$/;" v
+_ptmr04 mb91465k.h /^ .GLOBAL _pcn03, _pcnh03, _pcnl03, _ptmr04, _pcsr04, _pdut04$/;" v
+_ptmr05 mb91465k.h /^ .GLOBAL _pcn04, _pcnh04, _pcnl04, _ptmr05, _pcsr05, _pdut05$/;" v
+_ptmr06 mb91465k.h /^ .GLOBAL _pcn05, _pcnh05, _pcnl05, _ptmr06, _pcsr06, _pdut06$/;" v
+_ptmr07 mb91465k.h /^ .GLOBAL _pcn06, _pcnh06, _pcnl06, _ptmr07, _pcsr07, _pdut07$/;" v
+_ptmr08 mb91465k.h /^ .GLOBAL _pcn07, _pcnh07, _pcnl07, _ptmr08, _pcsr08, _pdut08$/;" v
+_ptmr09 mb91465k.h /^ .GLOBAL _pcn08, _pcnh08, _pcnl08, _ptmr09, _pcsr09, _pdut09$/;" v
+_ptmr10 mb91465k.h /^ .GLOBAL _pcn09, _pcnh09, _pcnl09, _ptmr10, _pcsr10, _pdut10$/;" v
+_ptmr11 mb91465k.h /^ .GLOBAL _pcn10, _pcnh10, _pcnl10, _ptmr11, _pcsr11, _pdut11$/;" v
+_rbsync mb91465k.h /^ .GLOBAL _enir1, _elvr1, _dicr, _hrcl, _rbsync, _scr00$/;" v
+_rdr00 mb91465k.h /^ .GLOBAL _smr00, _ssr00, _rdr00, _tdr00, _escr00, _eccr00$/;" v
+_rdr01 mb91465k.h /^ .GLOBAL _scr01, _smr01, _ssr01, _rdr01, _tdr01, _escr01$/;" v
+_rdr02 mb91465k.h /^ .GLOBAL _eccr01, _scr02, _smr02, _ssr02, _rdr02, _tdr02$/;" v
+_regctr mb91465k.h /^ .GLOBAL _wpcrl, _osccr, _regsel, _regctr, _modr, _pdrd14$/;" v
+_regsel mb91465k.h /^ .GLOBAL _wpcrl, _osccr, _regsel, _regctr, _modr, _pdrd14$/;" v
+_rsrr mb91465k.h /^ .GLOBAL _icr61, _icr62, _icr63, _rsrr, _stcr, _tbcr$/;" v
+_scr02 mb91465k.h /^ .GLOBAL _eccr01, _scr02, _smr02, _ssr02, _rdr02, _tdr02$/;" v
+_scr03 mb91465k.h /^ .GLOBAL _escr02, _eccr02, _scr03, _smr03, _ssr03, _rdr03$/;" v
+_scr04 mb91465k.h /^ .GLOBAL _tdr03, _escr03, _eccr03, _scr04, _smr04, _ssr04$/;" v
+_smr01 mb91465k.h /^ .GLOBAL _scr01, _smr01, _ssr01, _rdr01, _tdr01, _escr01$/;" v
+_smr02 mb91465k.h /^ .GLOBAL _eccr01, _scr02, _smr02, _ssr02, _rdr02, _tdr02$/;" v
+_smr03 mb91465k.h /^ .GLOBAL _escr02, _eccr02, _scr03, _smr03, _ssr03, _rdr03$/;" v
+_smr04 mb91465k.h /^ .GLOBAL _tdr03, _escr03, _eccr03, _scr04, _smr04, _ssr04$/;" v
+_ssr00 mb91465k.h /^ .GLOBAL _smr00, _ssr00, _rdr00, _tdr00, _escr00, _eccr00$/;" v
+_ssr01 mb91465k.h /^ .GLOBAL _scr01, _smr01, _ssr01, _rdr01, _tdr01, _escr01$/;" v
+_ssr02 mb91465k.h /^ .GLOBAL _eccr01, _scr02, _smr02, _ssr02, _rdr02, _tdr02$/;" v
+_ssr03 mb91465k.h /^ .GLOBAL _escr02, _eccr02, _scr03, _smr03, _ssr03, _rdr03$/;" v
+_statr4 mb91465k.h /^ .GLOBAL _fscr1, _ctrlr4, _statr4, _errcnt4, _btr4, _intr4$/;" v
+_stcr mb91465k.h /^ .GLOBAL _icr61, _icr62, _icr63, _rsrr, _stcr, _tbcr$/;" v
+_tccs0 mb91465k.h /^ .GLOBAL _tmcsr7, _tmcsrh7, _tmcsrl7, _tcdt0, _tccs0, _tcdt1$/;" v
+_tccs2 mb91465k.h /^ .GLOBAL _tccs1, _tcdt2, _tccs2, _tcdt3, _tccs3, _dmaca0$/;" v
+_tccs3 mb91465k.h /^ .GLOBAL _tccs1, _tcdt2, _tccs2, _tcdt3, _tccs3, _dmaca0$/;" v
+_tccs5 mb91465k.h /^ .GLOBAL _tcdt5, _tccs5, _tcdt6, _tccs6, _tcdt7, _tccs7$/;" v
+_tccs6 mb91465k.h /^ .GLOBAL _tcdt5, _tccs5, _tcdt6, _tccs6, _tcdt7, _tccs7$/;" v
+_tcdt0 mb91465k.h /^ .GLOBAL _tmcsr7, _tmcsrh7, _tmcsrl7, _tcdt0, _tccs0, _tcdt1$/;" v
+_tcdt2 mb91465k.h /^ .GLOBAL _tccs1, _tcdt2, _tccs2, _tcdt3, _tccs3, _dmaca0$/;" v
+_tcdt3 mb91465k.h /^ .GLOBAL _tccs1, _tcdt2, _tccs2, _tcdt3, _tccs3, _dmaca0$/;" v
+_tcdt4 mb91465k.h /^ .GLOBAL _occp4, _occp5, _occp6, _occp7, _tcdt4, _tccs4$/;" v
+_tcdt6 mb91465k.h /^ .GLOBAL _tcdt5, _tccs5, _tcdt6, _tccs6, _tcdt7, _tccs7$/;" v
+_tcdt7 mb91465k.h /^ .GLOBAL _tcdt5, _tccs5, _tcdt6, _tccs6, _tcdt7, _tccs7$/;" v
+_tdr00 mb91465k.h /^ .GLOBAL _smr00, _ssr00, _rdr00, _tdr00, _escr00, _eccr00$/;" v
+_tdr01 mb91465k.h /^ .GLOBAL _scr01, _smr01, _ssr01, _rdr01, _tdr01, _escr01$/;" v
+_tdr04 mb91465k.h /^ .GLOBAL _rdr04, _tdr04, _escr04, _eccr04, _fsr04, _fcr04$/;" v
+_tmcsr0 mb91465k.h /^ .GLOBAL _tmr0, _tmcsr0, _tmcsrh0, _tmcsrl0, _tmrlr1, _tmr1$/;" v
+_tmcsr3 mb91465k.h /^ .GLOBAL _tmcsrh2, _tmcsrl2, _tmrlr3, _tmr3, _tmcsr3, _tmcsrh3$/;" v
+_tmcsr4 mb91465k.h /^ .GLOBAL _tmcsrl3, _tmrlr4, _tmr4, _tmcsr4, _tmcsrh4, _tmcsrl4$/;" v
+_tmcsr5 mb91465k.h /^ .GLOBAL _tmrlr5, _tmr5, _tmcsr5, _tmcsrh5, _tmcsrl5, _tmrlr6$/;" v
+_tmcsr6 mb91465k.h /^ .GLOBAL _tmr6, _tmcsr6, _tmcsrh6, _tmcsrl6, _tmrlr7, _tmr7$/;" v
+_tmcsrh0 mb91465k.h /^ .GLOBAL _tmr0, _tmcsr0, _tmcsrh0, _tmcsrl0, _tmrlr1, _tmr1$/;" v
+_tmcsrh1 mb91465k.h /^ .GLOBAL _tmcsr1, _tmcsrh1, _tmcsrl1, _tmrlr2, _tmr2, _tmcsr2$/;" v
+_tmcsrh4 mb91465k.h /^ .GLOBAL _tmcsrl3, _tmrlr4, _tmr4, _tmcsr4, _tmcsrh4, _tmcsrl4$/;" v
+_tmcsrh5 mb91465k.h /^ .GLOBAL _tmrlr5, _tmr5, _tmcsr5, _tmcsrh5, _tmcsrl5, _tmrlr6$/;" v
+_tmcsrh6 mb91465k.h /^ .GLOBAL _tmr6, _tmcsr6, _tmcsrh6, _tmcsrl6, _tmrlr7, _tmr7$/;" v
+_tmcsrh7 mb91465k.h /^ .GLOBAL _tmcsr7, _tmcsrh7, _tmcsrl7, _tcdt0, _tccs0, _tcdt1$/;" v
+_tmcsrl0 mb91465k.h /^ .GLOBAL _tmr0, _tmcsr0, _tmcsrh0, _tmcsrl0, _tmrlr1, _tmr1$/;" v
+_tmcsrl1 mb91465k.h /^ .GLOBAL _tmcsr1, _tmcsrh1, _tmcsrl1, _tmrlr2, _tmr2, _tmcsr2$/;" v
+_tmcsrl2 mb91465k.h /^ .GLOBAL _tmcsrh2, _tmcsrl2, _tmrlr3, _tmr3, _tmcsr3, _tmcsrh3$/;" v
+_tmcsrl5 mb91465k.h /^ .GLOBAL _tmrlr5, _tmr5, _tmcsr5, _tmcsrh5, _tmcsrl5, _tmrlr6$/;" v
+_tmcsrl6 mb91465k.h /^ .GLOBAL _tmr6, _tmcsr6, _tmcsrh6, _tmcsrl6, _tmrlr7, _tmr7$/;" v
+_tmcsrl7 mb91465k.h /^ .GLOBAL _tmcsr7, _tmcsrh7, _tmcsrl7, _tcdt0, _tccs0, _tcdt1$/;" v
+_tmr2 mb91465k.h /^ .GLOBAL _tmcsr1, _tmcsrh1, _tmcsrl1, _tmrlr2, _tmr2, _tmcsr2$/;" v
+_tmr3 mb91465k.h /^ .GLOBAL _tmcsrh2, _tmcsrl2, _tmrlr3, _tmr3, _tmcsr3, _tmcsrh3$/;" v
+_tmr4 mb91465k.h /^ .GLOBAL _tmcsrl3, _tmrlr4, _tmr4, _tmcsr4, _tmcsrh4, _tmcsrl4$/;" v
+_tmr5 mb91465k.h /^ .GLOBAL _tmrlr5, _tmr5, _tmcsr5, _tmcsrh5, _tmcsrl5, _tmrlr6$/;" v
+_tmrlr1 mb91465k.h /^ .GLOBAL _tmr0, _tmcsr0, _tmcsrh0, _tmcsrl0, _tmrlr1, _tmr1$/;" v
+_tmrlr2 mb91465k.h /^ .GLOBAL _tmcsr1, _tmcsrh1, _tmcsrl1, _tmrlr2, _tmr2, _tmcsr2$/;" v
+_tmrlr3 mb91465k.h /^ .GLOBAL _tmcsrh2, _tmcsrl2, _tmrlr3, _tmr3, _tmcsr3, _tmcsrh3$/;" v
+_tmrlr4 mb91465k.h /^ .GLOBAL _tmcsrl3, _tmrlr4, _tmr4, _tmcsr4, _tmcsrh4, _tmcsrl4$/;" v
+_tmrlr7 mb91465k.h /^ .GLOBAL _tmr6, _tmcsr6, _tmcsrh6, _tmcsrl6, _tmrlr7, _tmr7$/;" v
+_treqr124 mb91465k.h /^ .GLOBAL _if2dtb_swp124, _if2dtb_swp24, _if2dtb_swp14, _treqr124, _treqr24, _treqr14$/;" v
+_treqr24 mb91465k.h /^ .GLOBAL _if2dtb_swp124, _if2dtb_swp24, _if2dtb_swp14, _treqr124, _treqr24, _treqr14$/;" v
+_wait64_loop Start91460.asm /^_wait64_loop:$/;" l
+_wpr mb91465k.h /^ .GLOBAL _ctbr, _clkr, _wpr, _divr0, _divr1, _plldivm$/;" v
+_wtcer mb91465k.h /^ .GLOBAL _oscc2, _oscs2, _porten, _wtcer, _wtcr, _wtbr$/;" v
+_wtcr mb91465k.h /^ .GLOBAL _oscc2, _oscs2, _porten, _wtcer, _wtcr, _wtbr$/;" v
+_wtmr mb91465k.h /^ .GLOBAL _wthr, _wtmr, _wtsr, _csvtr, _csvcr, _cscfg$/;" v
+_wtsr mb91465k.h /^ .GLOBAL _wthr, _wtmr, _wtsr, _csvtr, _csvcr, _cscfg$/;" v
+clock_startup Start91460.asm /^clock_startup:$/;" l
+copy_iram1 Start91460.asm /^copy_iram1: $/;" l
+copy_iram_end Start91460.asm /^copy_iram_end: $/;" l
+copy_rom1 Start91460.asm /^copy_rom1:$/;" l
+copy_rom2 Start91460.asm /^copy_rom2:$/;" l
+copy_rom_end Start91460.asm /^copy_rom_end:$/;" l
+data_clr0 Start91460.asm /^data_clr0:$/;" l
+data_clr1 Start91460.asm /^data_clr1:$/;" l
+data_clr2 Start91460.asm /^data_clr2:$/;" l
+data_clr_end Start91460.asm /^data_clr_end:$/;" l
+emu_sram_cs_mb91461r Start91460.asm /^emu_sram_cs_mb91461r: $/;" l
+emu_sram_cs_mb91461r Start91460.asm /^emu_sram_cs_mb91461r:$/;" l
+fill_sstack1 Start91460.asm /^fill_sstack1:$/;" l
+fill_sstack2 Start91460.asm /^fill_sstack2:$/;" l
+fill_sstack_end Start91460.asm /^fill_sstack_end:$/;" l
+fill_ustack1 Start91460.asm /^fill_ustack1:$/;" l
+fill_ustack2 Start91460.asm /^fill_ustack2:$/;" l
+fill_ustack_end Start91460.asm /^fill_ustack_end:$/;" l
+gearDownLoop Start91460.asm /^gearDownLoop: $/;" l
+gearUpLoop Start91460.asm /^gearUpLoop: $/;" l
+hseq_1 Flash.h 13;" d
+hseq_2 Flash.h 14;" d
+main MAIN.c /^void main(void)$/;" f
+mainNotStopped Start91460.asm /^mainNotStopped: $/;" l
+mainStabTime Start91460.asm /^ mainStabTime: ; Wait for stabilisation time$/;" l
+noClockStartup Start91460.asm /^noClockStartup:$/;" l
+notOnPll Start91460.asm /^notOnPll:$/;" l
+notOnSubClock Start91460.asm /^notOnSubClock:$/;" l
+smd_cs Start91460.asm /^smd_cs: $/;" l
+smd_cs Start91460.asm /^smd_cs:$/;" l
+smd_cs_mb91461r Start91460.asm /^smd_cs_mb91461r:$/;" l
+smd_tbr Start91460.asm /^smd_tbr: $/;" l
+start_main Start91460.asm /^start_main:$/;" l
+startnop Start91460.asm /^startnop: $/;" l
+subStabTime Start91460.asm /^subStabTime: $/;" l
+xFFFFFFEF Flash.c /^ ANDCCR #0xFFFFFFEF ; Clear Interrupt Flag$/;" v
projects / pyfrprog.git / commitdiff