1 /* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
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2 /* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
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3 /* ELIGIBILITY FOR ANY PURPOSES. */
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4 /* (C) Fujitsu Microelectronics Europe GmbH */
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5 ;=========================================================================================
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7 ;=========================================================================================
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14 ; 4.1 Controller device
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15 ; 4.2 Boot / flash security
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16 ; 4.3 Stack type and stack size
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17 ; 4.4 Copy code from flash to I-RAM
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19 ; 4.6 Low-level library interface
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20 ; 4.7 Clock Configuration
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21 ; 4.7.1 Clock selection
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22 ; 4.7.2 Select Clock Modulator
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23 ; 4.8 External bus interface
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24 ; 4.8.1 Select chipselect
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25 ; 4.8.2 Set memory addressing for chipselects
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26 ; 4.8.3 Configure chipselect area
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27 ; 4.8.4 Set wait cycles for chipselects
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28 ; 4.8.5 Configure chipselects SDRAM memory only
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29 ; 4.8.6 Referesh control register RCR
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30 ; 4.8.7 Terminal and timing control register
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31 ; 4.8.8 Enable / disable I-cache
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32 ; 4.8.9 Enable CACHE for chipselect
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33 ; 4.8.10 Select external bus mode (data lines)
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34 ; 4.8.11 Select external bus mode (address lines)
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35 ; 4.8.12 Select external bus mode (control signals)
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37 ; 5 Definitions of Configurations
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39 ; 6 Section and data declaration
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40 ; 6.1 Define stack size
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41 ; 6.2 Define sections
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44 ; 7.1 Initialise stack pointer and table base register
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45 ; 7.2 Check for CSV reset and set CSV
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46 ; 7.3 Check clock condition
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47 ; 7.4 Restore default settings after reset
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48 ; 7.4.1 Disable clock modulator
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49 ; 7.4.2 Check if running on sub clock, change to main clock
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50 ; 7.4.3 Disable sub clock
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51 ; 7.4.4 Check if running on PLL, gear down PLL
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53 ; 7.4.6 Set to main clock
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54 ; 7.5 Set memory controller
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56 ; 7.6.1 Set Voltage Regulator Settings
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57 ; 7.6.2 Power on clock modulator - clock modulator part I
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58 ; 7.6.3 Set CLKR register w/o clock mode
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60 ; 7.6.5 Wait for PLL oscillation stabilisation
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62 ; 7.6.6.1 Set CPU and peripheral clock
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63 ; 7.6.6.2 Set external bus interface clock
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64 ; 7.6.6.3 Set CAN clock prescaler
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65 ; 7.6.6.4 Switch main clock mode
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66 ; 7.6.6.5 Switch sub clock mode
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67 ; 7.6.6.6 Switch to PLL mode
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68 ; 7.6.7 Enable frequncy modulation - clock modulator part II
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69 ; 7.7 Set BusInterface
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70 ; 7.7.1 Disable all CS
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71 ; 7.7.2 Clear TCR register
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80 ; 7.7.11 Set special SDRAM config register
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81 ; 7.7.12 set Port function register
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82 ; 7.7.13 Set TCR register
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83 ; 7.7.14 Enable cache for selected CS
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84 ; 7.7.15 Set SDRAM referesh control register
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85 ; 7.7.16 Enable used CS
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86 ; 7.7.17 I-cache on/off
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87 ; 7.7.18 Set port function register to general as I/O-port
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88 ; 7.8 Copy code from flash to I-RAM
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91 ; 7.11 Copy Init section from ROM to RAM
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92 ; 7.12 C library initialization
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93 ; 7.13 Call C++ constructors
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94 ; 7.14 Call main routine
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95 ; 7.15 Return from main function
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97 ;=========================================================================================
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99 ;=========================================================================================
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100 ; Fujitsu Microelectronics Europe GmbH
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101 ; http://emea.fujitsu.com/microelectronics
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103 ; The following software is for demonstration purposes only. It is not fully
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104 ; tested, nor validated in order to fullfill its task under all circumstances.
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105 ; Therefore, this software or any part of it must only be used in an evaluation
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106 ; laboratory environment.
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107 ; This software is subject to the rules of our standard DISCLAIMER, that is
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108 ; delivered with our SW-tools on the Fujitsu Microcontrollers CD/DVD (V3.4 or
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109 ; higher "\START.HTM") or on our Internet Pages:
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110 ; http://www.fme.gsdc.de/gsdc.htm
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111 ; http://emea.fujitsu.com/microelectronics
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113 ;=========================================================================================
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115 ;=========================================================================================
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117 ;=========================================================================================
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118 ; MB914xx (FR60 CORE ONLY) Series C Compiler's
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120 ; Startup file for memory and basic controller initialisation
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121 ;=========================================================================================
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124 ; 2005-04-18 V1.0 UMa Release first version
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125 ; 2005-06-17 V1.1 UMa Added bus interface, modified c++ startup
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126 ; 2005-06-28 V1.2 UMa minor changes
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127 ; 2005-07-27 V1.3 UMa default values changed
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128 ; 2005-10-04 V1.4 UMa changed code 'Call main Routine'
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129 ; Added secutiy section for MB91F467D
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130 ; Added Flash Access Read Timing setting section;
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131 ; 2005-10-04 V1.5 UMa Added Flash Controller Section
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132 ; 2005-10-28 V1.6 UMa Check for CSV reset
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133 ; 2005-11.16 V1.7 UMa Monitor Debugger support added: Copy of intvect Table
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134 ; Ext. Int 0 as abort function
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135 ; Changed PLL-Startup, Reset HWWD added
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136 ; 2005-11-16 V1.7 UMa Examples for MUL_G changed
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137 ; 2006-02-14 V1.8 UMa mb91464a added
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138 ; Settings for Clock Spervisor added
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139 ; Name of Section SECURITY changed to SECURITY_VECTORS
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140 ; Example values for gear-up changed
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141 ; 2006-03-17 V1.9 UMa Changed Startup for Monitor Debugger
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142 ; 2006-04-24 v2.0 UMa Added MB91465K and MB91469G
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143 ; 2006-05-03 v2.1 UMa Added MB91461R; removed MB91V460A
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144 ; Added settings for the external bus-interface
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145 ; 2006-07-28 v2.2 UMa Added I-RAM copy function (ROM -> IRAM)
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146 ; Added default settings for FLASH Access Read Timing
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148 ; Changed default settings for FLASH cache configuration
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150 ; Changed check for clock startup
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151 ; 2006-08-16 v2.3 MVo Corrected Boot Security Sector Addresses for MB91469G
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152 ; 2006-10-06 v2.4 UMa Added new devices
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153 ; Corrected typo in I_RAM to flash copy function
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154 ; Changed default settings for flash cache configuration
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155 ; Changed comments for SDRAM bus interface configuration
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156 ; Changed comments and default setting of CAN Prescaler
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157 ; Added Stack filler
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158 ; Added Settings for REGSEL Register
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159 ; 2007-02-13 v2.5 UMa Introduction of default configurations
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160 ; Changed I_RAM to flash copy function
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163 ;=========================================================================================
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165 ;=========================================================================================
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167 ; CHECK ALL OPTIONS WHETHER THEY FIT TO THE APPLICATION;
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169 ; Configure this startup file in the "Settings" section. Search for
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170 ; comments with leading "; <<<". This points to the items to be set.
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171 ;=========================================================================================
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178 ;=========================================================================================
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179 ; 4.1 Controller Device
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180 ;=========================================================================================
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181 #set MB91464A 2 ; MB91460 series
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183 #set MB91467B 10 ; MB91460 series
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185 #set MB91467C 11 ; MB91460 series
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187 #set MB91467D 4 ; MB91460 series
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189 #set MB91469G 6 ; MB91460 series
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191 #set MB91465K 3 ; MB91460 series
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193 #set MB91463N 8 ; MB91460 series
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195 #set MB91461R 1 ; MB91460 series
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196 #set MB91467R 5 ; MB91460 series
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198 #set MB91465X 9 ; MB91460 series
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200 #set others 7 ; MB91460 series
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204 #set DEVICE MB91465K ; <<< select device
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206 ;=========================================================================================
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207 ; 4.2 Boot / Flash Security
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208 ;=========================================================================================
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210 #set BOOT_FLASH_SEC OFF ; <<< BOOT and Flash Security Vector
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212 ; The flash devices have two flash and two boot security vectors. It is important to set
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213 ; the four vectors correctly. Otherwise it might be possible, that the flash device is
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214 ; not accessible any more via the bootrom. Please read carefully the hardware manual.
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216 ; OFF: The security feature is switch off. The section SECURITY_VECTORS is reserved and
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217 ; the vectors are set.
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218 ; ON: IMPORTANT! The security vectors are not set. But the section SECURITY_VECTORS
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221 ; Note: This feature is not supported by every device. Please check the data sheet. This
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222 ; feature is not available on MB91461R.
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224 ;=========================================================================================
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225 ; 4.3 Stack Type and Stack Size
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226 ;=========================================================================================
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228 #set USRSTACK 0 ; user stack: for main program
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229 #set SYSSTACK 1 ; system stack: for main program and
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233 #set STACKUSE SYSSTACK ; <<< set active stack
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235 #set STACK_RESERVE ON ; <<< reserve stack area in
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237 #set STACK_SYS_SIZE 0x400-4 ; <<< byte size of System stack
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238 #set STACK_USR_SIZE 0x2 ; <<< byte size of User stack
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240 #set STACK_FILL OFF ; <<< fills the stack area with pattern
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241 #set STACK_PATTERN 0x55AA6699 ; <<< the pattern to write to stack
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243 ; - If the active stack is set to SYSSTACK, it is used for main program and interrupts.
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244 ; In this case, the user stack could be set to a dummy size. If the active stack is
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245 ; set to user stack, it is used for the main program but the system stack is
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246 ; automatically activated, if an interrupt is serviced. Both stack areas must have a
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248 ; - If STACK_RESERVE is ON, the sections USTACK and SSTACK are reserved in this module.
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249 ; Otherwise, they have to be reserved in other modules. If STACK_RESERVE is OFF, the
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250 ; size definitions STACK_SYS_SIZE and STACK_USR_SIZE have no meaning.
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251 ; - Even if they are reverved in other modules, they are still initialised in this
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254 ; Note: Several library functions require quite a big stack (due to ANSI).
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255 ; Check the stack information files (*.stk) in the LIB\911 directory.
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257 ;=========================================================================================
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258 ; 4.4 Copy code from Flash to I-RAM
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259 ;=========================================================================================
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261 #set I_RAM ON ; <<< select if code in section IRAM
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264 ; If this option is activated code located in the section IRAM is copied during startup
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265 ; from ROM to the instruction-RAM. The code is linked for the instruction-RAM.
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267 ;=========================================================================================
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268 ; 4.5 Low-Level Library Interface
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269 ;=========================================================================================
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271 #set CLIBINIT OFF ; <<< select ext. libray usage
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273 ; This option has only to be set, if stream-IO/standard-IO function of the C-libraray
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274 ; have to be used (printf(), fopen()...). This also requires low-level functions to be
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275 ; defined by the application software.
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276 ; For other library functions like (e.g. sprintf()) all this is not necessary. However,
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277 ; several functions consume a large amount of stack.
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279 ;=========================================================================================
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280 ; 4.6 C++ start-up
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281 ;=========================================================================================
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283 #set CPLUSPLUS OFF ; <<< activate if c++ files are used
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285 ; In the C++ specifications, when external or static objects are used, a constructor
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286 ; must be called followed by the main function. Because four-byte pointers to the main
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287 ; function are stored in the EXT_CTOR_DTOR section, call a constructor sequentially from
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288 ; the lower address of the four addresses in that section. If using C++ sources,
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289 ; activate this function to create the section EXT_CTOR_DTOR.
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291 ;=========================================================================================
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292 ; 4.7 Clock Configuration
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293 ;=========================================================================================
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294 ;=========================================================================================
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295 ; 4.7.1 Clock Selection
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296 ;=========================================================================================
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298 ; No clock settings
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301 ; Sub-oscillation input: 32 kHz
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302 #set SUB_32KHZ_CPU__32KHZ_PER_32KHZ_EXT_32KHZ_CAN__2MHZ 0x11
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304 ; Oscillation input: 4 MHz
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305 #set MAIN_4MHZ_CPU___2MHZ_PER__1MHZ_EXT__1MHZ_CAN__2MHZ 0x21
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306 #set PLL_4MHZ__CPU__48MHZ_PER_16MHZ_EXT_24MHZ_CAN_16MHZ 0x22
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307 #set PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ 0x23
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308 #set PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_27MHZ_CAN_20MHZ 0x24
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309 #set PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_40MHZ_CAN_20MHZ 0x25
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310 #set PLL_4MHZ__CPU__96MHZ_PER_16MHZ_EXT_48MHZ_CAN_16MHZ 0x26 ;not MB91V460, ...
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311 #set PLL_4MHZ__CPU_100MHZ_PER_20MHZ_EXT_50MHZ_CAN_20MHZ 0x27 ;not MB91V460, ...
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313 ; MB91461R only: Oscillation input: 10 MHz
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314 #set PLL_10MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ 0x41
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316 ; MB91461R only: Oscillation input: 20 MHz
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317 #set PLL_20MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ 0x51
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320 #set CLOCK_USER 0x61
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324 #set CLOCKSPEED PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ
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325 ; ; <<< Select clock configuration
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327 ; There are different default configurations available, where all necessary settings for
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328 ; clocks and the related registers are made. Beside this configurations, there is the
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329 ; possibility to define a user configuration in the chapter "Definition of
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332 ; - NO_CLOCK means:
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333 ; The clock registers are not set by the start-up file.
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335 ; - PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ means:
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336 ; Main oszillation = 4 MHz, PLL is activated
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337 ; CPU clock (CLKB) = 64 MHZ
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338 ; Peripheral clock (CLKP) = 16 MHZ
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339 ; Ext. bus clock (CLKT) = 32 MHZ
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340 ; CAN clock (CLKCAN) = 16 MHz, using PLLx
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343 ; The user configuration definded in the chapter "Definition of Configurations" is set.
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345 ; Note: Not all frequencies are supported by every device. Please see the hardware
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348 ;=========================================================================================
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349 ; 4.7.2 Select Clock Modulator
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350 ;=========================================================================================
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352 #set CLOMO OFF ; <<< Enable /disable clock modulator
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354 #set CMPR 0x026F ; <<< Ref. to the data sheet, CMPR
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356 ; Please refer to the data sheet of the device if you enable clock modulation. The
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357 ; register CMPR dependant on the PLL-Clock.
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359 ; Note: If the CLKCAN source is set either to main oscillator or to PLL output then the
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360 ; clock for the CAN is not influenced by the clock modulation. If the CLKCAN
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361 ; source is set CPU clock (CLKB) then the clock for the CAN is also modulated (if
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362 ; the clock modulator is enabled).
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364 ; Note: If the clock modulator is enabled, the wait states of the internal flash wait
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365 ; states must be adapted to maximum frequency. Please check the wait states
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368 ; Note: This feature is not supported by every device, e.g. MB91461. Please check the
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371 ;=========================================================================================
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372 ; 4.8 External Bus Interface
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374 ; The rest of the configuration is only applicable for devices with an external bus
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377 ; If the device does not offer an external bus interface, the configuration can be
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378 ; stoped at this point.
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380 ;=========================================================================================
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382 #set EXTBUS DEFAULT ; <<< Ext. Bus on/off
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384 ; ON - The ext. bus interface is enabled and is configured as
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387 ; OFF - The ext. bus interface is diabled. The port function
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388 ; registers are set to general I/O. The registers of
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389 ; ext. bus interface will not be touched by the start-up
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391 ; Be aware, that the device might be conifgured in ext.
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392 ; bus mode by default after reset.
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394 ; DEFAULT - Neither the register nor the respective port function
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395 ; registers are touched by the start-up file.
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396 ; Be aware, that the device might be conifgured in ext.
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397 ; bus mode by default after reset.
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400 ; Note: This feature is not supported by every device. Please check the data sheet. The
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401 ; following devices for example do not offer an external bus interface: MB91464A,
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402 ; MB91467C, MB91465K, MB91463N, MB91465X.
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404 ;=========================================================================================
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405 ; 4.8.1 Select Chipselect (Only EXTBUS == ON)
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406 ;=========================================================================================
\r
408 #set CS0 OFF ; <<< select CS (ON/OFF)
\r
409 #set CS1 OFF ; <<< select CS (ON/OFF)
\r
410 #set CS2 OFF ; <<< select CS (ON/OFF)
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411 #set CS3 OFF ; <<< select CS (ON/OFF)
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412 #set CS4 OFF ; <<< select CS (ON/OFF)
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413 #set CS5 OFF ; <<< select CS (ON/OFF)
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414 #set CS6 OFF ; <<< select CS (ON/OFF)
\r
415 #set CS7 OFF ; <<< select CS (ON/OFF)
\r
416 #set SDRAM OFF ; <<< select if a SDRAM is connected
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419 #set ENACSX B'00000000 ; <<< set CS, ENACSX
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421 ; ||||||||__ CS0 bit, enable/disable CS0 (1/0)
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422 ; |||||||___ CS1 bit, enable/disable CS1 (1/0)
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423 ; ||||||____ CS2 bit, enable/disable CS2 (1/0)
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424 ; |||||_____ CS3 bit, enable/disable CS3 (1/0)
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425 ; ||||______ CS4 bit, enable/disable CS4 (1/0)
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426 ; |||_______ CS5 bit, enable/disable CS5 (1/0)
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427 ; ||________ CS6 bit, enable/disable CS6 (1/0)
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428 ; |_________ CS7 bit, enable/disable CS7 (1/0)
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430 ; Note: If the SWB Monitor Debugger is used, set the CS1 (external RAM only) or CS0 and
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431 ; CS 1 (external RAM and flash) to off.
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433 ; Note: Not all Chipselects are supported by the different devices. Please check the
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436 ;=========================================================================================
\r
437 ; 4.8.2 Set memory addressing for Chipselects (only EXTBUS == ON)
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438 ;=========================================================================================
\r
440 #set AREASEL0 0x0000 ; <<< set start add. for CS0, ASR0
\r
441 #set AREASEL1 0x0000 ; <<< set start add. for CS1, ASR1
\r
442 #set AREASEL2 0x0000 ; <<< set start add. for CS2, ASR2
\r
443 #set AREASEL3 0x0000 ; <<< set start add. for CS3, ASR3
\r
444 #set AREASEL4 0x0000 ; <<< set start add. for CS4, ASR4
\r
445 #set AREASEL5 0x0000 ; <<< set start add. for CS5, ASR5
\r
446 #set AREASEL6 0x0000 ; <<< set start add. for CS6, ASR6
\r
447 #set AREASEL7 0x0000 ; <<< set start add. for CS7, ASR7
\r
449 ; Configure the starting address of each used Chipselect. Chipselects which are not used
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450 ; (not set to ON in "Select Chipselect") need not be set (setting ignored).
\r
452 ; NOTE: Just the upper 16-bit of the start address must be set, e.g. when using start
\r
453 ; address 0x00080000 set 0x0008.
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455 ;=========================================================================================
\r
456 ; 4.8.3 Configure Chipselect Area (only EXTBUS == ON)
\r
457 ;=========================================================================================
\r
459 #set CONFIGCS0 B'0000000000000000 ; <<< Config. CS0, ACR0
\r
460 #set CONFIGCS1 B'0000000000000000 ; <<< Config. CS1, ACR1
\r
461 #set CONFIGCS2 B'0000000000000000 ; <<< Config. CS2, ACR2
\r
462 #set CONFIGCS3 B'0000000000000000 ; <<< Config. CS3, ACR3
\r
463 #set CONFIGCS4 B'0000000000000000 ; <<< Config. CS4, ACR4
\r
464 #set CONFIGCS5 B'0000000000000000 ; <<< Config. CS5, ACR5
\r
465 #set CONFIGCS6 B'0000000000000000 ; <<< Config. CS6, ACR6
\r
466 #set CONFIGCS7 B'0000000000000000 ; <<< Config. CS7, ACR7
\r
468 ; ||||||||||||||||__ TYP0 bit, TYP0-4 bits select access type
\r
469 ; |||||||||||||||___ TYP1 bit
\r
470 ; ||||||||||||||____ TYP2 bit
\r
471 ; |||||||||||||_____ TYP3 bit
\r
472 ; ||||||||||||______ LEND bit, select little '1' or big endian '0'
\r
473 ; |||||||||||_______ WREN bit, en-/disable (1/0) Write access
\r
474 ; ||||||||||________ PFEN bit, en-/disable (1/0) pre-fetch
\r
475 ; |||||||||_________ SREN bit, en-/disable (1/0) share of BRQ & BGRNTX
\r
476 ; ||||||||__________ BST0 bit, BSTx bits select burst size
\r
477 ; |||||||___________ BST1 bit
\r
478 ; ||||||____________ DBW0 bit, DBWx select data bus width
\r
479 ; |||||_____________ DBW1 bit
\r
480 ; ||||______________ ASZ0 bit, ASZx bits select address size of CS
\r
481 ; |||_______________ ASZ1 bit
\r
482 ; ||________________ ASZ2 bit
\r
483 ; |_________________ ASZ3 bit
\r
487 ; TYP3 TYP2 TYP1 TYP0 : Select access type of each CS
\r
488 ; 0 0 X X : Normal access (asynchronous SRAM, I/O,
\r
489 ; single/page/busrt-ROM/FLASH)
\r
490 ; 0 1 X X : Address/data multiplexed (8bit / 16bit bus width only)
\r
491 ; 0 X X 0 : WAIT insertion by RDY disabled
\r
492 ; 0 X X 1 : WAIT insertion by RDY enabled
\r
493 ; 0 X 0 X : The WR0X pin to the WR3X pin are used as write strobes
\r
494 ; (WRX is fixed at H-Level)
\r
495 ; 0 X 1 X : The WRX pin is used as write strobe
\r
496 ; 1 0 0 0 : Memory type A: SDRAM/FCRAM (Auto pre-charge used)
\r
497 ; 1 0 0 1 : Memory type B: FCRAM (Auto pre-charge used)
\r
498 ; 1 0 1 0 : setting not allowed
\r
499 ; 1 0 1 1 : setting not allowed
\r
500 ; 1 1 0 0 : setting not allowed
\r
501 ; 1 1 0 1 : setting not allowed
\r
502 ; 1 1 1 0 : setting not allowed
\r
503 ; 1 1 1 1 : mask area setting
\r
505 ; LEND : select BYTE ordering
\r
507 ; 1 : Little endian
\r
509 ; WREN : enable or disable write access
\r
513 ; PFEN : Enable or disable the pre-fetch
\r
517 ; SREN : Enable or disable the sharing of BRQ and BGRNTX
\r
519 ; 1 : enabled (CSx pin High-Z)
\r
521 ; BST1 BST0 : set burst size of chip select area
\r
522 ; 0 0 : 1 burst (single access)
\r
523 ; 0 1 : 2 bursts (Address boundary 1 bit)
\r
524 ; 1 0 : 4 bursts (Address boundary 2 bit)
\r
525 ; 1 1 : 8 bursts (Address boundary 3 bit)
\r
527 ; DBW1 DBW0 : Set data bus width
\r
528 ; 0 0 : 8-bit (BYTE access)
\r
529 ; 0 1 : 16-bit (HALF-WORD access)
\r
530 ; 1 0 : 32-bit (WORD access)
\r
533 ; ASZ3 ASZ2 ASZ1 ASZ0 : Select memory size of each chipselect
\r
534 ; 0 0 0 0 : 64 Kbyte (0x01.0000 bytes; use ASR A[31:16] bits)
\r
535 ; 0 0 0 1 : 128 Kbyte (0x02.0000 bytes; use ASR A[31:17] bits)
\r
536 ; 0 0 1 0 : 256 Kbyte (0x04.0000 bytes; use ASR A[31:18] bits)
\r
537 ; 0 0 1 1 : 512 Kbyte (0x08.0000 bytes; use ASR A[31:19] bits)
\r
538 ; 0 1 0 0 : 1 Mbyte (0x10.0000 bytes; use ASR A[31:20] bits)
\r
539 ; 0 1 0 1 : 2 Mbyte (0x20.0000 bytes; use ASR A[31:21] bits)
\r
540 ; 0 1 1 0 : 4 Mbyte (0x40.0000 bytes; use ASR A[31:22] bits)
\r
541 ; 0 1 1 1 : 8 Mbyte (0x80.0000 bytes; use ASR A[31:23] bits)
\r
542 ; 1 0 0 0 : 16 Mbyte (0x100.0000 bytes; use ASR A[31:24] bits)
\r
543 ; 1 0 0 1 : 32 Mbyte (0x200.0000 bytes; use ASR A[31:25] bits)
\r
544 ; 1 0 1 0 : 64 Mbyte (0x400.0000 bytes; use ASR A[31:26] bits)
\r
545 ; 1 0 1 1 : 128 Mbyte (0x800.0000 bytes; use ASR A[31:27] bits)
\r
546 ; 1 1 0 0 : 256 Mbyte (0x1000.0000 bytes; use ASR A[31:28] bits)
\r
547 ; 1 1 0 1 : 512 Mbyte (0x2000.0000 bytes; use ASR A[31:29] bits)
\r
548 ; 1 1 1 0 : 1024 Mbyte(0x4000.0000 bytes; use ASR A[31:30] bits)
\r
549 ; 1 1 1 1 : 2048 Mbyte(0x8000.0000 bytes; use ASR A[31] bit)
\r
551 ;=========================================================================================
\r
552 ; 4.8.4 Set Wait cycles for Chipselects for ordinary businterface (only EXTBUS == ON)
\r
553 ;=========================================================================================
\r
555 ; Ordinary bus interface (w/o SDRAM and FRAM) (ACRx_Type = 0xxx)
\r
557 #set WAITREG0 B'0000000000000000 ; <<< CS0 Waitstates, AWR0
\r
558 #set WAITREG1 B'0000000000000000 ; <<< CS1 Waitstates, AWR1
\r
559 #set WAITREG2 B'0000000000000000 ; <<< CS2 Waitstates, AWR2
\r
560 #set WAITREG3 B'0000000000000000 ; <<< CS3 Waitstates, AWR3
\r
561 #set WAITREG4 B'0000000000000000 ; <<< CS4 Waitstates, AWR4
\r
562 #set WAITREG5 B'0000000000000000 ; <<< CS5 Waitstates, AWR5
\r
564 ; ||||||||||||||||__ W00 bit, RDY/WRY-> CSX hold cycle
\r
565 ; |||||||||||||||___ W01 bit, CSX->RDX/WRX setup extension cycle
\r
566 ; ||||||||||||||____ W02 bit, Address -> CSX Delay selection
\r
567 ; |||||||||||||_____ W03 bit, WR0X to WR3X/WRX outout timing
\r
568 ; ||||||||||||______ W04 bit, W04/W05 Write recovery cycle
\r
569 ; |||||||||||_______ W05 bit
\r
570 ; ||||||||||________ W06 bit, W06/07 Read -> Write idle cycle
\r
571 ; |||||||||_________ W07 bit selection
\r
572 ; ||||||||__________ W08 bit, W08-W11 Intra-page access cycle
\r
573 ; |||||||___________ W09 bit select (0-15 cycles)
\r
574 ; ||||||____________ W10 bit
\r
575 ; |||||_____________ W11 bit
\r
576 ; ||||______________ W12 bit, W12-W15 First access wait cycle
\r
577 ; |||_______________ W13 bit select (0-15 cycles)
\r
578 ; ||________________ W14 bit
\r
579 ; |_________________ W15 bit
\r
582 ; SDRAM and FRAM bus interface (ACRx_Type = 100x)
\r
584 #set WAITREG6 B'0000000000000000 ; <<< CS6 Waitstates, AWR6
\r
585 #set WAITREG7 B'0000000000000000 ; <<< CS7 Waitstates, AWR7
\r
587 ; ||||||||||||||||__ W00 bit, W0-W1 RAS precharge cycles
\r
588 ; |||||||||||||||___ W01 bit
\r
589 ; ||||||||||||||____ W02 bit, W2-W3 RAS active Time
\r
590 ; |||||||||||||_____ W03 bit
\r
591 ; ||||||||||||______ W04 bit, W4-W5 Write recovery cycle
\r
592 ; |||||||||||_______ W05 bit
\r
593 ; ||||||||||________ W06 bit, W6-W7 Read->Write idle cycle
\r
594 ; |||||||||_________ W07 bit
\r
595 ; ||||||||__________ W08 bit, W8-W10 CAS latency
\r
596 ; |||||||___________ W09 bit
\r
597 ; ||||||____________ W10 bit
\r
598 ; |||||_____________ W11 bit, reserved
\r
599 ; ||||______________ W12 bit, W12-W16 RAS-CAS delay
\r
600 ; |||_______________ W13 bit
\r
601 ; ||________________ W14 bit
\r
602 ; |_________________ W15 bit, reserved
\r
605 ; The bit meaning depends on the configured bus interface type. The bus interface can be
\r
606 ; configured for different memory types. Depending on the memory type, the wait register
\r
607 ; bits have a differnt meaning. CS0-5 should be configurable as ordinary bus interface
\r
608 ; (w/o SDRAM and FRAM) and CS6-7 should be configurable as SDRAM and FRAM. It is also
\r
609 ; possible and for some devices neccessary to configure other two chip selects as SDRAM
\r
610 ; or FRAM interface. In such a case be aware of the bit meanings.
\r
613 ; Ordinary bus interface (w/o SDRAM and FRAM) (ACRx_Type = 0xxx)
\r
614 ; --------------------------------------------------------------
\r
618 ; W00 : RDY/WRX -> CSX hold extension cycle
\r
622 ; W01 : CSX -> RDX/WRX setup extention cycle
\r
626 ; W02 : Address -> CSX Delay selection
\r
627 ; 0 : no delay selected
\r
628 ; 1 : delay selected
\r
630 ; W03 : WR0X to WR3X/WRX outout timing selection
\r
631 ; 0 : MCLK synchronous write output enable (ASX=L)
\r
632 ; 1 : Asynchronous write strobe output (norma operation)
\r
634 ; W05 W04 : select Write recovery cycle
\r
640 ; W07 W06 : Read -> Write idle cycle selection
\r
646 ; W11 W10 W09 W08 : Intra-page access cycle select (0-15 cycles)
\r
647 ; 0 0 0 0 : 0 Wait state
\r
648 ; 0 0 0 1 : 1 Auto-wait cycle
\r
649 ; 0 0 1 0 : 2 Auto-wait cycle
\r
651 ; 1 1 1 1 : 15 Auto wait cycles
\r
653 ; W15 W14 W13 W12 : First access wait cycle can be set (0-15 cycles)
\r
654 ; 0 0 0 0 : 0 Wait state
\r
655 ; 0 0 0 1 : 1 Auto-wait cycle
\r
656 ; 0 0 1 0 : 2 Auto-wait cycle
\r
658 ; 1 1 1 1 : 15 Auto wait cycles
\r
662 ; SDRAM and FRAM bus interface (ACRx_Type = 100x)
\r
663 ; -----------------------------------------------
\r
667 ; W01 W00 : RAS precharge cycles.
\r
673 ; W03 W02 : RAS active Time
\r
679 ; W05 W04 : set Write recovery cycle (1 - 4 cycles)
\r
685 ; W07 W06 : set Read -> Write idle Cycle (1 - 4 cycles)
\r
691 ; W10 W09 W08 : set CAS latency (1 - 8 cycles)
\r
697 ; W11 : RESERVED, ALWAYS WRITE 0 !
\r
699 ; W14 W13 W12 : set RAS-CAS delay (1 - 8 cycles)
\r
705 ; W15 : RESERVED, ALWAYS WRITE 0 !
\r
708 ; The bit meaning depends on the configured bus interface type
\r
710 ;=========================================================================================
\r
711 ; 4.8.5 Configure Chipselects for SDRAM memory only (only EXTBUS == ON and SDRAM)
\r
712 ;=========================================================================================
\r
714 #set MEMCON B'00000111 ; <<< set special SDRAM register, MCRA
\r
716 ; ||||||||__ ABS0 bit, set max. active banks (ABS1,0)
\r
717 ; |||||||___ ABS1 bit
\r
718 ; ||||||____ BANK bit, set number of banks connected to CS
\r
719 ; |||||_____ WBST bit, Write burst enable/disable
\r
720 ; ||||______ PSZ0 bit, Set page size (PSZ2-0)
\r
721 ; |||_______ PSZ1 bit
\r
722 ; ||________ PSZ2 bit
\r
723 ; |_________ reserved, always write 0
\r
725 ; When connecting SDRAM/FCRAM TYP3-0=1000 in ACRx register the following register must
\r
730 ; ABS1 ABS0 : Set maximum number of bank, active at same time
\r
736 ; BANK : Set number of connected SDRAM banks
\r
740 ; WBST : Write burst enable
\r
744 ; PSZ2 PSZ1 PS0 : Select page size of connected memory
\r
745 ; 0 0 0 : 8-bit column address = A0 to A7
\r
746 ; 0 0 1 : 9-bit column address = A0 to A8
\r
747 ; 0 1 0 : 10-bit column address = A0 to A9
\r
748 ; 0 1 1 : 11-bit column address = A0 to A9, A11
\r
749 ; 1 X X : setting disabled
\r
752 ;=========================================================================================
\r
753 ; 4.8.6 Referesh Control Register RCR (only EXTBUS == ON and SDRAM)
\r
754 ;=========================================================================================
\r
756 #set REFRESH B'1110001001000111 ; <<< set Refresh Control Register, RCR
\r
758 ; ||||||||||||||||__ TRC0 bit, set refresh cycle (TRC2-0)
\r
759 ; |||||||||||||||___ TRC1 bit
\r
760 ; ||||||||||||||____ TRC2 bit
\r
761 ; |||||||||||||_____ PON bit, set power-on control
\r
762 ; ||||||||||||______ RFC0 bit, set refresh count (RFC2-0)
\r
763 ; |||||||||||_______ RFC1 bit
\r
764 ; ||||||||||________ RFC2 bit
\r
765 ; |||||||||_________ BRST bit, set burst refresh control
\r
766 ; ||||||||__________ RFINT0 bit, set auto refresh interval
\r
767 ; |||||||___________ RFINT1 bit, (RFINT5-0)
\r
768 ; ||||||____________ RFINT2 bit
\r
769 ; |||||_____________ RFINT3 bit
\r
770 ; ||||______________ RFINT4 bit
\r
771 ; |||_______________ RFINT5 bit
\r
772 ; ||________________ RRLD bit, counter refresh strat control
\r
773 ; |_________________ SELF bit, self refresh control
\r
776 ; This register sets various SDRAM refresh controls. When SDRAM control is not set for
\r
777 ; any area, the setting of this register is meaningless, but do not change the register
\r
778 ; value at initial state. When a read is performed using a read-modify-write
\r
779 ; instruction, 0 always returns from the SELF, RRLD, and PON bits.
\r
784 ; TRC2 TRC1 TRC0 : Refresh Cycle
\r
794 ; PON : Power-on control
\r
796 ; 1 : power-on sequence started
\r
798 ; RFC2 RFC1 RFC0 : Refresh Count
\r
805 ; 1 1 0 : Setting disabled
\r
806 ; 1 1 1 : Refresh disabled
\r
808 ; BRST : Burst refresh control
\r
809 ; 0 : Decentralised refresh
\r
810 ; 1 : burst refresh
\r
812 ; RFINT[5-0] : auto refresh interval
\r
814 ; RRLD : Refresh counter Activation Control
\r
816 ; 1 : Autorefresh performed once, then value of RFINT reloaded
\r
818 ; SELF : Self refresh control
\r
819 ; 0 : auto refresh or power down
\r
820 ; 1 : Transitions to self-refresch mode
\r
822 ; NOTE: PON bit is set after the above setting. Do not set PON bit to 1 in the
\r
823 ; above setting. Otherwise the settings are not correct set.
\r
825 ;=========================================================================================
\r
826 ; 4.8.7 Terminal and Timing Control Register (only EXTBUS == ON)
\r
827 ;=========================================================================================
\r
829 #set TIMECONTR B'00000000 ; <<< set TCR register, TCR
\r
831 ; ||||||||__ RDW0 bit, set wait cycle reduction (RDW0,1)
\r
832 ; |||||||___ RDW1 bit
\r
833 ; ||||||____ OHT0 bit, set output hold delay (OHT1,0)
\r
834 ; |||||_____ OHT1 bit
\r
835 ; ||||______ reserved, always write 0
\r
836 ; |||_______ PCLR bit, prefetch buffer clear
\r
837 ; ||________ PSUS bit, prefetch suspend
\r
838 ; |_________ BREN bit, BRQ input enable
\r
840 ; This register controls the general functions of the external bus interface controller
\r
841 ; such as the common-pin function setting and timing control.
\r
845 ; RDW1 RDW0 : Wait cycle reduction
\r
846 ; 0 0 : Normal Wait (AWR0 - 7 setting)
\r
847 ; 0 1 : 1/2 of AWR0 - 7 setting value
\r
848 ; 1 0 : 1/4 of AWR0 - 7 setting value
\r
849 ; 1 1 : 1/8 of AWR0 - 7 setting value
\r
851 ; OHT1 OHT0 : Output hold selection bit
\r
852 ; 0 0 : Output performed at falling edge of SYSCLK/MCLK
\r
853 ; 0 1 : Output performed about 3ns after falling edge of SYSCLK/MCLK
\r
854 ; 1 0 : Output performed about 4ns after falling edge of SYSCLK/MCLK
\r
855 ; 1 1 : Output performed about 5ns after falling edge of SYSCLK/MCLK
\r
857 ; PCLR : Prefetch buffer all clear
\r
859 ; 1 : Prefetch buffer cleared
\r
861 ; PSUS : prefetch suspension bit
\r
862 ; 0 : Prefetch enabled
\r
863 ; 1 : Prefetch disabled
\r
865 ; BREN : BRQ input enable
\r
867 ; 1 : enabled, Bus sharing of BRQ/BGRNTX performed
\r
869 ; Note: This function is used to prevent an excessive access cycle wait while operating
\r
870 ; at a low-speed clock (such as while base clock operating at low speed or
\r
871 ; high frequency division rate for external bus clock).
\r
873 ;=========================================================================================
\r
874 ; 4.8.8 Enable/Disable I-CACHE (only EXTBUS == ON)
\r
875 ;=========================================================================================
\r
877 #set C1024 1 ; CACHE Size: 1024 BYTE
\r
878 #set C2048 2 ; CACHE Size: 2048 BYTE
\r
879 #set C4096 3 ; CACHE Size: 4096 BYTE
\r
882 #set CACHE OFF ; <<< Select use of cache
\r
883 #set CACHE_SIZE C4096 ; <<< Select size of cache, ISIZE
\r
885 ; It is possible to use cache functionality on the I-Bus on several devices. Please
\r
886 ; check the corresponidng data sheet if this feature is available on a certain device
\r
887 ; and for the size of the cache. This is the general cache configuration. It is possible
\r
888 ; to configure for each CS area, if the cache should be used.
\r
890 ; Note: This feature is not supported by every device. Please check the data sheet. The
\r
891 ; feature is for example supported by MB91461R, MB91469G.
\r
893 ;=========================================================================================
\r
894 ; 4.8.9 Enable CACHE for chipselect (only EXTBUS == ON)
\r
895 ;=========================================================================================
\r
897 #set CHEENA B'11111111 ; <<< en-/disable cache, CHER
\r
899 ; ||||||||__ CHE0 bit, CS0 area
\r
900 ; |||||||___ CHE1 bit, CS1 area
\r
901 ; ||||||____ CHE2 bit, CS2 area
\r
902 ; |||||_____ CHE3 bit, CS3 area
\r
903 ; ||||______ CHE4 bit, CS4 area
\r
904 ; |||_______ CHE5 bit, CS5 area
\r
905 ; ||________ CHE6 bit, CS6 area
\r
906 ; |_________ CHE7 bit, CS7 area
\r
908 ; Additional to the general cache enable setting, select which CS area should be used
\r
909 ; with cache functionality.
\r
911 ; Note: Not all Chipselects are supported by the different devices. Please check the
\r
914 ; Note: This feature is not supported by every device. Please check the data sheet. The
\r
915 ; Feature is supported by MB91461R, MB91469G.
\r
917 ;=========================================================================================
\r
918 ; 4.8.10 Select External bus mode (Data lines) (only EXTBUS == ON)
\r
919 ;=========================================================================================
\r
921 #set PFUNC0 B'11111111 ;<<< Data lines or GIO, PFR00
\r
923 ; ||||||||__ D24 / P00_0
\r
924 ; |||||||___ D25 / P00_1
\r
925 ; ||||||____ D26 / P00_2
\r
926 ; |||||_____ D27 / P00_3
\r
927 ; ||||______ D28 / P00_4
\r
928 ; |||_______ D29 / P00_5
\r
929 ; ||________ D30 / P00_6
\r
930 ; |_________ D31 / P00_7
\r
932 #set PFUNC1 B'11111111 ;<<< Data lines or GIO, PFR01
\r
934 ; ||||||||__ D16 / P01_0
\r
935 ; |||||||___ D17 / P01_1
\r
936 ; ||||||____ D18 / P01_2
\r
937 ; |||||_____ D19 / P01_3
\r
938 ; ||||______ D20 / P01_4
\r
939 ; |||_______ D21 / P01_5
\r
940 ; ||________ D22 / P01_6
\r
941 ; |_________ D23 / P01_7
\r
943 #set PFUNC2 B'11111111 ;<<< Data lines or GIO, PFR02
\r
945 ; ||||||||__ D8 / P02_0
\r
946 ; |||||||___ D9 / P02_1
\r
947 ; ||||||____ D10 / P02_2
\r
948 ; |||||_____ D11 / P02_3
\r
949 ; ||||______ D12 / P02_4
\r
950 ; |||_______ D13 / P02_5
\r
951 ; ||________ D14 / P02_6
\r
952 ; |_________ D15 / P02_7
\r
954 #set PFUNC3 B'11111111 ;<<< Data lines or GIO, PFR03
\r
956 ; ||||||||__ D0 / P03_0
\r
957 ; |||||||___ D1 / P03_1
\r
958 ; ||||||____ D2 / P03_2
\r
959 ; |||||_____ D3 / P03_3
\r
960 ; ||||______ D4 / P03_4
\r
961 ; |||_______ D5 / P03_5
\r
962 ; ||________ D6 / P03_6
\r
963 ; |_________ D7 / P03_7
\r
965 ; Select if the ports are set to
\r
966 ; 1 : External bus mode, I/O for data lines or
\r
967 ; 0 : General I/O port (GIO)
\r
969 ; Note: Not all data-lines are supported by the different devices. Please check the data
\r
972 ;=========================================================================================
\r
973 ; 4.8.11 Select External bus mode (Address lines) (only EXTBUS == ON)
\r
974 ;=========================================================================================
\r
976 #set PFUNC4 B'11111111 ;<<< Address lines or GIO, PFR04
\r
978 ; ||||||||__ A24 / P04_0
\r
979 ; |||||||___ A25 / P04_1
\r
980 ; ||||||____ A26 / P04_2
\r
981 ; |||||_____ A27 / P04_3
\r
982 ; ||||______ A28 / P04_4
\r
983 ; |||_______ A29 / P04_5
\r
984 ; ||________ A30 / P04_6
\r
985 ; |_________ A31 / P04_7
\r
987 #set PFUNC5 B'11111111 ;<<< Address lines or GIO, PFR05
\r
989 ; ||||||||__ A16 / P05_0
\r
990 ; |||||||___ A17 / P05_1
\r
991 ; ||||||____ A18 / P05_2
\r
992 ; |||||_____ A19 / P05_3
\r
993 ; ||||______ A20 / P05_4
\r
994 ; |||_______ A21 / P05_5
\r
995 ; ||________ A22 / P05_6
\r
996 ; |_________ A23 / P05_7
\r
998 #set PFUNC6 B'11111111 ;<<< Address lines or GIO, PFR06
\r
1000 ; ||||||||__ A8 / P06_0
\r
1001 ; |||||||___ A9 / P06_1
\r
1002 ; ||||||____ A10 / P06_2
\r
1003 ; |||||_____ A11 / P06_3
\r
1004 ; ||||______ A12 / P06_4
\r
1005 ; |||_______ A13 / P06_5
\r
1006 ; ||________ A14 / P06_6
\r
1007 ; |_________ A15 / P06_7
\r
1009 #set PFUNC7 B'11111111 ;<<< Address lines or GIO, PFR07
\r
1011 ; ||||||||__ A0 / P07_0
\r
1012 ; |||||||___ A1 / P07_1
\r
1013 ; ||||||____ A2 / P07_2
\r
1014 ; |||||_____ A3 / P07_3
\r
1015 ; ||||______ A4 / P07_4
\r
1016 ; |||_______ A5 / P07_5
\r
1017 ; ||________ A6 / P07_6
\r
1018 ; |_________ A7 / P07_7
\r
1020 ; Select if the ports are set to
\r
1021 ; 1 : External bus mode, I/O for address lines or
\r
1022 ; 0 : General I/O port (GIO)
\r
1024 ; Note: Not all address-lines are supported by the different devices. Please check the
\r
1027 ;=========================================================================================
\r
1028 ; 4.8.12 Select External bus mode (Control signals) (only EXTBUS == ON)
\r
1029 ;=========================================================================================
\r
1031 #set PFUNC8 B'11111111 ;<<< Control signals or GIO, PFR08
\r
1033 ; ||||||||__ WRX0 / P08_0
\r
1034 ; |||||||___ WRX1 / P08_1
\r
1035 ; ||||||____ WRX2 / P08_2
\r
1036 ; |||||_____ WRX3 / P08_3
\r
1037 ; ||||______ RDX / P08_4
\r
1038 ; |||_______ BGRNTX / P08_5
\r
1039 ; ||________ BRQ / P08_6
\r
1040 ; |_________ RDY / P08_7
\r
1042 #set PFUNC9 B'11111111 ;<<< Control signals or GIO, PFR09
\r
1044 ; ||||||||__ CSX0 / P09_0
\r
1045 ; |||||||___ CSX1 / P09_1
\r
1046 ; ||||||____ CSX2 / P09_2
\r
1047 ; |||||_____ CSX3 / P09_3
\r
1048 ; ||||______ CSX4 / P09_4
\r
1049 ; |||_______ CSX5 / P09_5
\r
1050 ; ||________ CSX6 / P09_6
\r
1051 ; |_________ CSX7 / P09_7
\r
1053 #set PFUNC10 B'01011111 ;<<< Control signals or GIO, PFR10
\r
1055 ; ||||||||__ SYSCLK or !SYSCLK / P10_0
\r
1056 ; |||||||___ ASX / P10_1
\r
1057 ; ||||||____ BAAX / P10_2
\r
1058 ; |||||_____ WEX / P10_3
\r
1059 ; ||||______ MCLKO or !MCLKO / P10_4
\r
1060 ; |||_______ MCLKI or !MCLKI/ P10_5
\r
1061 ; ||________ MCLKE / P10_6
\r
1064 #set EPFUNC10 B'00000000 ;<<< Control signals or GIO, EPFR10
\r
1066 ; ||||||||__ 0:SYSCLK / 1:!SYSCLK
\r
1070 ; ||||______ 0:MCLKO / 1:!MCLKO
\r
1071 ; |||_______ 0:MCLKI / 1:!MCLKI
\r
1072 ; ||________ 0:MCLKI / 1:!MCLKI
\r
1076 ; Select if the ports are set to
\r
1077 ; 1 : External bus mode, I/O for control lines or
\r
1078 ; 0 : General I/O port (GIO)
\r
1080 ; Note: Not all control-lines are supported by the different devices. Please check the
\r
1083 ;=========================================================================================
\r
1084 ; 5 Definition of Configurations
\r
1085 ;=========================================================================================
\r
1087 #set NOCLOCK 0 ; do not touch CKSCR register
\r
1088 #set MAINCLOCK 1 ; select main clock
\r
1089 ; ; MB91461R : 1/4 of oscillation input
\r
1090 ; ; Others: 1/2 of oscillation input
\r
1091 #set MAINPLLCLOCK 2 ; select main clock with PLL
\r
1092 #set SUBCLOCK 3 ; select subclock (if available)
\r
1094 #set PSCLOCK_CLKB 0x00 ; select core clock (initial)
\r
1095 #set PSCLOCK_PLL 0x10 ; select PLL output (x)
\r
1096 #set PSCLOCK_MAIN 0x30 ; select Main Oscillation
\r
1098 ;=========================================================================================
\r
1099 ; 5.1 CLOCKSPEED == CLOCK_USER <<<
\r
1100 ;=========================================================================================
\r
1101 ; Must be configured only in the case of CLOCKSPEED is set to CLOCK_USER. Please see the
\r
1102 ; corresponding application note.
\r
1104 #if (CLOCKSPEED == CLOCK_USER )
\r
1105 #set CLOCKSOURCE MAINPLLCLOCK ; <<< Clocksource
\r
1106 #set ENABLE_SUBCLOCK OFF ; <<< Subclock: ON/OFF
\r
1107 #set PLLSPEED 0x010F ; <<< 0x48Ch, 0x48Dh: PLLDIVM/N ; 64 MHz
\r
1108 #set DIV_G 0x0F ; <<< 0x48Eh: PLLDIVG;
\r
1109 #set MUL_G 0x0F ; <<< 0x48Fh: PLLMULG;
\r
1111 #set CPUCLOCK 0x00 ; <<< 0x486h: DIV0R_B; => /1 ; 64 MHz
\r
1112 #set PERCLOCK 0x03 ; <<< 0x486h: DIV0R_P; => /4 ; 16 MHz
\r
1113 #set EXTBUSCLOCK 0x01 ; <<< 0x487h: DIV1R_T; => /2 ; 32 MHz
\r
1115 #set PSCLOCKSOURCE PSCLOCK_PLL ; <<< 0x4C0h: CANPRE; => PLLx;128 MHz
\r
1116 #set PSDVC 0x07 ; <<< 0x4C0h: CANPRE_DVC;=> /8 ; 16 MHz
\r
1117 #set CANCLOCK 0x00 ; <<< 0x4C1h: CANCKD;
\r
1118 ; Voltage Regulator
\r
1119 #set REGULATORSEL 0x06 ; <<< 0x4CEh: REGSEL;
\r
1120 #set REGULATORCTRL 0x00 ; <<< 0x4CFh: REGCTR;
\r
1121 ; Memory Controller
\r
1122 #set FLASHCONTROL 0x032 ; <<< 0x7002h: FCHCR;
\r
1123 #set FLASHREADT 0xC413 ; <<< 0x7004h: FMWT;
\r
1124 #set FLASHMWT2 0x10 ; <<< 0x7006h: FMWT2;
\r
1127 ;=========================================================================================
\r
1128 ; 5.2 CLOCKSPEED == NO_CLOCK
\r
1129 ;=========================================================================================
\r
1131 #if (CLOCKSPEED == NO_CLOCK )
\r
1132 #set CLOCKSOURCE NOCLOCK
\r
1135 ;=========================================================================================
\r
1136 ; 5.2 CLOCKSPEED == SUB_32KHZ_CPU__32KHZ_PER_32KHZ_EXT_32KHZ_CAN__2MHZ
\r
1137 ;=========================================================================================
\r
1139 #if (CLOCKSPEED == SUB_32KHZ_CPU__32KHZ_PER_32KHZ_EXT_32KHZ_CAN__2MHZ )
\r
1141 ; Start restriction; Maximum frequency
\r
1142 #if (DEVICE == MB91463N) || (DEVICE == MB91461R)
\r
1143 #error: Frequency is not supported by this device.
\r
1147 #set CLOCKSOURCE SUBCLOCK ; Clocksource
\r
1148 #set ENABLE_SUBCLOCK ON ; Subclock: ON/OFF
\r
1149 #set PLLSPEED 0x010F ; 0x48Ch, 0x48Dh: PLLDIVM/N ; n. a.
\r
1150 #set DIV_G 0x0F ; 0x48Eh: PLLDIVG;
\r
1151 #set MUL_G 0x0F ; 0x48Fh: PLLMULG;
\r
1153 #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 32 KHz
\r
1154 #set PERCLOCK 0x00 ; 0x486h: DIV0R_P; => /1 ; 32 KHz
\r
1155 #set EXTBUSCLOCK 0x00 ; 0x487h: DIV1R_T; => /1 ; 32 KHz
\r
1157 #set PSCLOCKSOURCE PSCLOCK_MAIN ; 0x4C0h: CANPRE; => MAIN ; 4 MHz
\r
1158 #set PSDVC 0x01 ; 0x4C0h: CANPRE_DVC; => /2 ; 2 MHz
\r
1159 #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
\r
1160 ; Voltage Regulator
\r
1161 #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;
\r
1162 #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR;
\r
1163 ; Memory Controller
\r
1164 #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;
\r
1165 #set FLASHREADT 0xC100 ; 0x7004h: FMWT;
\r
1166 #set FLASHMWT2 0x00 ; 0x7006h: FMWT2;
\r
1169 ;=========================================================================================
\r
1170 ; 5.3 CLOCKSPEED == MAIN__4MHZ_CPU___2MHZ_PER__1MHZ_EXT__1MHZ_CAN__2MHZ
\r
1171 ;=========================================================================================
\r
1173 #if (CLOCKSPEED == MAIN_4MHZ_CPU___2MHZ_PER__1MHZ_EXT__1MHZ_CAN__2MHZ )
\r
1175 ; Start restriction; Maximum frequency
\r
1176 #if (DEVICE == MB91461R)
\r
1177 #error: Frequency is not supported by this device.
\r
1181 #set CLOCKSOURCE MAINCLOCK ; Clocksource
\r
1182 #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF
\r
1183 #set PLLSPEED 0x010F ; 0x48Ch, 0x48Dh: PLLDIVM/N ; n. a.
\r
1184 #set DIV_G 0x0F ; 0x48Eh: PLLDIVG;
\r
1185 #set MUL_G 0x0F ; 0x48Fh: PLLMULG;
\r
1187 #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 2 MHz
\r
1188 #set PERCLOCK 0x01 ; 0x486h: DIV0R_P; => /2 ; 1 MHz
\r
1189 #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 1 MHz
\r
1191 #set PSCLOCKSOURCE PSCLOCK_MAIN ; 0x4C0h: CANPRE; => PLLx ; 4 MHz
\r
1192 #set PSDVC 0x01 ; 0x4C0h: CANPRE_DVC; => /2 ; 2 MHz
\r
1193 #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
\r
1194 ; Voltage Regulator
\r
1195 #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;
\r
1196 #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR;
\r
1197 ; Memory Controller
\r
1198 #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;
\r
1199 #set FLASHREADT 0xC100 ; 0x7004h: FMWT;
\r
1200 #set FLASHMWT2 0x00 ; 0x7006h: FMWT2;
\r
1203 ;=========================================================================================
\r
1204 ; 5.4 CLOCKSPEED == PLL_4MHZ__CPU__48MHZ_PER_16MHZ_EXT_24MHZ_CAN_16MHZ
\r
1205 ;=========================================================================================
\r
1207 #if (CLOCKSPEED == PLL_4MHZ__CPU__48MHZ_PER_16MHZ_EXT_24MHZ_CAN_16MHZ )
\r
1209 ; Start restriction; Maximum frequency
\r
1210 #if (DEVICE == MB91461R)
\r
1211 #error: Frequency is not supported by this device.
\r
1215 #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource
\r
1216 #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF
\r
1217 #set PLLSPEED 0x010B ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 48 MHz
\r
1218 #set DIV_G 0x0F ; 0x48Eh: PLLDIVG;
\r
1219 #set MUL_G 0x0B ; 0x48Fh: PLLMULG;
\r
1221 #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 48 MHz
\r
1222 #set PERCLOCK 0x02 ; 0x486h: DIV0R_P; => /3 ; 16 MHz
\r
1223 #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 24 MHz
\r
1225 #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 96 MHz
\r
1226 #set PSDVC 0x05 ; 0x4C0h: CANPRE_DVC; => /6 ; 16 MHz
\r
1227 #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
\r
1228 ; Voltage Regulator
\r
1229 #if (DEVICE == MB91469G)
\r
1230 #set REGULATORSEL 0x36 ; 0x4CEh: REGSEL;
\r
1232 #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;
\r
1234 #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR;
\r
1235 ; Memory Controller
\r
1236 #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;
\r
1237 #set FLASHREADT 0xC201 ; 0x7004h: FMWT;
\r
1238 #set FLASHMWT2 0x00 ; 0x7006h: FMWT2;
\r
1241 ;=========================================================================================
\r
1242 ; 5.5 CLOCKSPEED == PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ
\r
1243 ;=========================================================================================
\r
1245 #if (CLOCKSPEED == PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ )
\r
1247 ; Start restriction; Maximum frequency
\r
1248 #if (DEVICE == MB91461R)
\r
1249 #error: Frequency is not supported by this device.
\r
1253 #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource
\r
1254 #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF
\r
1255 #set PLLSPEED 0x010F ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 64 MHz
\r
1256 #set DIV_G 0x0F ; 0x48Eh: PLLDIVG;
\r
1257 #set MUL_G 0x0F ; 0x48Fh: PLLMULG;
\r
1259 #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 64 MHz
\r
1260 #set PERCLOCK 0x03 ; 0x486h: DIV0R_P; => /4 ; 16 MHz
\r
1261 #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 32 MHz
\r
1263 #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 128 MHz
\r
1264 #set PSDVC 0x07 ; 0x4C0h: CANPRE_DVC; => /8 ; 16 MHz
\r
1265 #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
\r
1266 ; Voltage Regulator
\r
1267 #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;
\r
1268 #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR;
\r
1269 ; Memory Controller
\r
1270 #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;
\r
1271 #set FLASHREADT 0xC413 ; 0x7004h: FMWT;
\r
1272 #set FLASHMWT2 0x10 ; 0x7006h: FMWT2;
\r
1275 ;=========================================================================================
\r
1276 ; 5.6 CLOCKSPEED == PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_27MHZ_CAN_20MHZ
\r
1277 ;=========================================================================================
\r
1279 #if (CLOCKSPEED == PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_27MHZ_CAN_20MHZ )
\r
1281 ; Start restriction; Maximum frequency
\r
1282 #if (DEVICE == MB91461R)
\r
1283 #error: Frequency is not supported by this device.
\r
1287 #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource
\r
1288 #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF
\r
1289 #set PLLSPEED 0x0113 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 80 MHz
\r
1290 #set DIV_G 0x0F ; 0x48Eh: PLLDIVG;
\r
1291 #set MUL_G 0x13 ; 0x48Fh: PLLMULG;
\r
1293 #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 80 MHz
\r
1294 #set PERCLOCK 0x03 ; 0x486h: DIV0R_P; => /4 ; 20 MHz
\r
1295 #set EXTBUSCLOCK 0x02 ; 0x487h: DIV1R_T; => /3 ; 27 MHz
\r
1297 #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 160 MHz
\r
1298 #set PSDVC 0x07 ; 0x4C0h: CANPRE_DVC; => /8 ; 8 MHz
\r
1299 #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
\r
1300 ; Voltage Regulator
\r
1301 #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;
\r
1302 #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR;
\r
1303 ; Memory Controller
\r
1304 #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;
\r
1305 #set FLASHREADT 0xC413 ; 0x7004h: FMWT;
\r
1306 #set FLASHMWT2 0x10 ; 0x7006h: FMWT2;
\r
1309 ;=========================================================================================
\r
1310 ; 5.7 CLOCKSPEED == PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_40MHZ_CAN_20MHZ
\r
1311 ;=========================================================================================
\r
1313 #if (CLOCKSPEED == PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_40MHZ_CAN_20MHZ )
\r
1315 ; Start restriction; Maximum frequency
\r
1316 #if (DEVICE == MB91461R)
\r
1317 #error: Frequency is not supported by this device.
\r
1321 #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource
\r
1322 #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF
\r
1323 #set PLLSPEED 0x0113 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 80 MHz
\r
1324 #set DIV_G 0x0F ; 0x48Eh: PLLDIVG;
\r
1325 #set MUL_G 0x13 ; 0x48Fh: PLLMULG;
\r
1327 #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 80 MHz
\r
1328 #set PERCLOCK 0x03 ; 0x486h: DIV0R_P; => /4 ; 20 MHz
\r
1329 #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 40 MHz
\r
1331 #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 160 MHz
\r
1332 #set PSDVC 0x07 ; 0x4C0h: CANPRE_DVC; => /8 ; 8 MHz
\r
1333 #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
\r
1334 ; Voltage Regulator
\r
1335 #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;
\r
1336 #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR;
\r
1337 ; Memory Controller
\r
1338 #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;
\r
1339 #set FLASHREADT 0xC413 ; 0x7004h: FMWT;
\r
1340 #set FLASHMWT2 0x10 ; 0x7006h: FMWT2;
\r
1343 ;=========================================================================================
\r
1344 ; 5.8 CLOCKSPEED == PLL_4MHZ__CPU__96MHZ_PER_16MHZ_EXT_48MHZ_CAN_16MHZ
\r
1345 ;=========================================================================================
\r
1347 #if (CLOCKSPEED == PLL_4MHZ__CPU__96MHZ_PER_16MHZ_EXT_48MHZ_CAN_16MHZ )
\r
1349 ; Start restriction; Maximum frequency
\r
1350 #if (DEVICE == MB91464A) || (DEVICE == MB91465K) || (DEVICE == MB91463N) ||\
\r
1351 (DEVICE == MB91461R) || (DEVICE == MB91467R)
\r
1352 #error: Frequency is not supported by this device.
\r
1356 #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource
\r
1357 #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF
\r
1358 #set PLLSPEED 0x0117 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 96 MHz
\r
1359 #set DIV_G 0x0F ; 0x48Eh: PLLDIVG;
\r
1360 #set MUL_G 0x17 ; 0x48Fh: PLLMULG;
\r
1362 #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 64 MHz
\r
1363 #set PERCLOCK 0x05 ; 0x486h: DIV0R_P; => /6 ; 16 MHz
\r
1364 #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 32 MHz
\r
1366 #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 192 MHz
\r
1367 #set PSDVC 0x0B ; 0x4C0h: CANPRE_DVC; => /12 ; 16 MHz
\r
1368 #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
\r
1369 ; Voltage Regulator
\r
1370 #if (DEVICE == MB91469G)
\r
1371 #set REGULATORSEL 0x36 ; 0x4CEh: REGSEL;
\r
1373 #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;
\r
1375 #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR;
\r
1376 ; Memory Controller
\r
1377 #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;
\r
1378 #set FLASHREADT 0xC413 ; 0x7004h: FMWT;
\r
1379 #set FLASHMWT2 0x10 ; 0x7006h: FMWT2;
\r
1382 ;=========================================================================================
\r
1383 ; 5.9 CLOCKSPEED == PLL_4MHZ__CPU_100MHZ_PER_20MHZ_EXT_50MHZ_CAN_20MHZ
\r
1384 ;=========================================================================================
\r
1386 #if (CLOCKSPEED == PLL_4MHZ__CPU_100MHZ_PER_20MHZ_EXT_50MHZ_CAN_20MHZ )
\r
1388 ; Start restriction; Maximum frequency
\r
1389 #if (DEVICE == MB91464A) || (DEVICE == MB91465K) || (DEVICE == MB91463N) ||\
\r
1390 (DEVICE == MB91461R) || (DEVICE == MB91467R) || (DEVICE == MB91467D)
\r
1391 #error: Frequency is not supported by this device.
\r
1395 #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource
\r
1396 #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF
\r
1397 #set PLLSPEED 0x0118 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 100 MHz
\r
1398 #set DIV_G 0x0F ; 0x48Eh: PLLDIVG;
\r
1399 #set MUL_G 0x17 ; 0x48Fh: PLLMULG;
\r
1401 #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 100 MHz
\r
1402 #set PERCLOCK 0x04 ; 0x486h: DIV0R_P; => /5 ; 20 MHz
\r
1403 #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 50 MHz
\r
1405 #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 200 MHz
\r
1406 #set PSDVC 0x09 ; 0x4C0h: CANPRE_DVC; => /10 ; 20 MHz
\r
1407 #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
\r
1408 ; Voltage Regulator
\r
1409 #if (DEVICE == MB91469G)
\r
1410 #set REGULATORSEL 0x36 ; 0x4CEh: REGSEL;
\r
1412 #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;
\r
1414 #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR;
\r
1415 ; Memory Controller
\r
1416 #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;
\r
1417 #set FLASHREADT 0xC413 ; 0x7004h: FMWT;
\r
1418 #set FLASHMWT2 0x10 ; 0x7006h: FMWT2;
\r
1421 ;=========================================================================================
\r
1422 ; 5.10 CLOCKSPEED == PLL_10MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ
\r
1423 ;=========================================================================================
\r
1425 #if (CLOCKSPEED == PLL_10MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ )
\r
1427 ; Start restriction; Maximum frequency
\r
1428 #if (DEVICE == MB91464A) || (DEVICE == MB91467B) || (DEVICE == MB91467C) ||\
\r
1429 (DEVICE == MB91467D) || (DEVICE == MB91469G) || (DEVICE == MB91465K) ||\
\r
1430 (DEVICE == MB91463N) || (DEVICE == MB91467R) || (DEVICE == MB91465X)
\r
1431 #error: Frequency is not supported by this device.
\r
1435 #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource
\r
1436 #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF
\r
1437 #set PLLSPEED 0x0105 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 60 MHz
\r
1438 #set DIV_G 0x0B ; 0x48Eh: PLLDIVG;
\r
1439 #set MUL_G 0x1F ; 0x48Fh: PLLMULG;
\r
1441 #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 60 MHz
\r
1442 #set PERCLOCK 0x02 ; 0x486h: DIV0R_P; => /3 ; 20 MHz
\r
1443 #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 30 MHz
\r
1445 #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 120 MHz
\r
1446 #set PSDVC 0x05 ; 0x4C0h: CANPRE_DVC; => /6 ; 20 MHz
\r
1447 #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
\r
1448 ; Voltage Regulator
\r
1450 ; Memory Controller
\r
1454 ;=========================================================================================
\r
1455 ; 5.11 CLOCKSPEED == PLL_20MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ
\r
1456 ;=========================================================================================
\r
1458 #if (CLOCKSPEED == PLL_20MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ )
\r
1460 ; Start restriction; Maximum frequency
\r
1461 #if (DEVICE == MB91464A) || (DEVICE == MB91467B) || (DEVICE == MB91467C) ||\
\r
1462 (DEVICE == MB91467D) || (DEVICE == MB91469G) || (DEVICE == MB91465K) ||\
\r
1463 (DEVICE == MB91463N) || (DEVICE == MB91467R) || (DEVICE == MB91465X)
\r
1464 #error: Frequency is not supported by this device.
\r
1468 #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource
\r
1469 #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF
\r
1470 #set PLLSPEED 0x0102 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 60 MHz
\r
1471 #set DIV_G 0x0F ; 0x48Eh: PLLDIVG;
\r
1472 #set MUL_G 0x1F ; 0x48Fh: PLLMULG;
\r
1474 #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 60 MHz
\r
1475 #set PERCLOCK 0x02 ; 0x486h: DIV0R_P; => /3 ; 20 MHz
\r
1476 #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 30 MHz
\r
1478 #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 120 MHz
\r
1479 #set PSDVC 0x05 ; 0x4C0h: CANPRE_DVC; => /6 ; 20 MHz
\r
1480 #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
\r
1481 ; Voltage Regulator
\r
1483 ; Memory Controller
\r
1487 ;=========================================================================================
\r
1488 ; 6 Section and Data Declaration
\r
1489 ;=========================================================================================
\r
1496 #if CLIBINIT == ON
\r
1499 .import __stream_init
\r
1502 #if CPLUSPLUS == ON
\r
1504 .import ___call_dtors
\r
1507 ;=========================================================================================
\r
1508 ; 6.1 Define Stack Size
\r
1509 ;=========================================================================================
\r
1510 .SECTION SSTACK, STACK, ALIGN=4
\r
1511 #if STACK_RESERVE == ON
\r
1512 .EXPORT __systemstack, __systemstack_top
\r
1514 .RES.B STACK_SYS_SIZE
\r
1515 __systemstack_top:
\r
1518 .SECTION USTACK, STACK, ALIGN=4
\r
1519 #if STACK_RESERVE == ON
\r
1520 .EXPORT __userstack, __userstack_top
\r
1522 .RES.B STACK_USR_SIZE
\r
1526 ;=========================================================================================
\r
1527 ; 6.2 Define Sections
\r
1528 ;=========================================================================================
\r
1529 .section DATA, data, align=4
\r
1530 .section INIT, data, align=4
\r
1531 .section IRAM, code, align=4
\r
1532 .section CONST, const, align=4
\r
1533 .section INTVECT, const, align=4
\r
1540 #if (DEVICE != MB91461R)
\r
1541 #if (DEVICE == MB91469G)
\r
1542 .section SECURITY_VECTORS, code, locate = 0x248000
\r
1544 .section SECURITY_VECTORS, code, locate = 0x148000
\r
1547 #if (BOOT_FLASH_SEC == OFF)
\r
1548 .data.w 0xFFFFFFFF
\r
1549 .data.w 0xFFFFFFFF
\r
1550 .data.w 0xFFFFFFFF
\r
1551 .data.w 0xFFFFFFFF
\r
1557 #if CPLUSPLUS == ON
\r
1558 .section EXT_CTOR_DTOR, const, align=4 ; C++ constructors
\r
1561 ;-----------------------------------------------------------------------------------------
\r
1562 ; MACRO Clear RC Watchdog
\r
1563 ;-----------------------------------------------------------------------------------------
\r
1564 #macro ClearRCwatchdog
\r
1565 LDI #0x4C7,R7 ; clear RC watchdog
\r
1568 ;-----------------------------------------------------------------------------------------
\r
1570 ;-----------------------------------------------------------------------------------------
\r
1571 #macro wait_loop loop_number
\r
1572 #local _wait64_loop
\r
1573 LDI #loop_number, R0
\r
1578 .section CODE, code, align=4
\r
1579 .section CODE_START, code, align=4
\r
1582 ;=========================================================================================
\r
1584 ;=========================================================================================
\r
1585 __start: ; start point
\r
1589 ANDCCR #0xEF ; disable interrupts
\r
1590 STILM #LOW_PRIOR ; set interrupt level to low prior
\r
1591 ClearRCwatchdog ; clear harware watchdog
\r
1593 ;=========================================================================================
\r
1594 ; 7.1 Initialise Stack Pointer and Table Base Register
\r
1595 ;=========================================================================================
\r
1596 #if STACKUSE == SYSSTACK
\r
1598 LDI #__userstack_top, SP ; initialize SP
\r
1600 LDI #__systemstack_top, SP ; initialize SP
\r
1603 #if STACKUSE == USRSTACK
\r
1605 LDI #__systemstack_top, SP ; initialize SP
\r
1607 LDI #__userstack_top, SP ; initialize SP
\r
1610 LDI #INTVECT, R0 ; set Table Base
\r
1614 #if (CLOCKSOURCE != NOCLOCK)
\r
1615 ;=========================================================================================
\r
1616 ; 7.2 Check for CSV reset and set CSV
\r
1617 ;=========================================================================================
\r
1618 ; Start restriction; No clock supervisor (CSV)
\r
1619 #if (DEVICE != MB91461R) && (DEVICE != MB91467R) && (DEVICE != MB91463N)
\r
1621 LDI:20 #0x04AD, R0 ; CSVCR
\r
1622 BORL #0x8, @R0 ; Enable Main Osc CSV
\r
1623 BTSTH #0x4, @R0 ; Check for Main Osc missing
\r
1624 BEQ NoMAINCSVreset ; Main osc available -> branch
\r
1626 BANDL #0x7, @R0 ; Disable Main Osc CSV
\r
1628 LDI #noClockStartup, R0 ; Main Clock missing -> no
\r
1629 JMP @R0 ; clock startup
\r
1634 BORL #0x4, @R0 ; Enable Sub Osc CSV
\r
1635 BTSTH #0x2, @R0 ; Check for Sub Osc missing
\r
1636 BEQ NoSUBCSVreset ; Sub osc available -> branch
\r
1638 BANDL #0xB, @R0 ; Disable Sub Osc SCSV
\r
1639 #if (CLOCKSOURCE == SUBCLOCK)
\r
1640 LDI #noClockStartup, R0 ; Sub Clock missing -> no
\r
1641 JMP @R0 ; clock startup
\r
1645 ;=========================================================================================
\r
1646 ; 7.3 Check Clock Condition
\r
1647 ;=========================================================================================
\r
1648 LDI #0x484, R0 ; Check for Default Values
\r
1651 BEQ clock_startup
\r
1653 ;=========================================================================================
\r
1654 ; 7.4 Restore Default Settings after Reset
\r
1655 ;=========================================================================================
\r
1656 ;=========================================================================================
\r
1657 ; 7.4.1 Disable Clock Modulator
\r
1658 ;=========================================================================================
\r
1659 LDI #0x04BB, R0 ; Clock Modulator Control Reg
\r
1660 BANDL #0xD, @R0 ; Disable Frequency modulation
\r
1662 BTSTL #8, @R0 ; Wait until Frequency modulation
\r
1663 BNE FMODwait ; is disabled
\r
1665 BANDL #0xE, @R0 ; Power down clock modulator
\r
1667 ;=========================================================================================
\r
1668 ; 7.4.2 Check if running on Sub Clock, change to Main Clock
\r
1669 ;=========================================================================================
\r
1670 LDI:20 #0x0484,R12 ; Check if running on sub clock
\r
1677 LDI:20 #0x04CC,R12 ; Check if Main Clock is stopped
\r
1679 BEQ mainNotStopped
\r
1681 BANDL #0xE, @R12 ; Start Main Oscillation
\r
1683 LDI #0x4C8, R0 ; Main Stabilisation Wait Time
\r
1684 LDI #0x04, R1 ; 32.7 ms
\r
1688 mainStabTime: ; Wait for stabilisation time
\r
1689 ClearRCwatchdog ; clear harware watchdog
\r
1696 LDI:20 #0x0484, R12 ; disable sub clock as source
\r
1697 BANDL #0xD, @R12 ; Clock source = 0x01 (Main/2)
\r
1700 ;=========================================================================================
\r
1701 ; 7.4.3 Disable Sub Clock
\r
1702 ;=========================================================================================
\r
1703 #if ENABLE_SUBCLOCK != ON
\r
1704 LDI #0x0484, R0 ; Clock source control reg CLKR
\r
1705 BANDL #0x7, @R0 ; Disable PLL
\r
1708 ;=========================================================================================
\r
1709 ; 7.4.4 Check if running on PLL, Gear Down PLL
\r
1710 ;=========================================================================================
\r
1711 LDI:20 #0x0484,R12 ; Check if running on PLL
\r
1718 LDI:20 #0x0490, R11 ; clear flags
\r
1722 STB R1, @R11 ; Set Flag for Simulator; no Effekt on
\r
1725 BANDL #0xC, @R12 ; disable PLL as clock source
\r
1726 ; Clock Source = 0x00 (Main/2)
\r
1728 LDI:20 #0x048E,R12 ; check if DivG != 0
\r
1735 ClearRCwatchdog ; clear harware watchdog
\r
1736 BTSTL #4, @R11 ; Gear Down
\r
1737 BEQ gearDownLoop ;
\r
1739 LDI #0x00,R1 ; Clear Flags
\r
1743 ;=========================================================================================
\r
1744 ; 7.4.5 Disable PLL
\r
1745 ;=========================================================================================
\r
1746 LDI #0x0484, R0 ; Clock source control reg CLKR
\r
1747 BANDL #0xB, @R0 ; Disable PLL
\r
1749 ;=========================================================================================
\r
1750 ; 7.4.6 Set to Main Clock
\r
1751 ;=========================================================================================
\r
1752 LDI:20 #0x0484,R12 ; Check if running on PLL
\r
1753 BANDL #0xC, @R12 ; disable PLL as clock source
\r
1754 ; Clock Source = 0x00 (Main/2)
\r
1757 ;=========================================================================================
\r
1758 ; 7.5 Set Memory Controller
\r
1759 ;=========================================================================================
\r
1760 ; Start restriction; No embedded flash
\r
1761 #if DEVICE != MB91461R
\r
1763 LDI #0x7002, R1 ; FLASH Controller Reg.
\r
1764 LDI #FLASHCONTROL, R2 ; Flash Controller Settings
\r
1765 STH R2, @R1 ; set register
\r
1766 LDI #0x7004, R1 ; FLASH Memory Wait Timing Reg.
\r
1767 LDI #FLASHREADT, R2 ; wait settings
\r
1768 STH R2, @R1 ; set register
\r
1769 LDI #0x7006, R1 ; FLASH Memory Wait Timing Reg.
\r
1770 LDI #FLASHMWT2, R2 ; wait settings
\r
1771 STB R2, @R1 ; set register
\r
1775 ;=========================================================================================
\r
1776 ; 7.6 Clock startup
\r
1777 ;=========================================================================================
\r
1778 ;=========================================================================================
\r
1779 ; 7.6.1 Set Voltage Regulator Settings
\r
1780 ;=========================================================================================
\r
1781 ; Start restriction; No regulator settings
\r
1782 #if DEVICE != MB91461R
\r
1784 LDI #0x04CF, R0 ; REGCTR
\r
1785 LDI #REGULATORCTRL, R1
\r
1788 LDI #0x04CE, R0 ; REGSEL
\r
1789 LDI #REGULATORSEL, R1
\r
1793 ;=========================================================================================
\r
1794 ; 7.6.2 Power on Clock Modulator - Clock Modulator Part I
\r
1795 ;=========================================================================================
\r
1797 LDI #0x04BB, R0 ; Clock Modulator Control Reg
\r
1798 LDI #0x11, R1 ; Load value to Power on CM
\r
1799 ORB R1, @R0 ; Power on clock modulaor
\r
1802 ;=========================================================================================
\r
1803 ; 7.6.3 Set CLKR Register w/o Clock Mode
\r
1804 ;=========================================================================================
\r
1805 ; Set Clock source (Base Clock) for the three clock tree selections
\r
1806 ; This select Base clock is used to select afterwards the 3
\r
1807 ; Clocks for the diffenrent internal trees.
\r
1808 ; When PLL is used, first pll multiplication ratio is set and PLL is
\r
1809 ; enabled. After waiting the PLL stabilisation time via timebase
\r
1810 ; timer, PLL clock is selected as clock source.
\r
1811 LDI #0x048C, R0 ; PLL Cntl Reg. PLLDIVM/N
\r
1812 LDI:20 #PLLSPEED, R1
\r
1815 LDI #0x048E, R0 ; PLL Cntl Reg. PLLDIVG
\r
1819 LDI #0x048F, R0 ; PLL Cntl Reg. PLLMULG
\r
1823 ;=========================================================================================
\r
1824 ; 7.6.4 Start PLL
\r
1825 ;=========================================================================================
\r
1826 #if ( ( CLOCKSOURCE == MAINPLLCLOCK ) || ( PSCLOCKSOURCE == PSCLOCK_PLL ) )
\r
1827 LDI #0x0484, R0 ; Clock source control reg CLKR
\r
1828 LDI #0x04, R1 ; Use PLL x1, enable PLL
\r
1829 ORB R1, @R0 ; store data to CLKR register
\r
1833 #if ENABLE_SUBCLOCK == ON
\r
1834 LDI #0x0484, R0 ; Clock source control reg CLKR
\r
1835 LDI #0x08, R1 ; enable subclock operation
\r
1836 ORB R1, @R0 ; store data to CLKR register
\r
1837 LDI #0x4CA, R0 ; Sub Clock oszilation
\r
1838 LDI #0x00, R1 ; stabilitsation time = 32 ms
\r
1843 ;=========================================================================================
\r
1844 ; 7.6.5 Wait for PLL oscillation stabilisation
\r
1845 ;=========================================================================================
\r
1846 #if ((CLOCKSOURCE==MAINPLLCLOCK)||(PSCLOCKSOURCE==PSCLOCK_PLL))
\r
1847 LDI #0x0482, R12 ; TimeBaseTimer TBCR
\r
1848 LDI #0x00, R1 ; set 1024 us @ 2 MHz
\r
1851 BANDH #7, @R12 ; clear interrupt flag
\r
1853 LDI #0x0483, R0 ; clearTimeBaseTimer CTBR
\r
1859 BANDH #7, @R12 ; clear interrupt flag
\r
1860 BORH #8, @R12 ; set interrupt flag for simulator
\r
1863 ClearRCwatchdog ; clear harware watchdog
\r
1868 ;=========================================================================================
\r
1869 ; 7.6.6 Set clocks
\r
1870 ;=========================================================================================
\r
1871 ;=========================================================================================
\r
1872 ; 7.6.6.1 Set CPU and peripheral clock
\r
1873 ;=========================================================================================
\r
1874 ; CPU and peripheral clock are set in one register
\r
1875 LDI #0x0486, R2 ; Set DIVR0 (CPU-clock (CLKB)
\r
1876 LDI #((CPUCLOCK << 4) + PERCLOCK), R3 ; Load CPU clock setting
\r
1878 ;=========================================================================================
\r
1879 ; 7.6.6.2 Set External Bus interface clock
\r
1880 ;=========================================================================================
\r
1881 ; set External Bus clock
\r
1882 ; Be aware to do smooth clock setting, to avoid wrong clock setting
\r
1883 ; Take care, always write 0 to the lower 4 bits of DIVR1 register
\r
1884 LDI #0x0487, R2 ; Set DIVR1
\r
1885 LDI #(EXTBUSCLOCK << 4), R3 ; Load Peripheral clock setting
\r
1888 ;=========================================================================================
\r
1889 ; 7.6.6.3 Set CAN clock prescaler
\r
1890 ;=========================================================================================
\r
1891 ; Set CAN Prescaler, only clock relevant parameter
\r
1892 LDI #0x04C0, R0 ; Set CAN ClockParameter Register
\r
1893 LDI #(PSCLOCKSOURCE + PSDVC), R1 ; Load Divider
\r
1894 STB R1, @R0 ; Set Divider
\r
1895 ; enable CAN clocks
\r
1896 LDI #0x04c1, R0 ; Set CAN Clock enable Register
\r
1897 LDI #CANCLOCK, R1 ; Load CANCLOCK
\r
1898 STB R1, @R0 ; set CANCLOCK
\r
1900 ;=========================================================================================
\r
1901 ; 7.6.6.4 Switch Main Clock Mode
\r
1902 ;=========================================================================================
\r
1903 #if CLOCKSOURCE == MAINCLOCK
\r
1905 ;=========================================================================================
\r
1906 ; 7.6.6.5 Switch Subclock Mode
\r
1907 ;=========================================================================================
\r
1908 #elif ( (CLOCKSOURCE == SUBCLOCK) )
\r
1909 #if ENABLE_SUBCLOCK == ON
\r
1912 ClearRCwatchdog ; clear harware watchdog
\r
1913 BTSTH #8, @R12 ; wait until sub clock stabilisation
\r
1914 BEQ subStabTime ; time is over
\r
1918 LDI #0x0484, R0 ; Clock source control reg CLKR
\r
1919 LDI #0x01, R1 ; load value to select main clock
\r
1920 ORB R1, @R0 ; enable main clock (1/2 external)
\r
1921 LDI #0x03, R1 ; load value to select subclock
\r
1922 ORB R1, @R0 ; enable subclock as clock source
\r
1924 #error: Wrong setting! The clock source is subclock, but the subclock is disabled.
\r
1927 ;=========================================================================================
\r
1928 ; 7.6.7 Switch to PLL Mode
\r
1929 ;=========================================================================================
\r
1930 #elif ( (CLOCKSOURCE == MAINPLLCLOCK) )
\r
1932 #if (DIV_G != 0x00)
\r
1933 LDI #0x0490, R0 ; PLL Ctrl Register
\r
1935 STB R1, @R0 ; Clear Flag
\r
1937 STB R1, @R0 ; Set Flag for Simulator; no Effekt on
\r
1940 LDI #0x0484, R3 ; Clock source control reg CLKR
\r
1941 BORL #0x2, @R3 ; enable PLL as clock source
\r
1943 #if (DIV_G != 0x00)
\r
1945 ClearRCwatchdog ; clear harware watchdog
\r
1946 LDUB @R0, R2 ; LOAD PLLCTR to R2
\r
1947 AND R1, R2 ; GRUP, counter reach 0
\r
1951 STB R1, @R0 ; Clear Gear-Up Flag
\r
1956 ;=========================================================================================
\r
1957 ; 7.6.8 Enable Frequncy Modulation - Clock Modulator Part II
\r
1958 ;=========================================================================================
\r
1959 #if CLOMO == ON ; Only applicable if Modulator is on
\r
1960 LDI #0x04B8, R0 ; Clock Modulation Parameter Reg
\r
1961 LDI #CMPR, R1 ; Load CMP value
\r
1962 STH R1, @R0 ; Store CMP value in CMPR
\r
1964 LDI #0x04BB, R0 ; Clock Modulator Control Reg
\r
1965 LDI #0x13, R1 ; Load value to FM on CM
\r
1966 ORB R1, @R0 ; FM on
\r
1972 ;=========================================================================================
\r
1973 ; 7.7 Set BusInterface
\r
1974 ;=========================================================================================
\r
1975 ; Start restriction; No ext. bus interface
\r
1976 #if (DEVICE != MB91464A) && (DEVICE != MB91467C) && (DEVICE != MB91465K) && \
\r
1977 (DEVICE != MB91463N) && (DEVICE != MB91465X)
\r
1979 #if (EXTBUS == ON)
\r
1980 ;=========================================================================================
\r
1981 ; 7.7.1 Disable all CS
\r
1982 ;=========================================================================================
\r
1983 ; Start restriction; Flashless device
\r
1984 #if(DEVICE != MB91461R)
\r
1986 LDI #0x0680, R3 ; chip select enable register CSER
\r
1987 LDI #(0x00), R2 ; load disable settings
\r
1989 ANDB R2, @R3 ; set register
\r
1992 ;=========================================================================================
\r
1993 ; 7.7.2 Clear TCR Register
\r
1994 ;=========================================================================================
\r
1995 LDI #0x0683, R1 ; Pin/Timing Control Register TCR
\r
1996 BORH #0x6,@R1 ; load timing settings
\r
1998 ;=========================================================================================
\r
2000 ;=========================================================================================
\r
2002 LDI #0x0640, R1 ; area select reg ASR0, ACR0
\r
2003 LDI #(AREASEL0<<16)+CONFIGCS0, R0 ; load settings
\r
2004 ST R0, @R1 ; set registers
\r
2006 LDI #0x660, R1 ; area wait register awr0
\r
2007 LDI #WAITREG0, R2 ; wait settings
\r
2008 STH R2, @R1 ; set register
\r
2011 ;=========================================================================================
\r
2013 ;=========================================================================================
\r
2015 LDI #0x0644, R1 ; area select reg ASR1, ACR1
\r
2016 LDI #(AREASEL1<<16)+CONFIGCS1, R0 ; load settings
\r
2017 ST R0, @R1 ; set registers
\r
2019 LDI #0x662, R1 ; area wait register awr1
\r
2020 LDI #WAITREG1, R2 ; wait settings
\r
2021 STH R2, @R1 ; set register
\r
2024 ;=========================================================================================
\r
2026 ;=========================================================================================
\r
2028 LDI #0x0648, R1 ; area select reg ASR2, ACR2
\r
2029 LDI #(AREASEL2<<16)+CONFIGCS2, R0 ; load settings
\r
2030 ST R0, @R1 ; set registers
\r
2031 LDI #0x664, R1 ; area wait register awr2
\r
2032 LDI #WAITREG2, R2 ; wait settings
\r
2033 STH R2, @R1 ; set register
\r
2035 ;=========================================================================================
\r
2037 ;=========================================================================================
\r
2039 LDI #0x064C, R1 ; area select reg ASR3, ACR3
\r
2040 LDI #(AREASEL3<<16)+CONFIGCS3, R0 ; load settings
\r
2041 ST R0, @R1 ; set registers
\r
2042 LDI #0x666, R1 ; area wait register awr3
\r
2043 LDI #WAITREG3, R2 ; wait settings
\r
2044 STH R2, @R1 ; set register
\r
2046 ;=========================================================================================
\r
2048 ;=========================================================================================
\r
2050 LDI #0x0650, R1 ; area select reg ASR4, ACR4
\r
2051 LDI #(AREASEL4<<16)+CONFIGCS4, R0 ; load settings
\r
2052 ST R0, @R1 ; set registers
\r
2053 LDI #0x668, R1 ; area wait register awr4
\r
2054 LDI #WAITREG4, R2 ; wait settings
\r
2055 STH R2, @R1 ; set register
\r
2057 ;=========================================================================================
\r
2059 ;=========================================================================================
\r
2061 LDI #0x0654, R1 ; area select reg ASR5, ACR5
\r
2062 LDI #(AREASEL5<<16)+CONFIGCS5, R0 ; load settings
\r
2063 ST R0, @R1 ; set registers
\r
2064 LDI #0x66A, R1 ; area wait register awr5
\r
2065 LDI #WAITREG5, R2 ; wait settings
\r
2066 STH R2, @R1 ; set register
\r
2068 ;=========================================================================================
\r
2070 ;=========================================================================================
\r
2072 LDI #0x0658, R1 ; area select reg ASR6, ACR6
\r
2073 LDI #(AREASEL6<<16)+CONFIGCS6, R0 ; load settings
\r
2074 ST R0, @R1 ; set registers
\r
2075 LDI #0x66C, R1 ; area wait register awr6
\r
2076 LDI #WAITREG6, R2 ; wait settings
\r
2077 STH R2, @R1 ; set register
\r
2079 ;=========================================================================================
\r
2081 ;=========================================================================================
\r
2083 LDI #0x065C, R1 ; area select reg ASR7, ACR7
\r
2084 LDI #(AREASEL7<<16)+CONFIGCS7, R0 ; load settings
\r
2085 ST R0, @R1 ; set registers
\r
2086 LDI #0x66E, R1 ; area wait register awr7
\r
2087 LDI #WAITREG7, R2 ; wait settings
\r
2088 STH R2, @R1 ; set register
\r
2090 ;=========================================================================================
\r
2091 ; 7.7.11 Set special SDRAM config register
\r
2092 ;=========================================================================================
\r
2094 LDI #0x670, R1 ; SDRAM memory config register
\r
2095 LDI #MEMCON, R2 ; wait settings
\r
2096 STB R2, @R1 ; set register
\r
2099 ;=========================================================================================
\r
2100 ; 7.7.12 set Port Function Register
\r
2101 ;=========================================================================================
\r
2102 ;=========================================================================================
\r
2103 ; 7.7.12.1 set PFR00 Register. External bus mode (D[24-31]) or General purpose port
\r
2104 ;=========================================================================================
\r
2105 LDI #0x0D80, R1 ; Port Function Register 0, (PFR00)
\r
2106 LDI #PFUNC0, R0 ; load port settings
\r
2107 STB R0, @R1 ; set register
\r
2108 ;=========================================================================================
\r
2109 ; 7.7.12.2 set PFR01 Register. External bus mode (D[16-23]) or General purpose port
\r
2110 ;=========================================================================================
\r
2111 LDI #0x0D81, R1 ; Port Function Register 1, (PFR01)
\r
2112 LDI #PFUNC1, R0 ; load port settings
\r
2113 STB R0, @R1 ; set register
\r
2114 ;=========================================================================================
\r
2115 ; 7.7.12.3 set PFR02 Register. External bus mode (D[8-15]) or General purpose port
\r
2116 ;=========================================================================================
\r
2117 LDI #0x0D82, R1 ; Port Function Register 2, (PFR02)
\r
2118 LDI #PFUNC2, R0 ; load port settings
\r
2119 STB R0, @R1 ; set register
\r
2120 ;=========================================================================================
\r
2121 ; 7.7.12.4 set PFR03 Register. External bus mode (D[0-7]) or General purpose port
\r
2122 ;=========================================================================================
\r
2123 LDI #0x0D83, R1 ; Port Function Register 3, (PFR03)
\r
2124 LDI #PFUNC3, R0 ; load port settings
\r
2125 STB R0, @R1 ; set register
\r
2126 ;=========================================================================================
\r
2127 ; 7.7.12.5 set PFR04 Register. External bus mode (Adr[24-31]) or General purpose port
\r
2128 ;=========================================================================================
\r
2129 LDI #0x0D84, R1 ; Port Function Register 4, (PFR04)
\r
2130 LDI #PFUNC4, R0 ; load port settings
\r
2131 STB R0, @R1 ; set register
\r
2132 ;=========================================================================================
\r
2133 ; 7.7.12.6 set PFR05 Register. External bus mode (Adr[16-23]) or General purpose port
\r
2134 ;=========================================================================================
\r
2135 LDI #0x0D85, R1 ; Port Function Register 5, (PFR05)
\r
2136 LDI #PFUNC5, R0 ; load port settings
\r
2137 STB R0, @R1 ; set register
\r
2138 ;=========================================================================================
\r
2139 ; 7.7.12.7 set PFR06 Register. External bus mode (Adr[8-15]) or General purpose port
\r
2140 ;=========================================================================================
\r
2141 LDI #0x0D86, R1 ; Port Function Register 6, (PFR06)
\r
2142 LDI #PFUNC6, R0 ; load port settings
\r
2143 STB R0, @R1 ; set register
\r
2144 ;=========================================================================================
\r
2145 ; 7.7.12.8 set PFR07 Register. External bus mode (Adr[0-7]) or General purpose port
\r
2146 ;=========================================================================================
\r
2147 LDI #0x0D87, R1 ; Port Function Register 7, (PFR07)
\r
2148 LDI #PFUNC7, R0 ; load port settings
\r
2149 STB R0, @R1 ; set register
\r
2150 ;=========================================================================================
\r
2151 ; 7.7.12.9 set PFR08 Register. External bus mode (Control Signals) or GIO port
\r
2152 ;=========================================================================================
\r
2153 LDI #0x0D88, R1 ; Port Function Register 8, (PFR08)
\r
2154 LDI #PFUNC8, R0 ; load port settings
\r
2155 STB R0, @R1 ; set register
\r
2156 ;=========================================================================================
\r
2157 ; 7.7.12.10 set PFR09 Register. External bus mode (Control Signals) or GIO port
\r
2158 ;=========================================================================================
\r
2159 LDI #0x0D89, R1 ; Port Function Register 9, (PFR09)
\r
2160 LDI #PFUNC9, R0 ; load port settings
\r
2161 STB R0, @R1 ; set register
\r
2162 ;=========================================================================================
\r
2163 ; 7.7.12.11 set PFR10 Register. External bus mode (Control Signals) or GIO port
\r
2164 ;=========================================================================================
\r
2165 LDI #0x0D8A, R1 ; Port Function Register 10, (PFR10)
\r
2166 LDI #PFUNC10, R0 ; load port settings
\r
2167 STB R0, @R1 ; set register
\r
2168 ;=========================================================================================
\r
2169 ; 7.7.12.12 set EPFR10 Register. External bus mode (Control Signals) or GIO port
\r
2170 ;=========================================================================================
\r
2171 LDI #0x0DCA, R1 ; Extended PFR 10, (EPFR10)
\r
2172 LDI #EPFUNC10, R0 ; load port settings
\r
2173 STB R0, @R1 ; set register
\r
2174 ;=========================================================================================
\r
2175 ; 7.7.13 Set TCR Register
\r
2176 ;=========================================================================================
\r
2177 LDI #0x0683, R1 ; Pin/Timing Control Register TCR
\r
2178 LDI #TIMECONTR, R0 ; load timing settings
\r
2179 STB R0, @R1 ; set register
\r
2180 ;=========================================================================================
\r
2181 ; 7.7.14 Enable CACHE for selected CS
\r
2182 ;=========================================================================================
\r
2183 LDI #0x0681, R3 ; chip select enable register CSER
\r
2186 ;=========================================================================================
\r
2187 ; 7.7.15 set SDRAM Referesh Control Register
\r
2188 ;=========================================================================================
\r
2190 LDI #0x0684, R1 ; Refresh Control Register RCR
\r
2191 LDI #REFRESH, R0 ; load refresh settings
\r
2192 STH R0, @R1 ; set register
\r
2194 OR R2, R0 ; Set PON bit to 1
\r
2195 STH R0, @R1 ; set register
\r
2197 ;=========================================================================================
\r
2198 ; 7.7.16 Enable used CS
\r
2199 ;=========================================================================================
\r
2200 LDI #0x0680, R3 ; chip select enable register CSER
\r
2202 ; Start restriction; Flashless device
\r
2203 #if (DEVICE == MB91461R)
\r
2205 emu_sram_cs_mb91461r:
\r
2206 ANDB R2, @R3 ; set register
\r
2210 ;=========================================================================================
\r
2211 ; 7.7.17 I-cache on/off
\r
2212 ;=========================================================================================
\r
2213 ; Start restriction; No cache
\r
2214 #if (DEVICE == MB91461R) || (DEVICE == MB91469G) || (DEVICE == others)
\r
2217 #if CACHE_SIZE == C1024
\r
2218 LDI #0x03C7, R1 ; Cache size register ISIZE
\r
2221 LDI #0x03E7, R1 ; Cache control reg ICHCR
\r
2222 LDI #0x07, R2 ; Release entry locks, flush and enable
\r
2223 STB R2, @R1 ; cache
\r
2224 #elif CACHE_SIZE == C2048
\r
2225 LDI #0x03C7, R1 ; Cache size register ISIZE
\r
2228 LDI #0x03E7, R1 ; Cache control reg ICHCR
\r
2229 LDI #0x07, R2 ; Release entry locks, flush and enable
\r
2230 STB R2, @R1 ; cache
\r
2231 #elif CACHE_SIZE == C4096
\r
2232 LDI #0x03C7, R1 ; Cache size register ISIZE
\r
2235 LDI #0x03E7, R1 ; Cache control reg ICHCR
\r
2236 LDI #0x07, R2 ; Release entry locks, flush and enable
\r
2237 STB R2, @R1 ; cache
\r
2239 #error: Wrong Cache size selected!
\r
2242 LDI #0x03E7, R1 ; Cache control reg ICHCR
\r
2243 LDI #0x06, R2 ; Release entry locks, flush and disable
\r
2244 STB R2, @R1 ; cache
\r
2247 #elif (EXTBUS == OFF)
\r
2248 ;=========================================================================================
\r
2249 ; 7.7.18 set Port Function Register to general as I/O-Port
\r
2250 ;=========================================================================================
\r
2251 ;=========================================================================================
\r
2252 ; 7.7.18.1 set PFR00 Register. External bus mode as General purpose port
\r
2253 ;=========================================================================================
\r
2254 LDI #0x0D80, R1 ; Port Function Register 0, (PFR00)
\r
2255 LDI #0x00, R0 ; load port settings
\r
2256 STB R0, @R1 ; set register
\r
2257 ;=========================================================================================
\r
2258 ; 7.7.18.2 set PFR01 Register. External bus mode as General purpose port
\r
2259 ;=========================================================================================
\r
2260 LDI #0x0D81, R1 ; Port Function Register 1, (PFR01)
\r
2261 LDI #0x00, R0 ; load port settings
\r
2262 STB R0, @R1 ; set register
\r
2263 ;=========================================================================================
\r
2264 ; 7.7.18.3 set PFR02 Register. External bus mode as General purpose port
\r
2265 ;=========================================================================================
\r
2266 LDI #0x0D82, R1 ; Port Function Register 2, (PFR02)
\r
2267 LDI #0x00, R0 ; load port settings
\r
2268 STB R0, @R1 ; set register
\r
2269 ;=========================================================================================
\r
2270 ; 7.7.18.4 set PFR03 Register. External bus mode as General purpose port
\r
2271 ;=========================================================================================
\r
2272 LDI #0x0D83, R1 ; Port Function Register 3, (PFR03)
\r
2273 LDI #0x00, R0 ; load port settings
\r
2274 STB R0, @R1 ; set register
\r
2275 ;=========================================================================================
\r
2276 ; 7.7.18.5 set PFR04 Register. External bus mode as General purpose port
\r
2277 ;=========================================================================================
\r
2278 LDI #0x0D84, R1 ; Port Function Register 4, (PFR04)
\r
2279 LDI #0x00, R0 ; load port settings
\r
2280 STB R0, @R1 ; set register
\r
2281 ;=========================================================================================
\r
2282 ; 7.7.18.6 set PFR05 Register. External bus mode as General purpose port
\r
2283 ;=========================================================================================
\r
2284 LDI #0x0D85, R1 ; Port Function Register 5, (PFR05)
\r
2285 LDI #0x00, R0 ; load port settings
\r
2286 STB R0, @R1 ; set register
\r
2287 ;=========================================================================================
\r
2288 ; 7.7.18.7 set PFR06 Register. External bus mode as General purpose port
\r
2289 ;=========================================================================================
\r
2290 LDI #0x0D86, R1 ; Port Function Register 6, (PFR06)
\r
2291 LDI #0x00, R0 ; load port settings
\r
2292 STB R0, @R1 ; set register
\r
2293 ;=========================================================================================
\r
2294 ; 7.7.18.8 set PFR07 Register. External bus mode as General purpose port
\r
2295 ;=========================================================================================
\r
2296 LDI #0x0D87, R1 ; Port Function Register 7, (PFR07)
\r
2297 LDI #0x00, R0 ; load port settings
\r
2298 STB R0, @R1 ; set register
\r
2299 ;=========================================================================================
\r
2300 ; 7.7.18.9 set PFR08 Register. External bus mode as General purpose port
\r
2301 ;=========================================================================================
\r
2302 LDI #0x0D88, R1 ; Port Function Register 8, (PFR08)
\r
2303 LDI #0x00, R0 ; load port settings
\r
2304 STB R0, @R1 ; set register
\r
2305 ;=========================================================================================
\r
2306 ; 7.7.18.10 set PFR09 Register. External bus mode as General purpose port
\r
2307 ;=========================================================================================
\r
2308 LDI #0x0D89, R1 ; Port Function Register 9, (PFR09)
\r
2309 LDI #0x00, R0 ; load port settings
\r
2310 STB R0, @R1 ; set register
\r
2311 ;=========================================================================================
\r
2312 ; 7.7.18.11 set PFR10 Register. External bus mode as General purpose port
\r
2313 ;=========================================================================================
\r
2314 LDI #0x0D8A, R1 ; Port Function Register 10, (PFR10)
\r
2315 LDI #0x00, R0 ; load port settings
\r
2316 STB R0, @R1 ; set register
\r
2317 ;=========================================================================================
\r
2318 ; 7.7.18.12 set EPFR10 Register. External bus mode as General purpose port
\r
2319 ;=========================================================================================
\r
2320 LDI #0x0DCA, R1 ; Extended PFR10, (EPFR10)
\r
2321 LDI #0x00, R0 ; load port settings
\r
2322 STB R0, @R1 ; set register
\r
2323 ;=========================================================================================
\r
2325 #elif (EXTBUS == DEFAULT)
\r
2328 emu_sram_cs_mb91461r:
\r
2330 #endif ; #endif (EXTBUS)
\r
2331 #endif ; #endif (excl. devices)
\r
2334 ;=========================================================================================
\r
2335 ; 7.8 Copy code from Flash to I-RAM
\r
2336 ;=========================================================================================
\r
2338 LDI #_RAM_IRAM, R0
\r
2339 LDI #_ROM_IRAM, R1
\r
2340 LDI #sizeof(IRAM), R13
\r
2345 LDUB @(R13, R1), R12
\r
2347 STB R12, @(R13, R0)
\r
2352 ;=========================================================================================
\r
2354 ;=========================================================================================
\r
2355 #if STACK_FILL == ON
\r
2356 LDI #STACK_PATTERN, R0
\r
2358 LDI #sizeof(SSTACK), R2
\r
2360 BEQ:D fill_sstack_end
\r
2364 BEQ:D fill_sstack2
\r
2370 LDI #STACK_PATTERN, R5
\r
2377 BHI:D fill_sstack1
\r
2378 STB R5, @(R13, R1)
\r
2380 BEQ:D fill_sstack_end
\r
2383 BGT:D fill_sstack2
\r
2387 LDI #STACK_PATTERN, R0
\r
2389 LDI #sizeof(USTACK), R2
\r
2391 BEQ:D fill_ustack_end
\r
2395 BEQ:D fill_ustack2
\r
2401 LDI #STACK_PATTERN, R5
\r
2408 BHI:D fill_ustack1
\r
2409 STB R5, @(R13, R1)
\r
2411 BEQ:D fill_ustack_end
\r
2414 BGT:D fill_ustack2
\r
2420 ;=========================================================================================
\r
2421 ; Standard C startup
\r
2422 ;=========================================================================================
\r
2423 ;=========================================================================================
\r
2424 ; 7.10 Clear data
\r
2425 ;=========================================================================================
\r
2426 ; clear DATA section
\r
2427 ; According to ANSI, the DATA section must be cleared during start-up
\r
2429 LDI #sizeof DATA &~0x3, R1
\r
2438 LDI:8 #sizeof DATA & 0x3, R1
\r
2439 LDI #DATA + (sizeof DATA & ~0x3), R13
\r
2446 STB R0, @(R13, R1)
\r
2450 ;=========================================================================================
\r
2451 ; 7.11 Copy Init section from ROM to RAM
\r
2452 ;=========================================================================================
\r
2454 ; All initialised data's (e.g. int i=1) must be stored in ROM/FLASH area.
\r
2456 ; The Application must copy the Section (Init) into the RAM area.
\r
2457 LDI #_RAM_INIT, R0
\r
2458 LDI #_ROM_INIT, R1
\r
2459 LDI #sizeof(INIT), R2
\r
2461 BEQ:D copy_rom_end
\r
2470 LDUB @(R13, R1), R12
\r
2473 STB R12, @(R13, R0)
\r
2475 BEQ:D copy_rom_end
\r
2478 LD @(R13, R1), R12
\r
2480 ST R12, @(R13, R0)
\r
2484 ;=========================================================================================
\r
2485 ; 7.12 C library initialization
\r
2486 ;=========================================================================================
\r
2487 #if CLIBINIT == ON
\r
2488 CALL32 __stream_init, r12 ; initialise library
\r
2490 ;=========================================================================================
\r
2491 ; 7.13 call C++ constructors
\r
2492 ;=========================================================================================
\r
2493 #if CPLUSPLUS == ON
\r
2494 LDI #___call_dtors, r4
\r
2495 CALL32 _atexit, r12
\r
2497 LDI #EXT_CTOR_DTOR, r8
\r
2498 LDI #EXT_CTOR_DTOR + sizeof(EXT_CTOR_DTOR), r9
\r
2511 ;=========================================================================================
\r
2512 ; 7.14 call main routine
\r
2513 ;=========================================================================================
\r
2514 ClearRCwatchdog ; clear harware watchdog
\r
2515 LDI:8 #0, r4 ; Set the 1st parameter for main to 0.
\r
2516 CALL32:d _main, r12
\r
2517 LDI:8 #0, r5 ; Set the 2nd parameter for main to 0.
\r
2518 #if CLIBINIT == ON
\r
2523 #if CPLUSPLUS == ON
\r
2527 ;=========================================================================================
\r
2528 ; 7.15 Return from main function
\r
2529 ;=========================================================================================
\r
projects / pyfrprog.git / blob