usb/host/ohci.c

   1 /*
   2        ppcskel - a Free Software replacement for the Nintendo/BroadOn bootloader.
   3        ohci hardware support
   4
   5 Copyright (C) 2009     Bernhard Urban <lewurm@gmx.net>
   6 Copyright (C) 2009     Sebastian Falbesoner <sebastian.falbesoner@gmail.com>
   7
   8 # This code is licensed to you under the terms of the GNU GPL, version 2;
   9 # see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
  10 */
  11
  12 #include "../../bootmii_ppc.h"
  13 #include "../../hollywood.h"
  14 #include "../../irq.h"
  15 #include "../../string.h"
  16 #include "../../malloc.h"
  17 #include "ohci.h"
  18 #include "host.h"
  19 #include "../usbspec/usb11spec.h"
  20
  21 /* activate control_quirk */
  22 #define _USE_C_Q
  23
  24 /* macro for accessing u32 variables that need to be in little endian byte order;
  25  *
  26  * whenever you read or write from an u32 field that the ohci host controller
  27  * will read or write from too, use this macro for access!
  28  */
  29 #define LE(dword) (u32)( (((dword) & 0xFF000000) >> 24) | \
  30                            (((dword) & 0x00FF0000) >> 8)  | \
  31                            (((dword) & 0x0000FF00) << 8)  | \
  32                            (((dword) & 0x000000FF) << 24) )
  33
  34 static struct general_td *allocate_general_td();
  35 static void dbg_op_state(u32 reg);
  36 static void configure_ports(u8 from_init, u32 reg);
  37 static void setup_port(u32 ohci, u32 reg, u8 from_init);
  38
  39 static struct ohci_hcca hcca_oh0;
  40 static struct ohci_hcca hcca_oh1;
  41
  42
  43 static struct general_td *allocate_general_td()
  44 {
  45         struct general_td *td;
  46         td = (struct general_td *)memalign(16, sizeof(struct general_td));
  47         memset(td, 0, sizeof(struct general_td));
  48         td->flags = LE(0);
  49         td->nexttd = LE(0);
  50         td->cbp = td->be = LE(0);
  51         return td;
  52 }
  53
  54
  55 static void dbg_op_state(u32 reg)
  56 {
  57         switch (read32(reg+OHCI_HC_CONTROL) & OHCI_CTRL_HCFS) {
  58                 case OHCI_USB_SUSPEND:
  59                         printf("ohci-- OHCI_USB_SUSPEND\n");
  60                         break;
  61                 case OHCI_USB_RESET:
  62                         printf("ohci-- OHCI_USB_RESET\n");
  63                         break;
  64                 case OHCI_USB_OPER:
  65                         printf("ohci-- OHCI_USB_OPER\n");
  66                         break;
  67                 case OHCI_USB_RESUME:
  68                         printf("ohci-- OHCI_USB_RESUME\n");
  69                         break;
  70         }
  71 }
  72
  73 #ifdef _DU_OHCI_F_HALT
  74 static void dbg_td_flag(u32 flag)
  75 {
  76         printf("**************** dbg_td_flag: 0x%08X ***************\n", flag);
  77         printf("CC: %X\tshould be 0, see page 32 (ohci spec)\n", (flag>>28)&0xf);
  78         printf("EC: %X\tsee page 20 (ohci spec)\n", (flag>>26)&3);
  79         printf(" T: %X\n", (flag>>24)&3);
  80         printf("DI: %X\n", (flag>>21)&7);
  81         printf("DP: %X\n", (flag>>19)&3);
  82         printf(" R: %X\n", (flag>>18)&1);
  83         printf("********************************************************\n");
  84 }
  85 #endif
  86
  87 static void general_td_fill(struct general_td *dest, const struct usb_transfer_descriptor *src)
  88 {
  89         if(src->actlen) {
  90                 dest->cbp = LE(virt_to_phys(src->buffer));
  91                 dest->be = LE(LE(dest->cbp) + src->actlen - 1);
  92                 /* save virtual address here */
  93                 dest->bufaddr = (u32) src->buffer;
  94         }
  95         else {
  96                 dest->cbp = dest->be = LE(0);
  97                 dest->bufaddr = 0;
  98         }
  99
 100         dest->buflen = src->actlen;
 101
 102         dest->flags &= LE(~OHCI_TD_DIRECTION_PID_MASK);
 103         switch(src->pid) {
 104                 case USB_PID_SETUP:
 105 #ifdef _DU_OHCI_Q
 106                         printf("pid_setup\n");
 107 #endif
 108                         dest->flags |= LE(OHCI_TD_DIRECTION_PID_SETUP);
 109                         dest->flags |= LE(OHCI_TD_TOGGLE_0);
 110                         dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
 111                         break;
 112                 case USB_PID_OUT:
 113 #ifdef _DU_OHCI_Q
 114                         printf("pid_out\n");
 115 #endif
 116                         dest->flags |= LE(OHCI_TD_DIRECTION_PID_OUT);
 117                         dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
 118
 119                         /*
 120                          * TODO: just temporary solution! (consider it with len?)
 121                          * there can be also regular PID_OUT pakets
 122                          */
 123                         dest->flags |= LE(OHCI_TD_TOGGLE_1);
 124                         break;
 125                 case USB_PID_IN:
 126 #ifdef _DU_OHCI_Q
 127                         printf("pid_in\n");
 128 #endif
 129                         dest->flags |= LE(OHCI_TD_DIRECTION_PID_IN);
 130                         if(src->maxp > src->actlen) {
 131                                 dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
 132 #ifdef _DU_OHCI_Q
 133                                 printf("round buffer!\n");
 134 #endif
 135                         }
 136                         /*
 137                          * let the endpoint do the togglestuff!
 138                          * TODO: just temporary solution!
 139                          * there can be also inregular PID_IN pakets (@Status Stage)
 140                          */
 141                         dest->flags |= LE(OHCI_TD_TOGGLE_CARRY);
 142                         break;
 143         }
 144         dest->flags |= LE(OHCI_TD_SET_DELAY_INTERRUPT(7));
 145 }
 146
 147 #ifdef _DU_OHCI_F_HALT
 148 static void dump_address(void *addr, u32 size, const char* str)
 149 {
 150         printf("%s hexdump (%d) @ 0x%08X:\n", str, size, addr);
 151         hexdump(addr, size);
 152 }
 153 #endif
 154
 155 static struct endpoint_descriptor _edhead;
 156 struct endpoint_descriptor *edhead = 0;
 157 void hcdi_fire(u32 reg)
 158 {
 159 #ifdef _DU_OHCI_F
 160         printf("<^>  <^>  <^> hcdi_fire(start)\n");
 161 #endif
 162
 163         if(edhead == 0)
 164                 return;
 165
 166 #ifdef _USE_C_Q
 167         /* quirk... 11ms seems to be a minimum :O */
 168         udelay(11000);
 169 #endif
 170
 171         write32(reg+OHCI_HC_CTRL_HEAD_ED, virt_to_phys(edhead));
 172
 173         /* sync it all */
 174         sync_after_write(edhead, sizeof(struct endpoint_descriptor));
 175 #ifdef _DU_OHCI_F
 176         dump_address(edhead, sizeof(struct endpoint_descriptor), "edhead(before)");
 177 #endif
 178
 179         struct general_td *x = phys_to_virt(LE(edhead->headp) & OHCI_ENDPOINT_HEAD_MASK);
 180         while(virt_to_phys(x)) {
 181                 sync_after_write(x, sizeof(struct general_td));
 182 #ifdef _DU_OHCI_F
 183                 dump_address(x, sizeof(struct general_td), "x(before)");
 184 #endif
 185
 186                 if(x->buflen > 0) {
 187                         sync_after_write((void*) phys_to_virt(LE(x->cbp)), x->buflen);
 188 #ifdef _DU_OHCI_F
 189                         dump_address((void*) phys_to_virt(LE(x->cbp)), x->buflen, "x->cbp(before)");
 190 #endif
 191                 }
 192                 x = phys_to_virt(LE(x->nexttd));
 193         }
 194
 195         /* trigger control list */
 196         set32(reg+OHCI_HC_CONTROL, OHCI_CTRL_CLE);
 197         write32(reg+OHCI_HC_COMMAND_STATUS, OHCI_CLF);
 198
 199         struct general_td *n=0, *prev = 0, *next = 0;
 200         /* poll until edhead->headp is null */
 201         do {
 202                 sync_before_read(edhead, sizeof(struct endpoint_descriptor));
 203 #ifdef _DU_OHCI_F
 204                 printf("edhead->headp: 0x%08X\n", LE(edhead->headp));
 205                 udelay(10000);
 206 #endif
 207
 208                 /* if halted, debug output plz. will break the transfer */
 209                 if((LE(edhead->headp) & OHCI_ENDPOINT_HALTED)) {
 210                         n = phys_to_virt(LE(edhead->headp)&~0xf);
 211                         prev = phys_to_virt((u32)prev);
 212 #ifdef _DU_OHCI_F_HALT
 213                         printf("halted!\n");
 214 #endif
 215
 216                         sync_before_read((void*) n, sizeof(struct general_td));
 217 #ifdef _DU_OHCI_F_HALT
 218                         printf("n: 0x%08X\n", n);
 219                         dump_address(n, sizeof(struct general_td), "n(after)");
 220 #endif
 221                         if(n->buflen > 0) {
 222                                 sync_before_read((void*) n->bufaddr, n->buflen);
 223 #ifdef _DU_OHCI_F_HALT
 224                                 dump_address((void*) n->bufaddr, n->buflen, "n->bufaddr(after)");
 225 #endif
 226                         }
 227 #ifdef _DU_OHCI_F_HALT
 228                         dbg_td_flag(LE(n->flags));
 229 #endif
 230
 231                         sync_before_read((void*) prev, sizeof(struct general_td));
 232 #ifdef _DU_OHCI_F_HALT
 233                         printf("prev: 0x%08X\n", prev);
 234                         dump_address(prev, sizeof(struct general_td), "prev(after)");
 235 #endif
 236                         if(prev->buflen >0) {
 237                                 sync_before_read((void*) prev->bufaddr, prev->buflen);
 238 #ifdef _DU_OHCI_F_HALT
 239                                 dump_address((void*) prev->bufaddr, prev->buflen, "prev->bufaddr(after)");
 240 #endif
 241                         }
 242 #ifdef _DU_OHCI_F_HALT
 243                         dbg_td_flag(LE(prev->flags));
 244                         printf("halted end!\n");
 245 #endif
 246                         return;
 247                 }
 248                 prev = (struct general_td*) (LE(edhead->headp)&~0xf);
 249         } while(LE(edhead->headp)&~0xf);
 250
 251         n = phys_to_virt(read32(reg+OHCI_HC_DONE_HEAD) & ~1);
 252 #ifdef _DU_OHCI_F
 253         printf("hc_done_head: 0x%08X\n", read32(reg+OHCI_HC_DONE_HEAD));
 254 #endif
 255
 256         prev = 0; next = 0;
 257         /* reverse done queue */
 258         while(virt_to_phys(n) && edhead->tdcount) {
 259                 sync_before_read((void*) n, sizeof(struct general_td));
 260 #ifdef _DU_OHCI_F
 261                 printf("n: 0x%08X\n", n);
 262                 printf("next: 0x%08X\n", next);
 263                 printf("prev: 0x%08X\n", prev);
 264 #endif
 265
 266                 next = n;
 267                 n = (struct general_td*) phys_to_virt(LE(n->nexttd));
 268                 next->nexttd = (u32) prev;
 269                 prev = next;
 270
 271                 edhead->tdcount--;
 272         }
 273
 274         n = next;
 275         prev = 0;
 276         while(virt_to_phys(n)) {
 277 #ifdef _DU_OHCI_F
 278                 dump_address(n, sizeof(struct general_td), "n(after)");
 279 #endif
 280                 if(n->buflen > 0) {
 281                         sync_before_read((void*) n->bufaddr, n->buflen);
 282 #ifdef _DU_OHCI_F
 283                         dump_address((void*) n->bufaddr, n->buflen, "n->bufaddr(after)");
 284 #endif
 285                 }
 286 #ifdef _DU_OHCI_F
 287                 dbg_td_flag(LE(n->flags));
 288 #endif
 289                 prev = n;
 290                 n = (struct general_td*) n->nexttd;
 291                 free(prev);
 292         }
 293
 294         if(reg == OHCI0_REG_BASE) {
 295                 hcca_oh0.done_head = 0;
 296                 sync_after_write(&hcca_oh0, sizeof(hcca_oh0));
 297         } else if (reg == OHCI1_REG_BASE) {
 298                 hcca_oh1.done_head = 0;
 299                 sync_after_write(&hcca_oh1, sizeof(hcca_oh1));
 300         }
 301
 302         write32(reg+OHCI_HC_CONTROL, read32(reg+OHCI_HC_CONTROL)&~OHCI_CTRL_CLE);
 303
 304         edhead = 0;
 305
 306 #ifdef _DU_OHCI_F
 307         printf("<^>  <^>  <^> hcdi_fire(end)\n");
 308 #endif
 309 }
 310
 311 /**
 312  * Enqueue a transfer descriptor.
 313  */
 314 u8 hcdi_enqueue(const struct usb_transfer_descriptor *td, u32 reg) {
 315 #ifdef _DU_OHCI_Q
 316         printf("*()*()*()*()*()*()*() hcdi_enqueue(start)\n");
 317 #endif
 318         if(!edhead) {
 319                 edhead = &_edhead;
 320                 memset(edhead, 0, sizeof(struct endpoint_descriptor));
 321                 edhead->flags = LE(OHCI_ENDPOINT_GENERAL_FORMAT);
 322                 edhead->headp = edhead->tailp = edhead->nexted = LE(0);
 323                 if(td->fullspeed) {
 324                         edhead->flags |= LE(OHCI_ENDPOINT_FULL_SPEED);
 325                 } else {
 326                         edhead->flags |= LE(OHCI_ENDPOINT_LOW_SPEED);
 327                 }
 328                 edhead->flags |= LE(OHCI_ENDPOINT_SET_DEVICE_ADDRESS(td->devaddress) |
 329                                 OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(td->endpoint) |
 330                                 OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(td->maxp));
 331                 edhead->tdcount = 0;
 332         }
 333
 334         struct general_td *tdhw = allocate_general_td();
 335         general_td_fill(tdhw, td);
 336         edhead->tdcount ++;
 337
 338         if(!edhead->headp) {
 339                 /* first transfer */
 340                 edhead->headp = LE(virt_to_phys((void*) ((u32)tdhw & OHCI_ENDPOINT_HEAD_MASK)));
 341         }
 342         else {
 343                 /* headp in endpoint already exists
 344                  * => go to list end
 345                  */
 346                 struct general_td *n = (struct general_td*) phys_to_virt(LE(edhead->headp) & OHCI_ENDPOINT_HEAD_MASK);
 347                 while(LE(n->nexttd)) {
 348                         n = phys_to_virt(LE(n->nexttd));
 349                 }
 350                 n->nexttd = LE(virt_to_phys((void*) ((u32)tdhw & OHCI_ENDPOINT_HEAD_MASK)));
 351 #ifdef _DU_OHCI_Q
 352                 printf("n: 0x%08X\n", n);
 353                 printf("n->nexttd: 0x%08X\n", phys_to_virt(LE(n->nexttd)));
 354 #endif
 355         }
 356
 357 #ifdef _DU_OHCI_Q
 358         printf("*()*()*()*()*()*()*() hcdi_enqueue(end)\n");
 359 #endif
 360         return 0;
 361 }
 362
 363
 364 /**
 365  * Remove an transfer descriptor from transfer queue.
 366  */
 367 u8 hcdi_dequeue(struct usb_transfer_descriptor *td, u32 reg) {
 368         return 0;
 369 }
 370
 371 void hcdi_init(u32 reg)
 372 {
 373         printf("ohci-- init\n");
 374         dbg_op_state(reg);
 375
 376         /* disable hc interrupts */
 377         set32(reg+OHCI_HC_INT_DISABLE, OHCI_INTR_MIE);
 378
 379         /* save fmInterval and calculate FSMPS */
 380 #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
 381 #define FI 0x2edf /* 12000 bits per frame (-1) */
 382         u32 fmint = read32(reg+OHCI_HC_FM_INTERVAL) & 0x3fff;
 383         if(fmint != FI)
 384                 printf("ohci-- fminterval delta: %d\n", fmint - FI);
 385         fmint |= FSMP (fmint) << 16;
 386
 387         /* enable interrupts of both usb host controllers */
 388         set32(EHCI_CTL, EHCI_CTL_OH0INTE | EHCI_CTL_OH1INTE | 0xe0000);
 389
 390         /* reset HC */
 391         write32(reg+OHCI_HC_COMMAND_STATUS, OHCI_HCR);
 392
 393         /* wait max. 30us */
 394         u32 ts = 30;
 395         while ((read32(reg+OHCI_HC_COMMAND_STATUS) & OHCI_HCR) != 0) {
 396                  if(--ts == 0) {
 397                         printf("ohci-- FAILED");
 398                         return;
 399                  }
 400                  udelay(1);
 401         }
 402
 403         /* disable interrupts; 2ms timelimit here!
 404            now we're in the SUSPEND state ... must go OPERATIONAL
 405            within 2msec else HC enters RESUME */
 406
 407         u32 cookie = irq_kill();
 408
 409         /* Tell the controller where the control and bulk lists are
 410          * The lists are empty now. */
 411         write32(reg+OHCI_HC_CTRL_HEAD_ED, 0);
 412         write32(reg+OHCI_HC_BULK_HEAD_ED, 0);
 413
 414         /* set hcca adress */
 415         if(reg == OHCI0_REG_BASE) {
 416                 sync_after_write(&hcca_oh0, 256);
 417                 write32(reg+OHCI_HC_HCCA, virt_to_phys(&hcca_oh0));
 418         } else {
 419                 sync_after_write(&hcca_oh1, 256);
 420                 write32(reg+OHCI_HC_HCCA, virt_to_phys(&hcca_oh1));
 421         }
 422
 423         /* set periodicstart */
 424 #define FIT (1<<31)
 425         u32 fmInterval = read32(reg+OHCI_HC_FM_INTERVAL) &0x3fff;
 426         u32 fit = read32(reg+OHCI_HC_FM_INTERVAL) & FIT;
 427
 428         write32(reg+OHCI_HC_FM_INTERVAL, fmint | (fit ^ FIT));
 429         write32(reg+OHCI_HC_PERIODIC_START, ((9*fmInterval)/10)&0x3fff);
 430
 431         /* testing bla */
 432         if ((read32(reg+OHCI_HC_FM_INTERVAL) & 0x3fff0000) == 0 || !read32(reg+OHCI_HC_PERIODIC_START)) {
 433                 printf("ohci-- w00t, fail!! see ohci-hcd.c:669\n");
 434         }
 435
 436         /* start HC operations */
 437         write32(reg+OHCI_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER);
 438
 439         /* wake on ConnectStatusChange, matching external hubs */
 440         write32(reg+OHCI_HC_RH_STATUS, /*RH_HS_DRWE |*/ RH_HS_LPSC);
 441
 442         /* Choose the interrupts we care about now, others later on demand */
 443         write32(reg+OHCI_HC_INT_STATUS, ~0);
 444         write32(reg+OHCI_HC_INT_ENABLE, OHCI_INTR_INIT);
 445
 446         //wtf?
 447         wait_ms ((read32(reg+OHCI_HC_RH_DESCRIPTOR_A) >> 23) & 0x1fe);
 448
 449         configure_ports((u8)1, reg);
 450         irq_restore(cookie);
 451
 452         dbg_op_state(reg);
 453 }
 454
 455 static void configure_ports(u8 from_init, u32 reg)
 456 {
 457 #ifdef _DU_OHCI_RH
 458         printf("=== Roothub @ %s ===\n", reg == OHCI0_REG_BASE ? "OHCI0" : "OHCI1");
 459         printf("OHCI_HC_RH_DESCRIPTOR_A:\t0x%08X\n", read32(reg+OHCI_HC_RH_DESCRIPTOR_A));
 460         printf("OHCI_HC_RH_DESCRIPTOR_B:\t0x%08X\n", read32(reg+OHCI_HC_RH_DESCRIPTOR_B));
 461         printf("OHCI_HC_RH_STATUS:\t\t0x%08X\n", read32(reg+OHCI_HC_RH_STATUS));
 462         printf("OHCI_HC_RH_PORT_STATUS_1:\t0x%08X\n", read32(reg+OHCI_HC_RH_PORT_STATUS_1));
 463         printf("OHCI_HC_RH_PORT_STATUS_2:\t0x%08X\n", read32(reg+OHCI_HC_RH_PORT_STATUS_2));
 464 #endif
 465
 466         setup_port(reg, reg+OHCI_HC_RH_PORT_STATUS_1, from_init);
 467         setup_port(reg, reg+OHCI_HC_RH_PORT_STATUS_2, from_init);
 468 #ifdef _DU_OHCI_RH
 469         printf("configure_ports done\n");
 470 #endif
 471 }
 472
 473 static void setup_port(u32 ohci, u32 reg, u8 from_init)
 474 {
 475         u32 port = read32(reg);
 476         if((port & RH_PS_CCS) && ((port & RH_PS_CSC) || from_init)) {
 477                 write32(reg, RH_PS_CSC);
 478
 479                 wait_ms(120);
 480
 481                 /* clear CSC flag, set PES and start port reset (PRS) */
 482                 write32(reg, RH_PS_PES);
 483                 while(!(read32(reg) & RH_PS_PES)) {
 484 #ifdef _DU_OHCI_RH
 485                         printf("fu\n");
 486 #endif
 487                         return;
 488                 }
 489
 490                 write32(reg, RH_PS_PRS);
 491
 492                 /* spin until port reset is complete */
 493                 while(!(read32(reg) & RH_PS_PRSC)); // hint: it may stuck here
 494 #ifdef _DU_OHCI_RH
 495                 printf("loop done\n");
 496 #endif
 497
 498                 /* returns usb_device struct */
 499                 (void) usb_add_device((read32(reg) & RH_PS_LSDA) >> 8, ohci);
 500         }
 501 }
 502
 503 void hcdi_irq(u32 reg)
 504 {
 505         /* read interrupt status */
 506         u32 flags = read32(reg+OHCI_HC_INT_STATUS);
 507
 508         /* when all bits are set to 1 some problem occured */
 509         if (flags == 0xffffffff) {
 510                 printf("ohci-- Houston, we have a serious problem! :(\n");
 511                 return;
 512         }
 513
 514         /* only care about interrupts that are enabled */
 515         flags &= read32(reg+OHCI_HC_INT_ENABLE);
 516
 517         /* nothing to do? */
 518         if (flags == 0) {
 519                 printf("OHCI Interrupt occured: but not for you! WTF?!\n");
 520                 return;
 521         }
 522
 523         printf("OHCI Interrupt occured: ");
 524         /* UnrecoverableError */
 525         if (flags & OHCI_INTR_UE) {
 526                 printf("UnrecoverableError\n");
 527                 /* TODO: well, I don't know... nothing,
 528                  *       because it won't happen anyway? ;-) */
 529         }
 530
 531         /* RootHubStatusChange */
 532         if (flags & OHCI_INTR_RHSC) {
 533                 printf("RootHubStatusChange\n");
 534                 /* TODO: set some next_statechange variable... */
 535                 configure_ports(0, reg);
 536                 write32(reg+OHCI_HC_INT_STATUS, OHCI_INTR_RD | OHCI_INTR_RHSC);
 537         }
 538         /* ResumeDetected */
 539         else if (flags & OHCI_INTR_RD) {
 540                 printf("ResumeDetected\n");
 541                 write32(reg+OHCI_HC_INT_STATUS, OHCI_INTR_RD);
 542                 /* TODO: figure out what the linux kernel does here... */
 543         }
 544
 545         /* WritebackDoneHead */
 546         if (flags & OHCI_INTR_WDH) {
 547                 printf("WritebackDoneHead\n");
 548                 /* basically the linux irq handler reverse TDs to their urbs
 549                  * and set done_head to null.
 550                  * since we are polling atm, just should do the latter task.
 551                  * however, this won't work for now (i don't know why...)
 552                  * TODO!
 553                  */
 554 #if 0
 555                 sync_before_read(&hcca_oh0, 256);
 556                 hcca_oh0.done_head = 0;
 557                 sync_after_write(&hcca_oh0, 256);
 558 #endif
 559         }
 560
 561         /* TODO: handle any pending URB/ED unlinks... */
 562
 563 #define HC_IS_RUNNING() 1 /* dirty, i know... just a temporary solution */
 564         if (HC_IS_RUNNING()) {
 565                 write32(reg+OHCI_HC_INT_STATUS, flags);
 566                 write32(reg+OHCI_HC_INT_ENABLE, OHCI_INTR_MIE);
 567         }
 568 }
 569
 570 void show_frame_no(u32 reg)
 571 {
 572         if(reg == OHCI0_REG_BASE) {
 573                 sync_before_read(&hcca_oh0, 256);
 574                 printf("***** frame_no: %d *****\n", LE(hcca_oh0.frame_no));
 575         } else if (reg == OHCI1_REG_BASE) {
 576                 sync_before_read(&hcca_oh1, 256);
 577                 printf("***** frame_no: %d *****\n", LE(hcca_oh1.frame_no));
 578         }
 579 }