2 ppcskel - a Free Software replacement for the Nintendo/BroadOn bootloader.
5 Copyright (C) 2009 Bernhard Urban <lewurm@gmx.net>
6 Copyright (C) 2009 Sebastian Falbesoner <sebastian.falbesoner@gmail.com>
8 # This code is licensed to you under the terms of the GNU GPL, version 2;
9 # see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
12 #include "../../bootmii_ppc.h"
13 #include "../../hollywood.h"
14 #include "../../irq.h"
15 #include "../../string.h"
16 #include "../../malloc.h"
19 #include "../usbspec/usb11spec.h"
21 /* activate control_quirk */
24 /* macro for accessing u32 variables that need to be in little endian byte order;
26 * whenever you read or write from an u32 field that the ohci host controller
27 * will read or write from too, use this macro for access!
29 #define LE(dword) (u32)( (((dword) & 0xFF000000) >> 24) | \
30 (((dword) & 0x00FF0000) >> 8) | \
31 (((dword) & 0x0000FF00) << 8) | \
32 (((dword) & 0x000000FF) << 24) )
34 static struct general_td *allocate_general_td();
35 static void dbg_op_state(u32 reg);
36 static void configure_ports(u8 from_init, u32 reg);
37 static struct usb_device *setup_port(u32 ohci, u32 reg, u8 pport, u8 from_init);
38 static void set_target_hcca(u32 reg);
40 static struct ohci_hcca hcca_oh0;
41 static struct ohci_hcca hcca_oh1;
42 struct ohci_hcca *hcca;
44 static struct general_td *allocate_general_td()
46 struct general_td *td;
47 td = (struct general_td *)memalign(16, sizeof(struct general_td));
48 memset(td, 0, sizeof(struct general_td));
51 td->cbp = td->be = LE(0);
56 static void dbg_op_state(u32 reg)
58 switch (read32(reg+OHCI_HC_CONTROL) & OHCI_CTRL_HCFS) {
59 case OHCI_USB_SUSPEND:
60 printf("ohci-- OHCI_USB_SUSPEND\n");
63 printf("ohci-- OHCI_USB_RESET\n");
66 printf("ohci-- OHCI_USB_OPER\n");
69 printf("ohci-- OHCI_USB_RESUME\n");
74 #ifdef _DU_OHCI_F_HALT
75 static void dbg_td_flag(u32 flag)
77 printf("**************** dbg_td_flag: 0x%08X ***************\n", flag);
78 printf("CC: %X\tshould be 0, see page 32 (ohci spec)\n", (flag>>28)&0xf);
79 printf("EC: %X\tsee page 20 (ohci spec)\n", (flag>>26)&3);
80 printf(" T: %X\n", (flag>>24)&3);
81 printf("DI: %X\n", (flag>>21)&7);
82 printf("DP: %X\n", (flag>>19)&3);
83 printf(" R: %X\n", (flag>>18)&1);
84 printf("********************************************************\n");
88 static void general_td_fill(struct general_td *dest, const struct usb_transfer_descriptor *src)
91 dest->cbp = LE(virt_to_phys(src->buffer));
92 dest->be = LE(LE(dest->cbp) + src->actlen - 1);
93 /* save virtual address here */
94 dest->bufaddr = (u32) src->buffer;
97 dest->cbp = dest->be = LE(0);
101 dest->buflen = src->actlen;
103 dest->flags &= LE(~OHCI_TD_DIRECTION_PID_MASK);
107 printf("pid_setup\n");
109 dest->flags |= LE(OHCI_TD_DIRECTION_PID_SETUP);
110 dest->flags |= LE(OHCI_TD_TOGGLE_0);
111 dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
117 dest->flags |= LE(OHCI_TD_DIRECTION_PID_OUT);
118 dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
120 dest->flags |= src->togl ? LE(OHCI_TD_TOGGLE_1) : LE(OHCI_TD_TOGGLE_0);
126 dest->flags |= LE(OHCI_TD_DIRECTION_PID_IN);
127 if(src->maxp > src->actlen) {
128 dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
130 printf("round buffer!\n");
133 dest->flags |= src->togl ? LE(OHCI_TD_TOGGLE_1) : LE(OHCI_TD_TOGGLE_0);
136 dest->flags |= LE(OHCI_TD_SET_DELAY_INTERRUPT(7));
139 #ifdef _DU_OHCI_F_HALT
140 static void dump_address(void *addr, u32 size, const char* str)
142 printf("%s hexdump (%d) @ 0x%08X:\n", str, size, addr);
147 static struct endpoint_descriptor _edhead;
148 struct endpoint_descriptor *edhead = 0;
149 void hcdi_fire(u32 reg)
152 printf("<^> <^> <^> hcdi_fire(start)\n");
159 switch(edhead->type) {
162 /* quirk... 11ms seems to be a minimum :O */
165 write32(reg+OHCI_HC_CTRL_HEAD_ED, virt_to_phys(edhead));
170 set_target_hcca(reg);
171 sync_before_read(hcca, sizeof(struct ohci_hcca));
172 for(itmp = 0; itmp < NUM_INITS; itmp++) {
173 hcca->int_table[itmp] = LE(virt_to_phys(edhead));
175 sync_after_write(hcca, sizeof(struct ohci_hcca));
179 write32(reg+OHCI_HC_BULK_HEAD_ED, virt_to_phys(edhead));
187 sync_after_write(edhead, sizeof(struct endpoint_descriptor));
189 dump_address(edhead, sizeof(struct endpoint_descriptor), "edhead(before)");
192 struct general_td *x = phys_to_virt(LE(edhead->headp) & OHCI_ENDPOINT_HEAD_MASK);
193 while(virt_to_phys(x)) {
194 sync_after_write(x, sizeof(struct general_td));
196 dump_address(x, sizeof(struct general_td), "x(before)");
200 sync_after_write((void*) phys_to_virt(LE(x->cbp)), x->buflen);
202 dump_address((void*) phys_to_virt(LE(x->cbp)), x->buflen, "x->cbp(before)");
205 x = phys_to_virt(LE(x->nexttd));
209 switch(edhead->type) {
211 /* trigger control list */
212 set32(reg+OHCI_HC_CONTROL, OHCI_CTRL_CLE);
213 write32(reg+OHCI_HC_COMMAND_STATUS, OHCI_CLF);
217 /* trigger periodic list */
218 set32(reg+OHCI_HC_CONTROL, OHCI_CTRL_PLE);
222 /* trigger bulk list */
223 set32(reg+OHCI_HC_CONTROL, OHCI_CTRL_BLE);
224 write32(reg+OHCI_HC_COMMAND_STATUS, OHCI_BLF);
231 struct general_td *n=0, *prev = 0, *next = 0;
232 /* poll until edhead->headp is null */
234 sync_before_read(edhead, sizeof(struct endpoint_descriptor));
236 printf("edhead->headp: 0x%08X\n", LE(edhead->headp));
239 /* if halted, debug output plz. will break the transfer */
240 if((LE(edhead->headp) & OHCI_ENDPOINT_HALTED)) {
241 n = phys_to_virt(LE(edhead->headp)&~0xf);
242 prev = phys_to_virt((u32)prev);
243 #ifdef _DU_OHCI_F_HALT
247 sync_before_read((void*) n, sizeof(struct general_td));
248 #ifdef _DU_OHCI_F_HALT
249 printf("n: 0x%08X\n", n);
250 dump_address(n, sizeof(struct general_td), "n(after)");
253 sync_before_read((void*) n->bufaddr, n->buflen);
254 #ifdef _DU_OHCI_F_HALT
255 dump_address((void*) n->bufaddr, n->buflen, "n->bufaddr(after)");
258 #ifdef _DU_OHCI_F_HALT
259 dbg_td_flag(LE(n->flags));
262 sync_before_read((void*) prev, sizeof(struct general_td));
263 #ifdef _DU_OHCI_F_HALT
264 printf("prev: 0x%08X\n", prev);
265 dump_address(prev, sizeof(struct general_td), "prev(after)");
267 if(prev->buflen >0) {
268 sync_before_read((void*) prev->bufaddr, prev->buflen);
269 #ifdef _DU_OHCI_F_HALT
270 dump_address((void*) prev->bufaddr, prev->buflen, "prev->bufaddr(after)");
273 #ifdef _DU_OHCI_F_HALT
274 dbg_td_flag(LE(prev->flags));
275 printf("halted end!\n");
279 prev = (struct general_td*) (LE(edhead->headp)&~0xf);
280 } while(LE(edhead->headp)&~0xf);
282 n = phys_to_virt(read32(reg+OHCI_HC_DONE_HEAD) & ~1);
284 printf("hc_done_head: 0x%08X\n", read32(reg+OHCI_HC_DONE_HEAD));
288 /* reverse done queue */
289 while(virt_to_phys(n) && edhead->tdcount) {
290 sync_before_read((void*) n, sizeof(struct general_td));
292 printf("n: 0x%08X\n", n);
293 printf("next: 0x%08X\n", next);
294 printf("prev: 0x%08X\n", prev);
298 n = (struct general_td*) phys_to_virt(LE(n->nexttd));
299 next->nexttd = (u32) prev;
307 while(virt_to_phys(n)) {
309 dump_address(n, sizeof(struct general_td), "n(after)");
312 sync_before_read((void*) n->bufaddr, n->buflen);
314 dump_address((void*) n->bufaddr, n->buflen, "n->bufaddr(after)");
318 dbg_td_flag(LE(n->flags));
321 n = (struct general_td*) n->nexttd;
326 set_target_hcca(reg);
327 sync_before_read(hcca, sizeof(struct ohci_hcca));
330 switch(edhead->type) {
332 write32(reg+OHCI_HC_CONTROL, read32(reg+OHCI_HC_CONTROL)&~OHCI_CTRL_CLE);
336 write32(reg+OHCI_HC_CONTROL, read32(reg+OHCI_HC_CONTROL)&~OHCI_CTRL_PLE);
337 for(jtmp = 0; jtmp < NUM_INITS; jtmp++) {
338 hcca->int_table[jtmp] = 0;
343 write32(reg+OHCI_HC_CONTROL, read32(reg+OHCI_HC_CONTROL)&~OHCI_CTRL_BLE);
351 sync_after_write(hcca, sizeof(struct ohci_hcca));
356 printf("<^> <^> <^> hcdi_fire(end)\n");
361 * Enqueue a transfer descriptor.
363 u8 hcdi_enqueue(const struct usb_transfer_descriptor *td, u32 reg) {
365 printf("*()*()*()*()*()*()*() hcdi_enqueue(start)\n");
369 memset(edhead, 0, sizeof(struct endpoint_descriptor));
370 edhead->flags = LE(OHCI_ENDPOINT_GENERAL_FORMAT);
371 edhead->headp = edhead->tailp = edhead->nexted = LE(0);
373 edhead->flags |= LE(OHCI_ENDPOINT_FULL_SPEED);
375 edhead->flags |= LE(OHCI_ENDPOINT_LOW_SPEED);
377 edhead->flags |= LE(OHCI_ENDPOINT_SET_DEVICE_ADDRESS(td->devaddress) |
378 OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(td->endpoint) |
379 OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(td->maxp));
381 edhead->type = td->type;
384 struct general_td *tdhw = allocate_general_td();
385 general_td_fill(tdhw, td);
390 edhead->headp = LE(virt_to_phys((void*) ((u32)tdhw & OHCI_ENDPOINT_HEAD_MASK)));
393 /* headp in endpoint already exists
396 struct general_td *n = (struct general_td*) phys_to_virt(LE(edhead->headp) & OHCI_ENDPOINT_HEAD_MASK);
397 while(LE(n->nexttd)) {
398 n = phys_to_virt(LE(n->nexttd));
400 n->nexttd = LE(virt_to_phys((void*) ((u32)tdhw & OHCI_ENDPOINT_HEAD_MASK)));
402 printf("n: 0x%08X\n", n);
403 printf("n->nexttd: 0x%08X\n", phys_to_virt(LE(n->nexttd)));
408 printf("*()*()*()*()*()*()*() hcdi_enqueue(end)\n");
415 * Remove an transfer descriptor from transfer queue.
417 u8 hcdi_dequeue(struct usb_transfer_descriptor *td, u32 reg) {
421 void hcdi_init(u32 reg)
423 printf("ohci-- init\n");
426 /* disable hc interrupts */
427 set32(reg+OHCI_HC_INT_DISABLE, OHCI_INTR_MIE);
429 /* save fmInterval and calculate FSMPS */
430 #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
431 #define FI 0x2edf /* 12000 bits per frame (-1) */
432 u32 fmint = read32(reg+OHCI_HC_FM_INTERVAL) & 0x3fff;
434 printf("ohci-- fminterval delta: %d\n", fmint - FI);
435 fmint |= FSMP (fmint) << 16;
437 /* enable interrupts of both usb host controllers */
438 set32(EHCI_CTL, EHCI_CTL_OH0INTE | EHCI_CTL_OH1INTE | 0xe0000);
441 write32(reg+OHCI_HC_COMMAND_STATUS, OHCI_HCR);
445 while ((read32(reg+OHCI_HC_COMMAND_STATUS) & OHCI_HCR) != 0) {
447 printf("ohci-- FAILED");
453 /* disable interrupts; 2ms timelimit here!
454 now we're in the SUSPEND state ... must go OPERATIONAL
455 within 2msec else HC enters RESUME */
457 u32 cookie = irq_kill();
459 /* Tell the controller where the control and bulk lists are
460 * The lists are empty now. */
461 write32(reg+OHCI_HC_CTRL_HEAD_ED, 0);
462 write32(reg+OHCI_HC_BULK_HEAD_ED, 0);
464 /* set hcca adress */
465 set_target_hcca(reg);
466 sync_after_write(hcca, 256);
467 write32(reg+OHCI_HC_HCCA, virt_to_phys(hcca));
469 /* set periodicstart */
471 u32 fmInterval = read32(reg+OHCI_HC_FM_INTERVAL) &0x3fff;
472 u32 fit = read32(reg+OHCI_HC_FM_INTERVAL) & FIT;
474 write32(reg+OHCI_HC_FM_INTERVAL, fmint | (fit ^ FIT));
475 write32(reg+OHCI_HC_PERIODIC_START, ((9*fmInterval)/10)&0x3fff);
478 if ((read32(reg+OHCI_HC_FM_INTERVAL) & 0x3fff0000) == 0 || !read32(reg+OHCI_HC_PERIODIC_START)) {
479 printf("ohci-- w00t, fail!! see ohci-hcd.c:669\n");
482 /* start HC operations */
483 write32(reg+OHCI_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER);
485 /* wake on ConnectStatusChange, matching external hubs */
486 write32(reg+OHCI_HC_RH_STATUS, /*RH_HS_DRWE |*/ RH_HS_LPSC);
488 /* Choose the interrupts we care about now, others later on demand */
489 write32(reg+OHCI_HC_INT_STATUS, ~0);
490 write32(reg+OHCI_HC_INT_ENABLE, OHCI_INTR_INIT);
493 wait_ms ((read32(reg+OHCI_HC_RH_DESCRIPTOR_A) >> 23) & 0x1fe);
495 configure_ports((u8)1, reg);
501 static struct usb_device *connected[2] = {NULL, NULL};
502 static void configure_ports(u8 from_init, u32 reg)
505 printf("=== Roothub @ %s ===\n", reg == OHCI0_REG_BASE ? "OHCI0" : "OHCI1");
506 printf("OHCI_HC_RH_DESCRIPTOR_A:\t0x%08X\n", read32(reg+OHCI_HC_RH_DESCRIPTOR_A));
507 printf("OHCI_HC_RH_DESCRIPTOR_B:\t0x%08X\n", read32(reg+OHCI_HC_RH_DESCRIPTOR_B));
508 printf("OHCI_HC_RH_STATUS:\t\t0x%08X\n", read32(reg+OHCI_HC_RH_STATUS));
509 printf("OHCI_HC_RH_PORT_STATUS_1:\t0x%08X\n", read32(reg+OHCI_HC_RH_PORT_STATUS_1));
510 printf("OHCI_HC_RH_PORT_STATUS_2:\t0x%08X\n", read32(reg+OHCI_HC_RH_PORT_STATUS_2));
513 struct usb_device *dtmp;
514 if(!(dtmp = setup_port(reg, reg+OHCI_HC_RH_PORT_STATUS_1, 0, from_init))) {
516 usb_remove_device(connected[0]);
523 if(!(dtmp = setup_port(reg, reg+OHCI_HC_RH_PORT_STATUS_2, 1, from_init))) {
525 usb_remove_device(connected[1]);
533 printf("configure_ports done\n");
537 static struct usb_device *setup_port(u32 ohci, u32 reg, u8 pport, u8 from_init)
539 u32 port = read32(reg);
540 if((port & RH_PS_CCS) && ((port & RH_PS_CSC) || from_init)) {
541 write32(reg, RH_PS_CSC);
545 /* clear CSC flag, set PES and start port reset (PRS) */
546 write32(reg, RH_PS_PES);
547 while(!(read32(reg) & RH_PS_PES)) {
554 write32(reg, RH_PS_PRS);
556 /* spin until port reset is complete */
557 while(!(read32(reg) & RH_PS_PRSC)); // hint: it may stuck here
559 printf("loop done\n");
562 /* returns usb_device struct */
563 return usb_add_device((read32(reg) & RH_PS_LSDA) >> 8, ohci);
565 if(port & RH_PS_CCS) {
566 return connected[pport];
571 void hcdi_irq(u32 reg)
573 /* read interrupt status */
574 u32 flags = read32(reg+OHCI_HC_INT_STATUS);
576 /* when all bits are set to 1 some problem occured */
577 if (flags == 0xffffffff) {
578 printf("ohci-- Houston, we have a serious problem! :(\n");
582 /* only care about interrupts that are enabled */
583 flags &= read32(reg+OHCI_HC_INT_ENABLE);
587 printf("OHCI Interrupt occured: but not for you! WTF?!\n");
591 printf("OHCI Interrupt occured: ");
592 /* UnrecoverableError */
593 if (flags & OHCI_INTR_UE) {
594 printf("UnrecoverableError\n");
595 /* TODO: well, I don't know... nothing,
596 * because it won't happen anyway? ;-) */
599 /* RootHubStatusChange */
600 if (flags & OHCI_INTR_RHSC) {
601 printf("RootHubStatusChange\n");
602 /* TODO: set some next_statechange variable... */
603 configure_ports(0, reg);
604 write32(reg+OHCI_HC_INT_STATUS, OHCI_INTR_RD | OHCI_INTR_RHSC);
607 else if (flags & OHCI_INTR_RD) {
608 printf("ResumeDetected\n");
609 write32(reg+OHCI_HC_INT_STATUS, OHCI_INTR_RD);
610 /* TODO: figure out what the linux kernel does here... */
613 /* WritebackDoneHead */
614 if (flags & OHCI_INTR_WDH) {
615 printf("WritebackDoneHead\n");
616 /* basically the linux irq handler reverse TDs to their urbs
617 * and set done_head to null.
618 * since we are polling atm, just should do the latter task.
619 * however, this won't work for now (i don't know why...)
623 sync_before_read(&hcca_oh0, 256);
624 hcca_oh0.done_head = 0;
625 sync_after_write(&hcca_oh0, 256);
629 /* TODO: handle any pending URB/ED unlinks... */
631 #define HC_IS_RUNNING() 1 /* dirty, i know... just a temporary solution */
632 if (HC_IS_RUNNING()) {
633 write32(reg+OHCI_HC_INT_STATUS, flags);
634 write32(reg+OHCI_HC_INT_ENABLE, OHCI_INTR_MIE);
638 /* Before you access the HCCA structure in any way, call this to set the pointer correctly! */
639 static void set_target_hcca(u32 reg)
642 case OHCI0_REG_BASE: hcca = &hcca_oh0; break;
643 case OHCI1_REG_BASE: hcca = &hcca_oh1; break;
647 void show_frame_no(u32 reg)
649 set_target_hcca(reg);
650 sync_before_read(hcca, 256);
651 printf("***** frame_no: %d *****\n", LE(hcca->frame_no));