usb/host/ohci.c

   1 /*
   2        ppcskel - a Free Software replacement for the Nintendo/BroadOn bootloader.
   3        ohci hardware support
   4
   5 Copyright (C) 2009     Bernhard Urban <lewurm@gmx.net>
   6 Copyright (C) 2009     Sebastian Falbesoner <sebastian.falbesoner@gmail.com>
   7
   8 # This code is licensed to you under the terms of the GNU GPL, version 2;
   9 # see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
  10 */
  11
  12 #include "../../bootmii_ppc.h"
  13 #include "../../hollywood.h"
  14 #include "../../irq.h"
  15 #include "../../string.h"
  16 #include "../../malloc.h"
  17 #include "ohci.h"
  18 #include "host.h"
  19 #include "../usbspec/usb11spec.h"
  20
  21 static struct ohci_hcca hcca_oh0;
  22
  23 static struct endpoint_descriptor *allocate_endpoint()
  24 {
  25         struct endpoint_descriptor *ep;
  26         ep = (struct endpoint_descriptor *)calloc(sizeof(struct endpoint_descriptor), 16);
  27         ep->flags = OHCI_ENDPOINT_GENERAL_FORMAT;
  28         ep->headp = ep->tailp = ep->nexted = 0;
  29         return ep;
  30 }
  31
  32 static struct general_td *allocate_general_td(size_t bsize)
  33 {
  34         struct general_td *td;
  35         td = (struct general_td *)calloc(sizeof(struct general_td), 16);
  36         td->flags = 0;
  37         td->nexttd = virt_to_phys(td);
  38         if(bsize == 0) {
  39                 td->cbp = td->be = 0;
  40         } else {
  41                 td->cbp = virt_to_phys(malloc(bsize));
  42                 td->be = td->cbp + bsize - 1;
  43         }
  44         return td;
  45 }
  46
  47 static void control_quirk()
  48 {
  49         static struct endpoint_descriptor *ed; /* empty ED */
  50         static struct general_td *td; /* dummy TD */
  51         u32 head;
  52         u32 current;
  53         u32 status;
  54
  55         /*
  56          * One time only.
  57          * Allocate and keep a special empty ED with just a dummy TD.
  58          */
  59         if (!ed) {
  60                 ed = allocate_endpoint();
  61                 if (!ed)
  62                         return;
  63
  64                 td = allocate_general_td(0);
  65                 if (!td) {
  66                         free(ed);
  67                         ed = NULL;
  68                         return;
  69                 }
  70
  71 #define ED_MASK ((u32)~0x0f)
  72                 ed->tailp = ed->headp = virt_to_phys((void*) ((u32)td & ED_MASK));
  73                 ed->flags |= OHCI_ENDPOINT_DIRECTION_OUT;
  74         }
  75
  76         /*
  77          * The OHCI USB host controllers on the Nintendo Wii
  78          * video game console stop working when new TDs are
  79          * added to a scheduled control ED after a transfer has
  80          * has taken place on it.
  81          *
  82          * Before scheduling any new control TD, we make the
  83          * controller happy by always loading a special control ED
  84          * with a single dummy TD and letting the controller attempt
  85          * the transfer.
  86          * The controller won't do anything with it, as the special
  87          * ED has no TDs, but it will keep the controller from failing
  88          * on the next transfer.
  89          */
  90         head = read32(OHCI0_HC_CTRL_HEAD_ED);
  91         if (head) {
  92                 printf("head: 0x%08X\n", head);
  93                 /*
  94                  * Load the special empty ED and tell the controller to
  95                  * process the control list.
  96                  */
  97                 sync_after_write(ed, 64);
  98                 sync_after_write(td, 64);
  99                 write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(ed));
 100
 101                 status = read32(OHCI0_HC_CONTROL);
 102                 set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
 103                 write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
 104
 105                 /* spin until the controller is done with the control list */
 106                 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 107                 while(!current) {
 108                         udelay(10);
 109                         current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 110                 }
 111
 112                 printf("current: 0x%08X\n", current);
 113
 114                 /* restore the old control head and control settings */
 115                 write32(OHCI0_HC_CONTROL, status);
 116                 write32(OHCI0_HC_CTRL_HEAD_ED, head);
 117         } else {
 118                 printf("nohead!\n");
 119         }
 120 }
 121
 122
 123 static void dbg_op_state()
 124 {
 125         switch (read32(OHCI0_HC_CONTROL) & OHCI_CTRL_HCFS) {
 126                 case OHCI_USB_SUSPEND:
 127                         printf("ohci-- OHCI_USB_SUSPEND\n");
 128                         break;
 129                 case OHCI_USB_RESET:
 130                         printf("ohci-- OHCI_USB_RESET\n");
 131                         break;
 132                 case OHCI_USB_OPER:
 133                         printf("ohci-- OHCI_USB_OPER\n");
 134                         break;
 135                 case OHCI_USB_RESUME:
 136                         printf("ohci-- OHCI_USB_RESUME\n");
 137                         break;
 138         }
 139 }
 140
 141
 142 /**
 143  * Enqueue a transfer descriptor.
 144  */
 145 u8 hcdi_enqueue(usb_transfer_descriptor *td) {
 146         control_quirk();
 147
 148         printf( "===========================\n"
 149                         "===========================\n"
 150                         "done head (vor sync): 0x%08X\n", hcca_oh0.done_head);
 151         sync_before_read(&hcca_oh0, 256);
 152         printf("done head (nach sync): 0x%08X\n", hcca_oh0.done_head);
 153
 154         struct general_td *tmptd = allocate_general_td(sizeof(td->actlen));
 155         (void) memcpy((void*) phys_to_virt(tmptd->cbp), td->buffer, sizeof(td->actlen)); /* throws dsi exception after some time :X */
 156
 157         tmptd->flags &= ~OHCI_TD_DIRECTION_PID_MASK;
 158         switch(td->pid) {
 159                 case USB_PID_SETUP:
 160                         printf("pid_setup\n");
 161                         tmptd->flags |= OHCI_TD_DIRECTION_PID_SETUP;
 162                         break;
 163                 case USB_PID_OUT:
 164                         printf("pid_out\n");
 165                         tmptd->flags |= OHCI_TD_DIRECTION_PID_OUT;
 166                         break;
 167                 case USB_PID_IN:
 168                         printf("pid_in\n");
 169                         tmptd->flags |= OHCI_TD_DIRECTION_PID_IN;
 170                         break;
 171         }
 172
 173         printf("tmptd hexump (before):\n");
 174         hexdump(tmptd, sizeof(struct general_td));
 175         printf("tmptd-cbp hexump (before):\n");
 176         hexdump((void*) phys_to_virt(tmptd->cbp), sizeof(td->actlen));
 177
 178         sync_after_write((void*) (tmptd->cbp), sizeof(td->actlen));
 179         sync_after_write(tmptd, sizeof(struct general_td));
 180
 181         struct endpoint_descriptor *dummyconfig = allocate_endpoint();
 182
 183         printf("tmpdt & ED_MASK: 0x%08X\n", virt_to_phys((void*) ((u32)tmptd & ED_MASK)));
 184 #define ED_MASK ((u32)~0x0f)
 185         dummyconfig->tailp = /* dummyconfig->headp = */ virt_to_phys((void*) ((u32)tmptd & ED_MASK));
 186 //      dummyconfig->flags |= OHCI_ENDPOINT_DIRECTION_OUT;
 187         sync_after_write(dummyconfig, 64);
 188         write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(dummyconfig));
 189
 190         printf("OHCI_CTRL_CLE: 0x%08X\n", read32(OHCI0_HC_CONTROL)&OHCI_CTRL_CLE);
 191         printf("OHCI_CLF: 0x%08X\n", read32(OHCI0_HC_COMMAND_STATUS)&OHCI_CLF);
 192         set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
 193         write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
 194
 195         printf("+++++++++++++++++++++++++++++\n");
 196         /* spin until the controller is done with the control list */
 197         u32 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 198         printf("current: 0x%08X\n", current);
 199         while(!current) {
 200                 udelay(10);
 201                 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 202         }
 203
 204         udelay(2000);
 205         udelay(2000);
 206         udelay(2000);
 207         current = read32(OHCI0_HC_CTRL_CURRENT_ED);
 208         printf("current: 0x%08X\n", current);
 209         printf("+++++++++++++++++++++++++++++\n");
 210         udelay(2000);
 211         udelay(2000);
 212         udelay(2000);
 213         udelay(2000);
 214         udelay(2000);
 215         udelay(2000);
 216         udelay(2000);
 217         udelay(2000);
 218
 219         sync_before_read(tmptd, sizeof(struct general_td));
 220         printf("tmptd hexump (after):\n");
 221         hexdump(tmptd, sizeof(struct general_td));
 222
 223         sync_before_read((void*) (tmptd->cbp), sizeof(td->actlen));
 224         printf("tmptd-cbp hexump (after):\n");
 225         hexdump((void*) (tmptd->cbp), sizeof(td->actlen));
 226
 227         printf("done head (vor sync): 0x%08X\n", hcca_oh0.done_head);
 228         sync_before_read(&hcca_oh0, 256);
 229         printf("done head (nach sync): 0x%08X\n", hcca_oh0.done_head);
 230
 231         free(tmptd);
 232         return 0;
 233 }
 234
 235 /**
 236  * Remove an transfer descriptor from transfer queue.
 237  */
 238 u8 hcdi_dequeue(usb_transfer_descriptor *td) {
 239         return 0;
 240 }
 241
 242 void hcdi_init()
 243 {
 244         printf("ohci-- init\n");
 245         dbg_op_state();
 246
 247         /* disable hc interrupts */
 248         set32(OHCI0_HC_INT_DISABLE, OHCI_INTR_MIE);
 249
 250         /* save fmInterval and calculate FSMPS */
 251 #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
 252 #define FI 0x2edf /* 12000 bits per frame (-1) */
 253         u32 fmint = read32(OHCI0_HC_FM_INTERVAL) & 0x3fff;
 254         if(fmint != FI)
 255                 printf("ohci-- fminterval delta: %d\n", fmint - FI);
 256         fmint |= FSMP (fmint) << 16;
 257
 258         /* enable interrupts of both usb host controllers */
 259         set32(EHCI_CTL, EHCI_CTL_OH0INTE | EHCI_CTL_OH1INTE | 0xe0000);
 260
 261         /* reset HC */
 262         write32(OHCI0_HC_COMMAND_STATUS, OHCI_HCR);
 263
 264         /* wait max. 30us */
 265         u32 ts = 30;
 266         while ((read32(OHCI0_HC_COMMAND_STATUS) & OHCI_HCR) != 0) {
 267                  if(--ts == 0) {
 268                         printf("ohci-- FAILED");
 269                         return;
 270                  }
 271                  udelay(1);
 272         }
 273
 274         /* disable interrupts; 2ms timelimit here!
 275            now we're in the SUSPEND state ... must go OPERATIONAL
 276            within 2msec else HC enters RESUME */
 277
 278         u32 cookie = irq_kill();
 279
 280         /* Tell the controller where the control and bulk lists are
 281          * The lists are empty now. */
 282         write32(OHCI0_HC_CTRL_HEAD_ED, 0);
 283         write32(OHCI0_HC_BULK_HEAD_ED, 0);
 284
 285         /* set hcca adress */
 286         sync_after_write(&hcca_oh0, 256);
 287         write32(OHCI0_HC_HCCA, virt_to_phys(&hcca_oh0));
 288
 289         /* set periodicstart */
 290 #define FIT (1<<31)
 291         u32 fmInterval = read32(OHCI0_HC_FM_INTERVAL) &0x3fff;
 292         u32 fit = read32(OHCI0_HC_FM_INTERVAL) & FIT;
 293
 294         write32(OHCI0_HC_FM_INTERVAL, fmint | (fit ^ FIT));
 295         write32(OHCI0_HC_PERIODIC_START, ((9*fmInterval)/10)&0x3fff);
 296
 297         /* testing bla */
 298         if ((read32(OHCI0_HC_FM_INTERVAL) & 0x3fff0000) == 0 || !read32(OHCI0_HC_PERIODIC_START)) {
 299                 printf("ohci-- w00t, fail!! see ohci-hcd.c:669\n");
 300         }
 301
 302         /* start HC operations */
 303         write32(OHCI0_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER);
 304
 305         /* wake on ConnectStatusChange, matching external hubs */
 306         set32(OHCI0_HC_RH_STATUS, RH_HS_DRWE);
 307
 308         /* Choose the interrupts we care about now, others later on demand */
 309         write32(OHCI0_HC_INT_STATUS, ~0);
 310         write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_INIT);
 311
 312         irq_restore(cookie);
 313
 314         dbg_op_state();
 315 }
 316
 317 void hcdi_irq()
 318 {
 319         /* read interrupt status */
 320         u32 flags = read32(OHCI0_HC_INT_STATUS);
 321
 322         /* when all bits are set to 1 some problem occured */
 323         if (flags == 0xffffffff) {
 324                 printf("ohci-- Houston, we have a serious problem! :(\n");
 325                 return;
 326         }
 327
 328         /* only care about interrupts that are enabled */
 329         flags &= read32(OHCI0_HC_INT_ENABLE);
 330
 331         /* nothing to do? */
 332         if (flags == 0)
 333                 return;
 334
 335         printf("OHCI Interrupt occured: ");
 336         /* UnrecoverableError */
 337         if (flags & OHCI_INTR_UE) {
 338                 printf("UnrecoverableError\n");
 339                 /* TODO: well, I don't know... nothing,
 340                  *       because it won't happen anyway? ;-) */
 341         }
 342
 343         /* RootHubStatusChange */
 344         if (flags & OHCI_INTR_RHSC) {
 345                 printf("RootHubStatusChange\n");
 346                 /* TODO: set some next_statechange variable... */
 347                 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD | OHCI_INTR_RHSC);
 348         }
 349         /* ResumeDetected */
 350         else if (flags & OHCI_INTR_RD) {
 351                 printf("ResumeDetected\n");
 352                 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD);
 353                 /* TODO: figure out what the linux kernel does here... */
 354         }
 355
 356         /* WritebackDoneHead */
 357         if (flags & OHCI_INTR_WDH) {
 358                 printf("WritebackDoneHead\n");
 359                 /* TODO: figure out what the linux kernel does here... */
 360         }
 361
 362         /* TODO: handle any pending URB/ED unlinks... */
 363
 364 #define HC_IS_RUNNING() 1 /* dirty, i know... just a temporary solution */
 365         if (HC_IS_RUNNING()) {
 366                 write32(OHCI0_HC_INT_STATUS, flags);
 367                 write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_MIE);
 368         }
 369 }
 370