pc-com: zeilennummer auch ausgeben

logic: 2978

diff --git a/src/TODO b/src/TODO
index b8c433110324405bdbf505939a682af9a487834e..c108b2c0b1859683c7efda36ffaaee13fa410b12 100644 (file)
--- a/src/TODO
+++ b/src/TODO
@@ -1,4 +1,7 @@
-- rs232/pc-kommunikation: RAM dumpen
+- rs232/pc-kommunikation: nicht den ganzen RAM dumpen? wie erkennt man das ende
+  wenn history noch nicht ganz vollgeschrieben ist?
+  einfach eine zeile skippen (= kein CR und newline machen) wenn das erste byte
+  in der zeile ein nullbyte ist?

 
 - fuer jede entity eine component definition machen und diese verwenden (in der
   top-level entity und in den simulationen).
 
 - fuer jede entity eine component definition machen und diese verwenden (in der
   top-level entity und in den simulationen).

diff --git a/src/display.vhd b/src/display.vhd
index 95606a205be81bccd7b5f51aac07a0b11d7d045e..ad5ac66c2a2d8d43988a32b599a50453dde14f36 100644 (file)
--- a/src/display.vhd
+++ b/src/display.vhd
@@ -224,27 +224,6 @@ begin
        -- out
        process(state_int, d_zeile_int, d_spalte_int, d_get_int, command_int,
                command_data_int, d_char)
        -- out
        process(state_int, d_zeile_int, d_spalte_int, d_get_int, command_int,
                command_data_int, d_char)

-               function zeile2char(i : std_logic_vector; stelle : natural) return hbyte is
-                       subtype zeilnum is string(1 to 2);
-                       type zeilnum_arr is array (natural range 0 to 49) of zeilnum;
-                       constant zn : zeilnum_arr := (
-                               0 => "00", 1 => "01", 2 => "02", 3 => "03", 4 => "04",
-                               5 => "05", 6 => "06", 7 => "07", 8 => "08", 9 => "09",
-                               10 => "10", 11 => "11", 12 => "12", 13 => "13", 14 => "14",
-                               15 => "15", 16 => "16", 17 => "17", 18 => "18", 19 => "19",
-                               20 => "20", 21 => "21", 22 => "22", 23 => "23", 24 => "24",
-                               25 => "25", 26 => "26", 27 => "27", 28 => "28", 29 => "29",
-                               30 => "30", 31 => "31", 32 => "32", 33 => "33", 34 => "34",
-                               35 => "35", 36 => "36", 37 => "37", 38 => "38", 39 => "39",
-                               40 => "40", 41 => "41", 42 => "42", 43 => "43", 44 => "44",
-                               45 => "45", 46 => "46", 47 => "47", 48 => "48", 49 => "49",
-                               others => "xy");
-                       variable t : signed(hzeile'length downto 0);
-               begin
-                       t := signed('0' & i);
-                       t := t / 2;
-                       return hbyte(to_unsigned(character'pos(zn(to_integer(t))(stelle)),8));
-               end;

        begin
                d_zeile_next <= d_zeile_int;
                d_spalte_next <= d_spalte_int;
        begin
                d_zeile_next <= d_zeile_int;
                d_spalte_next <= d_spalte_int;

diff --git a/src/gen_pkg.vhd b/src/gen_pkg.vhd
index dfe664c1fb05b077a27ef2e4ae84de0cf9bb117c..f8a2963d90405aea55fe3bd4271915482288685a 100644 (file)
--- a/src/gen_pkg.vhd
+++ b/src/gen_pkg.vhd
@@ -37,6 +37,7 @@ package gen_pkg is
 
        function ascii2sc (x : hbyte) return hbyte;
        function valid_char (x : hbyte) return boolean;
 
        function ascii2sc (x : hbyte) return hbyte;
        function valid_char (x : hbyte) return boolean;

+       function zeile2char(i : std_logic_vector; stelle : natural) return hbyte;

 
        -- http://www.marjorie.de/ps2/scancode-set2.htm
        constant SC_KP_0 : hbyte := x"70";
 
        -- http://www.marjorie.de/ps2/scancode-set2.htm
        constant SC_KP_0 : hbyte := x"70";


@@ -123,4 +124,26 @@ package body gen_pkg is
                end case;
                return y;
        end function;
                end case;
                return y;
        end function;

+
+       function zeile2char(i : std_logic_vector; stelle : natural) return hbyte is
+               subtype zeilnum is string(1 to 2);
+               type zeilnum_arr is array (natural range 0 to 49) of zeilnum;
+               constant zn : zeilnum_arr := (
+                       0 => "00", 1 => "01", 2 => "02", 3 => "03", 4 => "04",
+                       5 => "05", 6 => "06", 7 => "07", 8 => "08", 9 => "09",
+                       10 => "10", 11 => "11", 12 => "12", 13 => "13", 14 => "14",
+                       15 => "15", 16 => "16", 17 => "17", 18 => "18", 19 => "19",
+                       20 => "20", 21 => "21", 22 => "22", 23 => "23", 24 => "24",
+                       25 => "25", 26 => "26", 27 => "27", 28 => "28", 29 => "29",
+                       30 => "30", 31 => "31", 32 => "32", 33 => "33", 34 => "34",
+                       35 => "35", 36 => "36", 37 => "37", 38 => "38", 39 => "39",
+                       40 => "40", 41 => "41", 42 => "42", 43 => "43", 44 => "44",
+                       45 => "45", 46 => "46", 47 => "47", 48 => "48", 49 => "49",
+                       others => "xy");
+               variable t : signed(hzeile'length downto 0);
+       begin
+               t := signed('0' & i);
+               t := t / 2;
+               return hbyte(to_unsigned(character'pos(zn(to_integer(t))(stelle)),8));
+       end;

 end package body gen_pkg;
 end package body gen_pkg;

diff --git a/src/pc_communication.vhd b/src/pc_communication.vhd
index ca885dd5da144295b812c08b926f015af20323c0..410bc4fbb05aa0674f9e0eab1aa024bfa3da3b4d 100644 (file)
--- a/src/pc_communication.vhd
+++ b/src/pc_communication.vhd
@@ -37,7 +37,10 @@ architecture beh of pc_communication is
        signal tx_done_i, tx_done_i_next : std_logic;
        signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0);
 
        signal tx_done_i, tx_done_i_next : std_logic;
        signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0);
 

-       type STATE_PC is (IDLE, FETCH, FORWARD, WAIT_UART, UART_DONE, CR, CR_WAIT, NL, NL_WAIT);
+       type STATE_PC is (IDLE, FETCH, FORWARD, WAIT_UART, UART_DONE, CR, CR_WAIT,
+               NL, NL_WAIT, PRINT_NO1, PRINT_NO1_WAIT, PRINT_NO2, PRINT_NO2_WAIT,
+               PRINT_NO3, PRINT_NO3_WAIT, PRINT_NO4, PRINT_NO4_WAIT, PRINT_NO5,
+               PRINT_NO5_WAIT, PRINT_NO6, PRINT_NO0_WAIT);

        signal state, state_next : STATE_PC ;
 begin
        pc_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
        signal state, state_next : STATE_PC ;
 begin
        pc_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));


@@ -69,7 +72,8 @@ begin
        end process sync;
 
        process (state, zeile, spalte, tx_data_i, tx_done_i, pc_char, rx_new, btn_a,
        end process sync;
 
        process (state, zeile, spalte, tx_data_i, tx_done_i, pc_char, rx_new, btn_a,

-               pc_done)
+                       pc_done)
+               variable tmp : std_logic_vector(6 downto 0);

        begin
                get_next <= '0';
                new_i_next <= '0';
        begin
                get_next <= '0';
                new_i_next <= '0';


@@ -82,15 +86,76 @@ begin
                        when IDLE =>
 --                             if (rx_new = '1' and rx_data = x"0a") or btn_a = '0' then
                                if (rx_new = '1') or btn_a = '0' then
                        when IDLE =>
 --                             if (rx_new = '1' and rx_data = x"0a") or btn_a = '0' then
                                if (rx_new = '1') or btn_a = '0' then

+                                       state_next <= PRINT_NO0_WAIT;
+                               end if;
+
+                       when PRINT_NO0_WAIT =>
+                               if tx_done_i = '0' then
+                                       state_next <= PRINT_NO1;
+                               end if;
+                       when PRINT_NO1 =>
+                               tx_data_i_next <= x"28"; -- '('
+                               new_i_next <= '1';
+                               if tx_done_i = '1' then
+                                       state_next <= PRINT_NO1_WAIT;
+                               end if;
+                       when PRINT_NO1_WAIT =>
+                               if tx_done_i = '0' then
+                                       state_next <= PRINT_NO2;
+                               end if;
+                       when PRINT_NO2 =>
+                               tx_data_i_next <= zeile2char(std_logic_vector(to_unsigned(zeile,7)), 1);
+                               new_i_next <= '1';
+                               if tx_done_i = '1' then
+                                       state_next <= PRINT_NO2_WAIT;
+                               end if;
+                       when PRINT_NO2_WAIT =>
+                               if tx_done_i = '0' then
+                                       state_next <= PRINT_NO3;
+                               end if;
+                       when PRINT_NO3 =>
+                               tx_data_i_next <= zeile2char(std_logic_vector(to_unsigned(zeile,7)), 2);
+                               new_i_next <= '1';
+                               if tx_done_i = '1' then
+                                       state_next <= PRINT_NO3_WAIT;
+                               end if;
+                       when PRINT_NO3_WAIT =>
+                               if tx_done_i = '0' then
+                                       state_next <= PRINT_NO4;
+                               end if;
+                       when PRINT_NO4 =>
+                               tx_data_i_next <= x"29"; -- ')'
+                               new_i_next <= '1';
+                               if tx_done_i = '1' then
+                                       state_next <= PRINT_NO4_WAIT;
+                               end if;
+                       when PRINT_NO4_WAIT =>
+                               if tx_done_i = '0' then
+                                       state_next <= PRINT_NO5;
+                               end if;
+                       when PRINT_NO5 =>
+                               tx_data_i_next <= x"24"; -- '$'
+                               new_i_next <= '1';
+                               if tx_done_i = '1' then
+                                       state_next <= PRINT_NO5_WAIT;
+                               end if;
+                       when PRINT_NO5_WAIT =>
+                               if tx_done_i = '0' then
+                                       state_next <= PRINT_NO6;
+                               end if;
+                       when PRINT_NO6 =>
+                               tx_data_i_next <= x"20"; -- ' '
+                               new_i_next <= '1';
+                               if tx_done_i = '1' then

                                        state_next <= FETCH;
                                end if;
                                        state_next <= FETCH;
                                end if;

+

                        when FETCH =>
                                get_next <= '1';
                                if pc_done = '1' and tx_done_i = '0' then
                        when FETCH =>
                                get_next <= '1';
                                if pc_done = '1' and tx_done_i = '0' then

+                                       state_next <= FORWARD;

                                        if pc_char = x"00" then
                                                state_next <= UART_DONE;
                                        if pc_char = x"00" then
                                                state_next <= UART_DONE;

-                                       else
-                                               state_next <= FORWARD;

                                        end if;
                                end if;
                        when FORWARD =>
                                        end if;
                                end if;
                        when FORWARD =>


@@ -105,7 +170,7 @@ begin
                                if tx_done_i = '1' then
                                        state_next <= UART_DONE;
                                end if;
                                if tx_done_i = '1' then
                                        state_next <= UART_DONE;
                                end if;

-                       when UART_DONE => null;
+                       when UART_DONE =>

                                state_next <= FETCH;
                                spalte_next <= spalte + 1;
                                if spalte = HSPALTE_MAX + 1 then
                                state_next <= FETCH;
                                spalte_next <= spalte + 1;
                                if spalte = HSPALTE_MAX + 1 then


@@ -128,7 +193,14 @@ begin
                                        state_next <= CR_WAIT;
                                end if;
                        when CR_WAIT =>
                                        state_next <= CR_WAIT;
                                end if;
                        when CR_WAIT =>

-                               state_next <= FETCH;
+                               tmp := std_logic_vector(to_unsigned(zeile,7));
+                               if tmp(0) = '0' then
+                                       -- es handelt sich um eingabe
+                                       -- => print zeilennummer
+                                       state_next <= PRINT_NO0_WAIT;
+                               else
+                                       state_next <= FETCH;
+                               end if;

                                if zeile = HZEILE_MAX then
                                        state_next <= IDLE;
                                        zeile_next <= 0;
                                if zeile = HZEILE_MAX then
                                        state_next <= IDLE;
                                        zeile_next <= 0;