pll: warning fix

diff --git a/quartus/project_gen.tcl b/quartus/project_gen.tcl
index 584c7364188bb9ac6480df3e11a7535fa4e771e6..e972811d60b8caffbc7263039ef9d55c79342d3d 100644 (file)
--- a/quartus/project_gen.tcl
+++ b/quartus/project_gen.tcl
@@ -106,6 +106,8 @@ if {$make_assignments} {
 
        set_global_assignment -name FMAX_REQUIREMENT "33.33 MHz" -section_id sys_clk
        set_instance_assignment -name CLOCK_SETTINGS sys_clk -to sys_clk
+       #warning fix fuer pll
+       set_global_assignment -name ENABLE_CLOCK_LATENCY ON
 
        set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
        set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"

diff --git a/src/vpll.vhd b/src/vpll.vhd
index 9790567b93824184c9241daf41555d9104886583..044f7eab7e6a7341731b4d2e677692a235526be6 100644 (file)
--- a/src/vpll.vhd
+++ b/src/vpll.vhd
@@ -73,6 +73,7 @@ ARCHITECTURE SYN OF vpll IS
                compensate_clock                : STRING;
                inclk0_input_frequency          : NATURAL;
                intended_device_family          : STRING;
+               lpm_hint                : STRING;
                lpm_type                : STRING;
                operation_mode          : STRING;
                pll_type                : STRING;
@@ -149,6 +150,7 @@ BEGIN
                compensate_clock => "CLK0",
                inclk0_input_frequency => 30003,
                intended_device_family => "Stratix",
+               lpm_hint => "CBX_MODULE_PREFIX=vpll2",
                lpm_type => "altpll",
                operation_mode => "NORMAL",
                pll_type => "AUTO",
@@ -239,7 +241,7 @@ END SYN;
 -- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
 -- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.330"
 -- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "33.330"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
 -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
 -- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
 -- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
@@ -365,9 +367,10 @@ END SYN;
 -- Retrieval info: CONNECT: @extclkena 0 0 1 0 GND 0 0 0 0
 -- Retrieval info: CONNECT: @clkena 0 0 1 3 GND 0 0 0 0
 -- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.ppf TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.inc FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.cmp FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL vpll_inst.vhd FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll_inst.vhd TRUE
 -- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON