From 8fff20317f9be9b5305dfdc62c19ccf380176cd0 Mon Sep 17 00:00:00 2001 From: Bernhard Urban Date: Sat, 22 May 2010 00:21:29 +0200 Subject: [PATCH] pll: warning fix --- quartus/project_gen.tcl | 2 ++ src/vpll.vhd | 9 ++++++--- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/quartus/project_gen.tcl b/quartus/project_gen.tcl index 584c736..e972811 100644 --- a/quartus/project_gen.tcl +++ b/quartus/project_gen.tcl @@ -106,6 +106,8 @@ if {$make_assignments} { set_global_assignment -name FMAX_REQUIREMENT "33.33 MHz" -section_id sys_clk set_instance_assignment -name CLOCK_SETTINGS sys_clk -to sys_clk + #warning fix fuer pll + set_global_assignment -name ENABLE_CLOCK_LATENCY ON set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" diff --git a/src/vpll.vhd b/src/vpll.vhd index 9790567..044f7ea 100644 --- a/src/vpll.vhd +++ b/src/vpll.vhd @@ -73,6 +73,7 @@ ARCHITECTURE SYN OF vpll IS compensate_clock : STRING; inclk0_input_frequency : NATURAL; intended_device_family : STRING; + lpm_hint : STRING; lpm_type : STRING; operation_mode : STRING; pll_type : STRING; @@ -149,6 +150,7 @@ BEGIN compensate_clock => "CLK0", inclk0_input_frequency => 30003, intended_device_family => "Stratix", + lpm_hint => "CBX_MODULE_PREFIX=vpll2", lpm_type => "altpll", operation_mode => "NORMAL", pll_type => "AUTO", @@ -239,7 +241,7 @@ END SYN; -- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" -- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.330" -- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "33.330" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" -- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" -- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" @@ -365,9 +367,10 @@ END SYN; -- Retrieval info: CONNECT: @extclkena 0 0 1 0 GND 0 0 0 0 -- Retrieval info: CONNECT: @clkena 0 0 1 3 GND 0 0 0 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.ppf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.cmp FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL vpll_inst.vhd FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll_inst.vhd TRUE -- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON -- 2.25.1