end entity calc;
architecture top of calc is
+ constant CLK_FREQ : integer := 33000000;
+ constant BAUDRATE : integer := 115200;
-- ps/2
signal new_data : std_logic;
signal data : std_logic_vector(7 downto 0);
signal tx_data : std_logic_vector (7 downto 0);
begin
-- vga/ipcore
- textmode_vga_inst : entity work.textmode_vga(struct)
+ textmode_vga_inst : textmode_vga
generic map (
VGA_CLK_FREQ => 25000000,
BLINK_INTERVAL_MS => 500,
);
-- pll fuer vga
- vpll_inst : entity work.vpll(syn)
+ vpll_inst : vpll
port map (
inclk0 => sys_clk,
c0 => vga_clk
);
-- display
- display_inst : entity work.display(beh)
+ display_inst : display
port map (
sys_clk => sys_clk,
sys_res_n => sys_res_n_sync,
);
-- history
- history_inst : entity work.history(beh)
+ history_inst : history
port map (
sys_clk => sys_clk,
sys_res_n => sys_res_n_sync,
);
-- parser
- parser_inst : entity work.parser(beh)
+ parser_inst : parser
port map (
sys_clk => sys_clk,
sys_res_n => sys_res_n_sync,
);
-- scanner
- scanner_inst : entity work.scanner(beh)
+ scanner_inst : scanner
port map (
sys_clk => sys_clk,
sys_res_n => sys_res_n_sync,
);
-- ps/2
- ps2_inst : entity work.ps2_keyboard_controller(beh)
+ ps2_inst : ps2_keyboard_controller
generic map (
- CLK_FREQ => 33330000,
+ CLK_FREQ => CLK_FREQ,
SYNC_STAGES => 2
)
port map (
-- debouncer fuer sys_res_n
sys_res_n_debounce_inst : debounce
generic map (
- CLK_FREQ => 33330000,
+ CLK_FREQ => CLK_FREQ,
TIMEOUT => 1 ms,
RESET_VALUE => '1',
SYNC_STAGES => 2
);
-- synchronizer fuer rxd
- sync_rxd_inst : entity work.sync(beh)
+ sync_rxd_inst : sync
generic map (
SYNC_STAGES => 2,
RESET_VALUE => '1'
-- debouncer fuer btn_a
btn_a_debounce_inst : debounce
generic map (
- CLK_FREQ => 33330000,
+ CLK_FREQ => CLK_FREQ,
TIMEOUT => 1 ms,
RESET_VALUE => '1',
SYNC_STAGES => 2
);
-- rs232-rx
- rs232rx_inst : entity work.uart_rx(beh)
+ rs232rx_inst : uart_rx
generic map (
- CLK_FREQ => 33330000,
- BAUDRATE => 115200
+ CLK_FREQ => CLK_FREQ,
+ BAUDRATE => BAUDRATE
)
port map (
sys_clk => sys_clk,
);
-- rs232-tx
- rs232tx_inst : entity work.uart_tx(beh)
+ rs232tx_inst : uart_tx
generic map (
- CLK_FREQ => 33330000,
- BAUDRATE => 115200
+ CLK_FREQ => CLK_FREQ,
+ BAUDRATE => BAUDRATE
)
port map (
sys_clk => sys_clk,
tx_done => tx_done
);
- pc_com_inst : entity work.pc_communication(beh)
+ pc_com_inst : pc_communication
port map (
sys_clk => sys_clk,
sys_res_n => sys_res_n,
);
end architecture top;
-
constant SC_ENTER : hbyte := x"5a";
constant SC_BKSP : hbyte := x"66";
constant SC_SPACE : hbyte := x"29";
+
+ -- components...
+ component alu is
+ port (
+ sys_clk : in std_logic;
+ sys_res_n : in std_logic;
+ opcode : in alu_ops;
+ op1 : in csigned;
+ op2 : in csigned;
+ op3 : out csigned;
+ opM : out csigned;
+ do_calc : in std_logic;
+ calc_done : out std_logic;
+ calc_error : out std_logic
+ );
+ end component alu;
+
+ component parser is
+ port (
+ sys_clk : in std_logic;
+ sys_res_n : in std_logic;
+ -- History
+ p_rget : out std_logic;
+ p_rdone : in std_logic;
+ p_read : in hbyte;
+ p_wtake : out std_logic;
+ p_wdone : in std_logic;
+ p_write : out hbyte;
+ p_finished : out std_logic;
+ -- Scanner
+ do_it : in std_logic;
+ finished : out std_logic
+ );
+ end component parser;
+
+ component scanner is
+ port
+ (
+ sys_clk : in std_logic;
+ sys_res_n : in std_logic;
+ -- PS/2
+ new_data : in std_logic;
+ data : in std_logic_vector(7 downto 0);
+ -- History
+ s_char : out hbyte;
+ s_take : out std_logic;
+ s_done : in std_logic;
+ s_backspace : out std_logic;
+ -- Parser
+ do_it : out std_logic;
+ finished : in std_logic
+ );
+ end component scanner;
+
+ component history is
+ port (
+ sys_clk : in std_logic;
+ sys_res_n : in std_logic;
+ -- PC-komm
+ pc_get : in std_logic;
+ pc_spalte : in hspalte;
+ pc_zeile : in hzeile;
+ pc_char : out hbyte;
+ pc_done : out std_logic;
+ -- Scanner
+ s_char : in hbyte;
+ s_take : in std_logic;
+ s_done : out std_logic;
+ s_backspace : in std_logic;
+ -- Display
+ d_new_eingabe : out std_logic;
+ d_new_result : out std_logic;
+ d_new_bs : out std_logic;
+ d_zeile : in hzeile;
+ d_spalte : in hspalte;
+ d_get : in std_logic;
+ d_done : out std_logic;
+ d_char : out hbyte;
+ -- Parser
+ p_rget : in std_logic;
+ p_rdone : out std_logic;
+ p_read : out hbyte;
+ p_wtake : in std_logic;
+ p_wdone : out std_logic;
+ p_write : in hbyte;
+ p_finished : in std_logic
+ );
+ end component history;
+
+ component display is
+ port (
+ sys_clk : in std_logic;
+ sys_res_n : in std_logic;
+ -- History
+ d_new_eingabe : in std_logic;
+ d_new_result : in std_logic;
+ d_new_bs : in std_logic;
+ d_zeile : out hzeile;
+ d_spalte : out hspalte;
+ d_get : out std_logic;
+ d_done : in std_logic;
+ d_char : in hbyte;
+ -- VGA
+ command : out std_logic_vector(7 downto 0);
+ command_data : out std_logic_vector(31 downto 0);
+ free : in std_logic
+ );
+ end component display;
+
+ component pc_communication is
+ port (
+ sys_clk : in std_logic;
+ sys_res_n : in std_logic;
+
+ --button
+ btn_a : in std_logic;
+
+ --uart_tx
+ tx_data : out std_logic_vector(7 downto 0);
+ tx_new : out std_logic;
+ tx_done : in std_logic;
+
+ --uart_rx
+ rx_data : in std_logic_vector(7 downto 0);
+ rx_new : in std_logic;
+
+ -- History
+ pc_zeile : out hzeile;
+ pc_spalte : out hspalte;
+ pc_get : out std_logic;
+ pc_done : in std_logic;
+ pc_char : in hbyte
+ );
+ end component pc_communication;
+
+ component uart_rx is
+ generic (
+ CLK_FREQ : integer := 33000000;
+ BAUDRATE : integer := 115200
+ );
+ port(
+ sys_clk : in std_logic;
+ sys_res_n : in std_logic;
+ rxd : in std_logic;
+ rx_data : out std_logic_vector(7 downto 0);
+ rx_new : out std_logic
+ );
+ end component uart_rx;
+
+ component uart_tx is
+ generic (
+ CLK_FREQ : integer := 33000000;
+ BAUDRATE : integer := 115200
+ );
+ port(
+ sys_clk : in std_logic;
+ sys_res_n : in std_logic;
+ txd : out std_logic;
+ tx_data : in std_logic_vector(7 downto 0);
+ tx_new : in std_logic;
+ tx_done : out std_logic
+ );
+ end component uart_tx;
+
+ component vpll IS
+ port (
+ inclk0 : in std_logic := '0';
+ c0 : out std_logic
+ );
+ end component vpll;
+
+ component clk_vga_s3e is
+ port (
+ clk50 : in std_logic;
+ clk25 : out std_logic
+ );
+ end component clk_vga_s3e;
+
+ component sp_ram is
+ generic (
+ ADDR_WIDTH : integer range 1 to integer'high
+ );
+ port (
+ sys_clk : in std_logic;
+ address : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
+ data_out : out hbyte;
+ wr : in std_logic;
+ data_in : in hbyte
+ );
+ end component sp_ram;
end package gen_pkg;
package body gen_pkg is
projects / hwmod.git / commitdiff