From 51361c5dc1ab06332a04260f5192adcb398238e6 Mon Sep 17 00:00:00 2001 From: Bernhard Urban Date: Thu, 27 May 2010 20:43:56 +0200 Subject: [PATCH] allgemein: components fuer die module --- spec/speck.tex | 1 + src/beh_alu_tb.vhd | 5 +- src/beh_display_tb.vhd | 2 +- src/beh_history_tb.vhd | 12 +- src/beh_loopback_tb.vhd | 4 +- src/beh_parser_tb.vhd | 5 +- src/beh_pc_communication_tb.vhd | 2 +- src/beh_scanner_tb.vhd | 2 +- src/beh_uart_rx_tb.vhd | 2 +- src/beh_uart_tx_tb.vhd | 2 +- src/calc.vhd | 39 +++---- src/calc_s3e.vhd | 12 +- src/gen_pkg.vhd | 190 ++++++++++++++++++++++++++++++++ src/history.vhd | 2 +- src/parser.vhd | 5 +- 15 files changed, 238 insertions(+), 47 deletions(-) diff --git a/spec/speck.tex b/spec/speck.tex index ebcd8d2..238fc36 100644 --- a/spec/speck.tex +++ b/spec/speck.tex @@ -632,6 +632,7 @@ wirklich $\Rightarrow$ Tonne ebenfalls so breit wie \emph{p\_zeile} sein (zumindest vereinfacht das die Implementierung) \item RS232: \emph{tx\_done} hinzugefuegt. +\item PC-Kommunikation: auch die aktuelle Eingabe wird gesendet. \end{itemize} \end{document} diff --git a/src/beh_alu_tb.vhd b/src/beh_alu_tb.vhd index f6c6d5b..96cbeeb 100644 --- a/src/beh_alu_tb.vhd +++ b/src/beh_alu_tb.vhd @@ -12,9 +12,8 @@ architecture sim of beh_alu_tb is signal op1, op2, op3, opM : csigned; signal stop : boolean := false; begin - inst : entity work.alu(beh) - port map - ( + inst : alu + port map ( sys_clk => sys_clk, sys_res_n => sys_res_n, do_calc => do_calc, diff --git a/src/beh_display_tb.vhd b/src/beh_display_tb.vhd index 059d598..f1db735 100644 --- a/src/beh_display_tb.vhd +++ b/src/beh_display_tb.vhd @@ -29,7 +29,7 @@ architecture sim of beh_display_tb is signal stop : boolean := false; begin -- display - inst : entity work.display(beh) + inst : display port map ( sys_clk => sys_clk, sys_res_n => sys_res_n, diff --git a/src/beh_history_tb.vhd b/src/beh_history_tb.vhd index 87115c7..f249361 100644 --- a/src/beh_history_tb.vhd +++ b/src/beh_history_tb.vhd @@ -52,7 +52,7 @@ architecture sim of beh_history_tb is signal stop : boolean := false; begin -- history - inst : entity work.history(beh) + inst : history port map ( sys_clk => sys_clk, sys_res_n => sys_res_n, @@ -87,7 +87,7 @@ begin ); -- display - inst_disp : entity work.display(beh) + inst_disp : display port map ( sys_clk => sys_clk, sys_res_n => sys_res_n, @@ -107,7 +107,7 @@ begin ); -- parser - inst_parser : entity work.parser(beh) + inst_parser : parser port map ( sys_clk => sys_clk, sys_res_n => sys_res_n, @@ -125,7 +125,7 @@ begin ); -- scanner - inst_scan : entity work.scanner(beh) + inst_scan : scanner port map ( sys_clk => sys_clk, sys_res_n => sys_res_n, @@ -142,7 +142,7 @@ begin finished => finished ); --uart_tx - inst_uart : entity work.uart_tx(beh) + inst_uart : uart_tx port map ( sys_clk => sys_clk, sys_res_n => sys_res_n, @@ -153,7 +153,7 @@ begin ); --pc_communication - inst_pc_com : entity work.pc_communication(beh) + inst_pc_com : pc_communication port map( sys_clk => sys_clk, sys_res_n => sys_res_n, diff --git a/src/beh_loopback_tb.vhd b/src/beh_loopback_tb.vhd index 5e040f0..4bc01c8 100644 --- a/src/beh_loopback_tb.vhd +++ b/src/beh_loopback_tb.vhd @@ -17,7 +17,7 @@ architecture sim of beh_loopback_tb is signal tx_data : std_logic_vector (7 downto 0); signal stop : boolean := false; begin - inst_rx : entity work.uart_rx(beh) + inst_rx : uart_rx generic map ( CLK_FREQ => CLK_FREQ, BAUDRATE => BAUDRATE @@ -29,7 +29,7 @@ begin rx_data => rx_data, rx_new => rx_new ); - inst_tx : entity work.uart_tx(beh) + inst_tx : uart_tx generic map ( CLK_FREQ => CLK_FREQ, BAUDRATE => BAUDRATE diff --git a/src/beh_parser_tb.vhd b/src/beh_parser_tb.vhd index eb45205..6b3f9e6 100644 --- a/src/beh_parser_tb.vhd +++ b/src/beh_parser_tb.vhd @@ -18,9 +18,8 @@ architecture sim of beh_parser_tb is signal stop : boolean := false; begin - inst : entity work.parser(beh) - port map - ( + inst : parser + port map ( sys_clk => sys_clk, sys_res_n => sys_res_n, -- history diff --git a/src/beh_pc_communication_tb.vhd b/src/beh_pc_communication_tb.vhd index d9f8789..aa921e2 100644 --- a/src/beh_pc_communication_tb.vhd +++ b/src/beh_pc_communication_tb.vhd @@ -30,7 +30,7 @@ architecture sim of beh_pc_communication_tb is signal pc_char : hbyte; begin -- pc_communication - inst : entity work.pc_communication(beh) + inst : pc_communication port map ( sys_clk => sys_clk, sys_res_n => sys_res_n, diff --git a/src/beh_scanner_tb.vhd b/src/beh_scanner_tb.vhd index 795e4e8..d9b7bb4 100644 --- a/src/beh_scanner_tb.vhd +++ b/src/beh_scanner_tb.vhd @@ -21,7 +21,7 @@ architecture sim of beh_scanner_tb is signal stop : boolean := false; begin - inst : entity work.scanner(beh) + inst : scanner port map ( sys_clk => sys_clk, sys_res_n => sys_res_n, diff --git a/src/beh_uart_rx_tb.vhd b/src/beh_uart_rx_tb.vhd index f5e3c69..e6d2ad5 100644 --- a/src/beh_uart_rx_tb.vhd +++ b/src/beh_uart_rx_tb.vhd @@ -15,7 +15,7 @@ architecture sim of beh_uart_rx_tb is signal rx_data : std_logic_vector (7 downto 0); signal stop : boolean := false; begin - inst : entity work.uart_rx(beh) + inst : uart_rx generic map ( CLK_FREQ => CLK_FREQ, BAUDRATE => BAUDRATE diff --git a/src/beh_uart_tx_tb.vhd b/src/beh_uart_tx_tb.vhd index 3f75682..db4453c 100644 --- a/src/beh_uart_tx_tb.vhd +++ b/src/beh_uart_tx_tb.vhd @@ -15,7 +15,7 @@ architecture sim of beh_uart_tx_tb is signal tx_data : std_logic_vector (7 downto 0); signal stop : boolean := false; begin - inst : entity work.uart_tx(beh) + inst : uart_tx generic map ( CLK_FREQ => CLK_FREQ, BAUDRATE => BAUDRATE diff --git a/src/calc.vhd b/src/calc.vhd index b967e1f..20d2027 100644 --- a/src/calc.vhd +++ b/src/calc.vhd @@ -31,6 +31,8 @@ entity calc is end entity calc; architecture top of calc is + constant CLK_FREQ : integer := 33000000; + constant BAUDRATE : integer := 115200; -- ps/2 signal new_data : std_logic; signal data : std_logic_vector(7 downto 0); @@ -74,7 +76,7 @@ architecture top of calc is signal tx_data : std_logic_vector (7 downto 0); begin -- vga/ipcore - textmode_vga_inst : entity work.textmode_vga(struct) + textmode_vga_inst : textmode_vga generic map ( VGA_CLK_FREQ => 25000000, BLINK_INTERVAL_MS => 500, @@ -96,14 +98,14 @@ begin ); -- pll fuer vga - vpll_inst : entity work.vpll(syn) + vpll_inst : vpll port map ( inclk0 => sys_clk, c0 => vga_clk ); -- display - display_inst : entity work.display(beh) + display_inst : display port map ( sys_clk => sys_clk, sys_res_n => sys_res_n_sync, @@ -123,7 +125,7 @@ begin ); -- history - history_inst : entity work.history(beh) + history_inst : history port map ( sys_clk => sys_clk, sys_res_n => sys_res_n_sync, @@ -158,7 +160,7 @@ begin ); -- parser - parser_inst : entity work.parser(beh) + parser_inst : parser port map ( sys_clk => sys_clk, sys_res_n => sys_res_n_sync, @@ -176,7 +178,7 @@ begin ); -- scanner - scanner_inst : entity work.scanner(beh) + scanner_inst : scanner port map ( sys_clk => sys_clk, sys_res_n => sys_res_n_sync, @@ -194,9 +196,9 @@ begin ); -- ps/2 - ps2_inst : entity work.ps2_keyboard_controller(beh) + ps2_inst : ps2_keyboard_controller generic map ( - CLK_FREQ => 33330000, + CLK_FREQ => CLK_FREQ, SYNC_STAGES => 2 ) port map ( @@ -212,7 +214,7 @@ begin -- debouncer fuer sys_res_n sys_res_n_debounce_inst : debounce generic map ( - CLK_FREQ => 33330000, + CLK_FREQ => CLK_FREQ, TIMEOUT => 1 ms, RESET_VALUE => '1', SYNC_STAGES => 2 @@ -225,7 +227,7 @@ begin ); -- synchronizer fuer rxd - sync_rxd_inst : entity work.sync(beh) + sync_rxd_inst : sync generic map ( SYNC_STAGES => 2, RESET_VALUE => '1' @@ -240,7 +242,7 @@ begin -- debouncer fuer btn_a btn_a_debounce_inst : debounce generic map ( - CLK_FREQ => 33330000, + CLK_FREQ => CLK_FREQ, TIMEOUT => 1 ms, RESET_VALUE => '1', SYNC_STAGES => 2 @@ -253,10 +255,10 @@ begin ); -- rs232-rx - rs232rx_inst : entity work.uart_rx(beh) + rs232rx_inst : uart_rx generic map ( - CLK_FREQ => 33330000, - BAUDRATE => 115200 + CLK_FREQ => CLK_FREQ, + BAUDRATE => BAUDRATE ) port map ( sys_clk => sys_clk, @@ -267,10 +269,10 @@ begin ); -- rs232-tx - rs232tx_inst : entity work.uart_tx(beh) + rs232tx_inst : uart_tx generic map ( - CLK_FREQ => 33330000, - BAUDRATE => 115200 + CLK_FREQ => CLK_FREQ, + BAUDRATE => BAUDRATE ) port map ( sys_clk => sys_clk, @@ -281,7 +283,7 @@ begin tx_done => tx_done ); - pc_com_inst : entity work.pc_communication(beh) + pc_com_inst : pc_communication port map ( sys_clk => sys_clk, sys_res_n => sys_res_n, @@ -303,4 +305,3 @@ begin ); end architecture top; - diff --git a/src/calc_s3e.vhd b/src/calc_s3e.vhd index fb699ef..3c67b22 100644 --- a/src/calc_s3e.vhd +++ b/src/calc_s3e.vhd @@ -30,6 +30,8 @@ entity calc is end entity calc; architecture top of calc is + constant CLK_FREQ : integer := 50000000; + constant BAUDRATE : integer := 115200; -- reset signal sys_res_n : std_logic; -- ps/2 @@ -196,7 +198,7 @@ begin -- ps/2 ps2_inst : entity work.ps2_keyboard_controller(beh) generic map ( - CLK_FREQ => 50000000, + CLK_FREQ => CLK_FREQ, SYNC_STAGES => 2 ) port map ( @@ -225,8 +227,8 @@ begin -- rs232-rx rs232rx_inst : entity work.uart_rx(beh) generic map ( - CLK_FREQ => 50000000, - BAUDRATE => 115200 + CLK_FREQ => CLK_FREQ, + BAUDRATE => BAUDRATE ) port map ( sys_clk => CLK_50MHZ, @@ -239,8 +241,8 @@ begin -- rs232-tx rs232tx_inst : entity work.uart_tx(beh) generic map ( - CLK_FREQ => 50000000, - BAUDRATE => 115200 + CLK_FREQ => CLK_FREQ, + BAUDRATE => BAUDRATE ) port map ( sys_clk => CLK_50MHZ, diff --git a/src/gen_pkg.vhd b/src/gen_pkg.vhd index f8a2963..922911c 100644 --- a/src/gen_pkg.vhd +++ b/src/gen_pkg.vhd @@ -73,6 +73,196 @@ package gen_pkg is constant SC_ENTER : hbyte := x"5a"; constant SC_BKSP : hbyte := x"66"; constant SC_SPACE : hbyte := x"29"; + + -- components... + component alu is + port ( + sys_clk : in std_logic; + sys_res_n : in std_logic; + opcode : in alu_ops; + op1 : in csigned; + op2 : in csigned; + op3 : out csigned; + opM : out csigned; + do_calc : in std_logic; + calc_done : out std_logic; + calc_error : out std_logic + ); + end component alu; + + component parser is + port ( + sys_clk : in std_logic; + sys_res_n : in std_logic; + -- History + p_rget : out std_logic; + p_rdone : in std_logic; + p_read : in hbyte; + p_wtake : out std_logic; + p_wdone : in std_logic; + p_write : out hbyte; + p_finished : out std_logic; + -- Scanner + do_it : in std_logic; + finished : out std_logic + ); + end component parser; + + component scanner is + port + ( + sys_clk : in std_logic; + sys_res_n : in std_logic; + -- PS/2 + new_data : in std_logic; + data : in std_logic_vector(7 downto 0); + -- History + s_char : out hbyte; + s_take : out std_logic; + s_done : in std_logic; + s_backspace : out std_logic; + -- Parser + do_it : out std_logic; + finished : in std_logic + ); + end component scanner; + + component history is + port ( + sys_clk : in std_logic; + sys_res_n : in std_logic; + -- PC-komm + pc_get : in std_logic; + pc_spalte : in hspalte; + pc_zeile : in hzeile; + pc_char : out hbyte; + pc_done : out std_logic; + -- Scanner + s_char : in hbyte; + s_take : in std_logic; + s_done : out std_logic; + s_backspace : in std_logic; + -- Display + d_new_eingabe : out std_logic; + d_new_result : out std_logic; + d_new_bs : out std_logic; + d_zeile : in hzeile; + d_spalte : in hspalte; + d_get : in std_logic; + d_done : out std_logic; + d_char : out hbyte; + -- Parser + p_rget : in std_logic; + p_rdone : out std_logic; + p_read : out hbyte; + p_wtake : in std_logic; + p_wdone : out std_logic; + p_write : in hbyte; + p_finished : in std_logic + ); + end component history; + + component display is + port ( + sys_clk : in std_logic; + sys_res_n : in std_logic; + -- History + d_new_eingabe : in std_logic; + d_new_result : in std_logic; + d_new_bs : in std_logic; + d_zeile : out hzeile; + d_spalte : out hspalte; + d_get : out std_logic; + d_done : in std_logic; + d_char : in hbyte; + -- VGA + command : out std_logic_vector(7 downto 0); + command_data : out std_logic_vector(31 downto 0); + free : in std_logic + ); + end component display; + + component pc_communication is + port ( + sys_clk : in std_logic; + sys_res_n : in std_logic; + + --button + btn_a : in std_logic; + + --uart_tx + tx_data : out std_logic_vector(7 downto 0); + tx_new : out std_logic; + tx_done : in std_logic; + + --uart_rx + rx_data : in std_logic_vector(7 downto 0); + rx_new : in std_logic; + + -- History + pc_zeile : out hzeile; + pc_spalte : out hspalte; + pc_get : out std_logic; + pc_done : in std_logic; + pc_char : in hbyte + ); + end component pc_communication; + + component uart_rx is + generic ( + CLK_FREQ : integer := 33000000; + BAUDRATE : integer := 115200 + ); + port( + sys_clk : in std_logic; + sys_res_n : in std_logic; + rxd : in std_logic; + rx_data : out std_logic_vector(7 downto 0); + rx_new : out std_logic + ); + end component uart_rx; + + component uart_tx is + generic ( + CLK_FREQ : integer := 33000000; + BAUDRATE : integer := 115200 + ); + port( + sys_clk : in std_logic; + sys_res_n : in std_logic; + txd : out std_logic; + tx_data : in std_logic_vector(7 downto 0); + tx_new : in std_logic; + tx_done : out std_logic + ); + end component uart_tx; + + component vpll IS + port ( + inclk0 : in std_logic := '0'; + c0 : out std_logic + ); + end component vpll; + + component clk_vga_s3e is + port ( + clk50 : in std_logic; + clk25 : out std_logic + ); + end component clk_vga_s3e; + + component sp_ram is + generic ( + ADDR_WIDTH : integer range 1 to integer'high + ); + port ( + sys_clk : in std_logic; + address : in std_logic_vector(ADDR_WIDTH - 1 downto 0); + data_out : out hbyte; + wr : in std_logic; + data_in : in hbyte + ); + end component sp_ram; end package gen_pkg; package body gen_pkg is diff --git a/src/history.vhd b/src/history.vhd index 3858b43..0c91868 100644 --- a/src/history.vhd +++ b/src/history.vhd @@ -376,7 +376,7 @@ begin end case; end process; - sp_ram_inst : entity work.sp_ram(beh) + sp_ram_inst : sp_ram generic map ( ADDR_WIDTH => H_RAM_WIDTH ) diff --git a/src/parser.vhd b/src/parser.vhd index 95952d1..0867dea 100644 --- a/src/parser.vhd +++ b/src/parser.vhd @@ -57,9 +57,8 @@ architecture beh of parser is signal calc_done : std_logic; signal calc_error : std_logic; begin - instalu : entity work.alu(beh) - port map - ( + instalu : alu + port map ( sys_clk => sys_clk, sys_res_n => sys_res_n, do_calc => do_calc, -- 2.25.1