-- rs232/pc-kommunikation: RAM dumpen
+- rs232/pc-kommunikation: nicht den ganzen RAM dumpen? wie erkennt man das ende
+ wenn history noch nicht ganz vollgeschrieben ist?
+ einfach eine zeile skippen (= kein CR und newline machen) wenn das erste byte
+ in der zeile ein nullbyte ist?
- fuer jede entity eine component definition machen und diese verwenden (in der
top-level entity und in den simulationen).
-- out
process(state_int, d_zeile_int, d_spalte_int, d_get_int, command_int,
command_data_int, d_char)
- function zeile2char(i : std_logic_vector; stelle : natural) return hbyte is
- subtype zeilnum is string(1 to 2);
- type zeilnum_arr is array (natural range 0 to 49) of zeilnum;
- constant zn : zeilnum_arr := (
- 0 => "00", 1 => "01", 2 => "02", 3 => "03", 4 => "04",
- 5 => "05", 6 => "06", 7 => "07", 8 => "08", 9 => "09",
- 10 => "10", 11 => "11", 12 => "12", 13 => "13", 14 => "14",
- 15 => "15", 16 => "16", 17 => "17", 18 => "18", 19 => "19",
- 20 => "20", 21 => "21", 22 => "22", 23 => "23", 24 => "24",
- 25 => "25", 26 => "26", 27 => "27", 28 => "28", 29 => "29",
- 30 => "30", 31 => "31", 32 => "32", 33 => "33", 34 => "34",
- 35 => "35", 36 => "36", 37 => "37", 38 => "38", 39 => "39",
- 40 => "40", 41 => "41", 42 => "42", 43 => "43", 44 => "44",
- 45 => "45", 46 => "46", 47 => "47", 48 => "48", 49 => "49",
- others => "xy");
- variable t : signed(hzeile'length downto 0);
- begin
- t := signed('0' & i);
- t := t / 2;
- return hbyte(to_unsigned(character'pos(zn(to_integer(t))(stelle)),8));
- end;
begin
d_zeile_next <= d_zeile_int;
d_spalte_next <= d_spalte_int;
function ascii2sc (x : hbyte) return hbyte;
function valid_char (x : hbyte) return boolean;
+ function zeile2char(i : std_logic_vector; stelle : natural) return hbyte;
-- http://www.marjorie.de/ps2/scancode-set2.htm
constant SC_KP_0 : hbyte := x"70";
end case;
return y;
end function;
+
+ function zeile2char(i : std_logic_vector; stelle : natural) return hbyte is
+ subtype zeilnum is string(1 to 2);
+ type zeilnum_arr is array (natural range 0 to 49) of zeilnum;
+ constant zn : zeilnum_arr := (
+ 0 => "00", 1 => "01", 2 => "02", 3 => "03", 4 => "04",
+ 5 => "05", 6 => "06", 7 => "07", 8 => "08", 9 => "09",
+ 10 => "10", 11 => "11", 12 => "12", 13 => "13", 14 => "14",
+ 15 => "15", 16 => "16", 17 => "17", 18 => "18", 19 => "19",
+ 20 => "20", 21 => "21", 22 => "22", 23 => "23", 24 => "24",
+ 25 => "25", 26 => "26", 27 => "27", 28 => "28", 29 => "29",
+ 30 => "30", 31 => "31", 32 => "32", 33 => "33", 34 => "34",
+ 35 => "35", 36 => "36", 37 => "37", 38 => "38", 39 => "39",
+ 40 => "40", 41 => "41", 42 => "42", 43 => "43", 44 => "44",
+ 45 => "45", 46 => "46", 47 => "47", 48 => "48", 49 => "49",
+ others => "xy");
+ variable t : signed(hzeile'length downto 0);
+ begin
+ t := signed('0' & i);
+ t := t / 2;
+ return hbyte(to_unsigned(character'pos(zn(to_integer(t))(stelle)),8));
+ end;
end package body gen_pkg;
signal tx_done_i, tx_done_i_next : std_logic;
signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0);
- type STATE_PC is (IDLE, FETCH, FORWARD, WAIT_UART, UART_DONE, CR, CR_WAIT, NL, NL_WAIT);
+ type STATE_PC is (IDLE, FETCH, FORWARD, WAIT_UART, UART_DONE, CR, CR_WAIT,
+ NL, NL_WAIT, PRINT_NO1, PRINT_NO1_WAIT, PRINT_NO2, PRINT_NO2_WAIT,
+ PRINT_NO3, PRINT_NO3_WAIT, PRINT_NO4, PRINT_NO4_WAIT, PRINT_NO5,
+ PRINT_NO5_WAIT, PRINT_NO6, PRINT_NO0_WAIT);
signal state, state_next : STATE_PC ;
begin
pc_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
end process sync;
process (state, zeile, spalte, tx_data_i, tx_done_i, pc_char, rx_new, btn_a,
- pc_done)
+ pc_done)
+ variable tmp : std_logic_vector(6 downto 0);
begin
get_next <= '0';
new_i_next <= '0';
when IDLE =>
-- if (rx_new = '1' and rx_data = x"0a") or btn_a = '0' then
if (rx_new = '1') or btn_a = '0' then
+ state_next <= PRINT_NO0_WAIT;
+ end if;
+
+ when PRINT_NO0_WAIT =>
+ if tx_done_i = '0' then
+ state_next <= PRINT_NO1;
+ end if;
+ when PRINT_NO1 =>
+ tx_data_i_next <= x"28"; -- '('
+ new_i_next <= '1';
+ if tx_done_i = '1' then
+ state_next <= PRINT_NO1_WAIT;
+ end if;
+ when PRINT_NO1_WAIT =>
+ if tx_done_i = '0' then
+ state_next <= PRINT_NO2;
+ end if;
+ when PRINT_NO2 =>
+ tx_data_i_next <= zeile2char(std_logic_vector(to_unsigned(zeile,7)), 1);
+ new_i_next <= '1';
+ if tx_done_i = '1' then
+ state_next <= PRINT_NO2_WAIT;
+ end if;
+ when PRINT_NO2_WAIT =>
+ if tx_done_i = '0' then
+ state_next <= PRINT_NO3;
+ end if;
+ when PRINT_NO3 =>
+ tx_data_i_next <= zeile2char(std_logic_vector(to_unsigned(zeile,7)), 2);
+ new_i_next <= '1';
+ if tx_done_i = '1' then
+ state_next <= PRINT_NO3_WAIT;
+ end if;
+ when PRINT_NO3_WAIT =>
+ if tx_done_i = '0' then
+ state_next <= PRINT_NO4;
+ end if;
+ when PRINT_NO4 =>
+ tx_data_i_next <= x"29"; -- ')'
+ new_i_next <= '1';
+ if tx_done_i = '1' then
+ state_next <= PRINT_NO4_WAIT;
+ end if;
+ when PRINT_NO4_WAIT =>
+ if tx_done_i = '0' then
+ state_next <= PRINT_NO5;
+ end if;
+ when PRINT_NO5 =>
+ tx_data_i_next <= x"24"; -- '$'
+ new_i_next <= '1';
+ if tx_done_i = '1' then
+ state_next <= PRINT_NO5_WAIT;
+ end if;
+ when PRINT_NO5_WAIT =>
+ if tx_done_i = '0' then
+ state_next <= PRINT_NO6;
+ end if;
+ when PRINT_NO6 =>
+ tx_data_i_next <= x"20"; -- ' '
+ new_i_next <= '1';
+ if tx_done_i = '1' then
state_next <= FETCH;
end if;
+
when FETCH =>
get_next <= '1';
if pc_done = '1' and tx_done_i = '0' then
+ state_next <= FORWARD;
if pc_char = x"00" then
state_next <= UART_DONE;
- else
- state_next <= FORWARD;
end if;
end if;
when FORWARD =>
if tx_done_i = '1' then
state_next <= UART_DONE;
end if;
- when UART_DONE => null;
+ when UART_DONE =>
state_next <= FETCH;
spalte_next <= spalte + 1;
if spalte = HSPALTE_MAX + 1 then
state_next <= CR_WAIT;
end if;
when CR_WAIT =>
- state_next <= FETCH;
+ tmp := std_logic_vector(to_unsigned(zeile,7));
+ if tmp(0) = '0' then
+ -- es handelt sich um eingabe
+ -- => print zeilennummer
+ state_next <= PRINT_NO0_WAIT;
+ else
+ state_next <= FETCH;
+ end if;
if zeile = HZEILE_MAX then
state_next <= IDLE;
zeile_next <= 0;