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beautify
author
Alexander Oh
<oh.a@gmx.at>
Thu, 27 May 2010 03:28:00 +0000
(
05:28
+0200)
committer
Alexander Oh
<oh.a@gmx.at>
Thu, 27 May 2010 03:28:00 +0000
(
05:28
+0200)
src/beh_history_tb.vhd
patch
|
blob
|
history
src/beh_pc_communication_tb.vhd
patch
|
blob
|
history
src/calc.vhd
patch
|
blob
|
history
src/history.vhd
patch
|
blob
|
history
src/pc_communication.vhd
patch
|
blob
|
history
diff --git
a/src/beh_history_tb.vhd
b/src/beh_history_tb.vhd
index abce49d9826eadf770228f27b85bbf478fd8859f..2a24d04d7313a59d00791a0e07a69e1cd7ef6bf4 100644
(file)
--- a/
src/beh_history_tb.vhd
+++ b/
src/beh_history_tb.vhd
@@
-168,11
+168,11
@@
begin
rx_data => (others => '0'),
rx_new => '0',
-- History
rx_data => (others => '0'),
rx_new => '0',
-- History
-
d
_zeile => pc_zeile,
-
d
_spalte => pc_spalte,
-
d
_get => pc_get,
-
d
_done => pc_done,
-
d
_char => pc_char
+
pc
_zeile => pc_zeile,
+
pc
_spalte => pc_spalte,
+
pc
_get => pc_get,
+
pc
_done => pc_done,
+
pc
_char => pc_char
);
process
);
process
diff --git
a/src/beh_pc_communication_tb.vhd
b/src/beh_pc_communication_tb.vhd
index 03d1d62cac108c8c6663047136bc9fb56a53b20a..ae8ed744aa2ddf41cf7241f8169ff21a12f80c15 100644
(file)
--- a/
src/beh_pc_communication_tb.vhd
+++ b/
src/beh_pc_communication_tb.vhd
@@
-21,13
+21,13
@@
architecture sim of beh_pc_communication_tb is
signal tx_new : std_logic;
signal tx_done : std_logic;
signal rx_new : std_logic;
signal tx_new : std_logic;
signal tx_done : std_logic;
signal rx_new : std_logic;
- signal
d
_get : std_logic;
- signal
d
_done : std_logic;
+ signal
pc
_get : std_logic;
+ signal
pc
_done : std_logic;
signal rx_data, tx_data : std_logic_vector(7 downto 0);
signal rx_data, tx_data : std_logic_vector(7 downto 0);
- signal
d
_zeile : hzeile;
- signal
d
_spalte : hspalte;
- signal
d
_char : hbyte;
+ signal
pc
_zeile : hzeile;
+ signal
pc
_spalte : hspalte;
+ signal
pc
_char : hbyte;
begin
-- pc_communication
inst : entity work.pc_communication(beh)
begin
-- pc_communication
inst : entity work.pc_communication(beh)
@@
-48,11
+48,11
@@
begin
rx_new => rx_new,
-- History
rx_new => rx_new,
-- History
-
d_zeile => d
_zeile,
-
d_spalte => d
_spalte,
-
d_get => d
_get,
-
d_done => d
_done,
-
d_char => d
_char
+
pc_zeile => pc
_zeile,
+
pc_spalte => pc
_spalte,
+
pc_get => pc
_get,
+
pc_done => pc
_done,
+
pc_char => pc
_char
);
clk : process
);
clk : process
@@
-73,8
+73,8
@@
begin
variable l : line;
begin
--take control of the situation.
variable l : line;
begin
--take control of the situation.
-
d
_char <= (others => '0');
-
d
_done <= '0';
+
pc
_char <= (others => '0');
+
pc
_done <= '0';
wait until sys_res_n = '1';
while not endfile (f) loop
wait until sys_res_n = '1';
while not endfile (f) loop
@@
-82,14
+82,14
@@
begin
buf := l.all;
i := 1;
while i < l'length loop
buf := l.all;
i := 1;
while i < l'length loop
-
d
_done <= '0';
- wait until rising_edge(
d
_get);
-
d
_char <= (others => '0');
+
pc
_done <= '0';
+ wait until rising_edge(
pc
_get);
+
pc
_char <= (others => '0');
wait for 300 ns;
wait for 300 ns;
-
d
_char <= hbyte(std_logic_vector(to_unsigned(character'pos(buf(i)),8)));
+
pc
_char <= hbyte(std_logic_vector(to_unsigned(character'pos(buf(i)),8)));
i := i + 1;
i := i + 1;
-
d
_done <= '1';
+
pc
_done <= '1';
wait for 30 ns;
end loop;
wait for 30 ns;
end loop;
diff --git
a/src/calc.vhd
b/src/calc.vhd
index 420e2734e01b700bfa5847f51fca5d90129ffbf2..5cfefaad061be980b687ede8aa998497a3606a9a 100644
(file)
--- a/
src/calc.vhd
+++ b/
src/calc.vhd
@@
-298,11
+298,11
@@
begin
rx_data => rx_data,
rx_new => rx_new,
-- History
rx_data => rx_data,
rx_new => rx_new,
-- History
-
d
_zeile => pc_zeile,
-
d
_spalte => pc_spalte,
-
d
_get => pc_get,
-
d
_done => pc_done,
-
d
_char => pc_char
+
pc
_zeile => pc_zeile,
+
pc
_spalte => pc_spalte,
+
pc
_get => pc_get,
+
pc
_done => pc_done,
+
pc
_char => pc_char
);
end architecture top;
);
end architecture top;
diff --git
a/src/history.vhd
b/src/history.vhd
index e260583cd0ac7c48c7d280b9719305a77a343064..dd2ce8bd7fae662811dccb4ab6d7e8adbcded876 100644
(file)
--- a/
src/history.vhd
+++ b/
src/history.vhd
@@
-13,6
+13,7
@@
entity history is
pc_zeile : in hzeile;
pc_char : out hbyte;
pc_done : out std_logic;
pc_zeile : in hzeile;
pc_char : out hbyte;
pc_done : out std_logic;
+ pc_busy : out std_logic;
-- Scanner
s_char : in hbyte;
s_take : in std_logic;
-- Scanner
s_char : in hbyte;
s_take : in std_logic;
@@
-59,6
+60,7
@@
architecture beh of history is
signal p_sp_write_int, p_sp_write_next : hspalte;
signal pc_char_next ,pc_char_int : hbyte;
signal pc_done_next, pc_done_int : std_logic;
signal p_sp_write_int, p_sp_write_next : hspalte;
signal pc_char_next ,pc_char_int : hbyte;
signal pc_done_next, pc_done_int : std_logic;
+ signal pc_busy_next, pc_busy_int : std_logic;
-- ram
signal address_next, address_int : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
-- ram
signal address_next, address_int : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
@@
-75,6
+77,7
@@
begin
p_wdone <= p_wdone_int;
p_read <= p_read_int;
pc_done <= pc_done_int;
p_wdone <= p_wdone_int;
p_read <= p_read_int;
pc_done <= pc_done_int;
+ pc_busy <= pc_busy_int;
pc_char <= pc_char_int;
process(sys_clk, sys_res_n)
pc_char <= pc_char_int;
process(sys_clk, sys_res_n)
diff --git
a/src/pc_communication.vhd
b/src/pc_communication.vhd
index bb15b065194f9e32f24de8d848af9baa674229f8..b40444682580dddb605740bbba66703fa8517077 100644
(file)
--- a/
src/pc_communication.vhd
+++ b/
src/pc_communication.vhd
@@
-21,11
+21,11
@@
entity pc_communication is
rx_new : in std_logic;
-- History
rx_new : in std_logic;
-- History
-
d
_zeile : out hzeile;
-
d
_spalte : out hspalte;
-
d
_get : out std_logic;
-
d
_done : in std_logic;
-
d
_char : in hbyte
+
pc
_zeile : out hzeile;
+
pc
_spalte : out hspalte;
+
pc
_get : out std_logic;
+
pc
_done : in std_logic;
+
pc
_char : in hbyte
);
end entity pc_communication;
);
end entity pc_communication;
@@
-43,9
+43,9
@@
architecture beh of pc_communication is
begin
begin
-
d
_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
-
d
_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
-
d
_get <= get;
+
pc
_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
+
pc
_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
+
pc
_get <= get;
tx_new <= new_i;
tx_done_i_next <= tx_done;
tx_data <= tx_data_i;
tx_new <= new_i;
tx_done_i_next <= tx_done;
tx_data <= tx_data_i;
@@
-71,7
+71,7
@@
begin
end if;
end process sync;
end if;
end process sync;
- output_pc : process (state, zeile, spalte, tx_data_i, tx_done_i,
d
_char)
+ output_pc : process (state, zeile, spalte, tx_data_i, tx_done_i,
pc
_char)
begin
get_next <= '0';
new_i_next <= '0';
begin
get_next <= '0';
new_i_next <= '0';
@@
-86,7
+86,7
@@
begin
when FETCH =>
get_next <= '1';
when WAIT_HIST =>
when FETCH =>
get_next <= '1';
when WAIT_HIST =>
-
tx_data_i_next <= d
_char;
+
tx_data_i_next <= pc
_char;
when FORWARD =>
new_i_next <= '1';
when WAIT_UART =>
when FORWARD =>
new_i_next <= '1';
when WAIT_UART =>
@@
-104,7
+104,8
@@
begin
end case;
end process output_pc;
end case;
end process output_pc;
- next_state_pc : process (btn_a, d_done, rx_new, rx_data, spalte, state, tx_data_i ,tx_done_i, zeile)
+ next_state_pc : process (btn_a, pc_done, rx_new, rx_data, spalte, state,
+ tx_data_i ,tx_done_i, zeile)
begin
state_next <= state;
case state is
begin
state_next <= state;
case state is
@@
-115,7
+116,7
@@
begin
when FETCH =>
state_next <= WAIT_HIST;
when WAIT_HIST =>
when FETCH =>
state_next <= WAIT_HIST;
when WAIT_HIST =>
- if (
d
_done = '1') then
+ if (
pc
_done = '1') then
state_next <= FORWARD;
end if;
when FORWARD =>
state_next <= FORWARD;
end if;
when FORWARD =>