VHDL_DIR := ../src
PROJ_VHDL = alu.vhd \
textmode_vga/spartan3e_starterkit/textmode_vga_platform_dependent_pkg.vhd \
+ clk_vga_s3e.vhd \
calc_s3e.vhd \
- dcm_s3e.vhd \
display.vhd \
history.vhd \
math_pkg.vhd \
#NET "BTN_SOUTH" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
#NET "BTN_WEST" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ;
# ==== Clock inputs (CLK) ====
-NET "sys_clk_real" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
+NET "CLK_50MHZ" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
# Define clock period for 50 MHz oscillator (40%/60% duty-cycle)
-NET "sys_clk_real" PERIOD = 20 ns HIGH 40 %;
+NET "CLK_50MHZ" PERIOD = 20 ns HIGH 40 %;
#NET "CLK_AUX" LOC = "B8" | IOSTANDARD = LVCMOS33 ;
#NET "CLK_SMA" LOC = "A10" | IOSTANDARD = LVCMOS33 ;
# ==== Digital-to-Analog Converter (DAC) ====
#NET "XC_TRIG" LOC = "R17" | IOSTANDARD = LVCMOS33 ;
#NET "XC_GCK0" LOC = "H16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "GCLK10" LOC = "C9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-NET "sys_clk_real" TNM_NET = "sys_clk_real";
+NET "CLK_50MHZ" TNM_NET = "CLK_50MHZ";
#NET "clk_reg1" TNM_NET = "clk_reg1";
#TIMESPEC "TS_clk_reg1" = PERIOD "clk_reg1" 40 ns HIGH 50 %;
entity calc is
port (
- sys_clk_real : in std_logic;
- sys_res_n : in std_logic;
+ CLK_50MHZ : in std_logic;
+ -- sys_res_n : in std_logic;
-- btnA
-- TODO: pins
-- rs232
end entity calc;
architecture top of calc is
- -- clk
- signal sys_clk : std_logic;
-- ps/2
signal new_data : std_logic;
signal data : std_logic_vector(7 downto 0);
-- tmp: history<>scanner
signal do_it, finished : std_logic;
-
- COMPONENT dcm_s3e
- PORT(
- CLKIN_IN : IN std_logic;
- RST_IN : IN std_logic;
- CLKIN_IBUFG_OUT : OUT std_logic;
- CLK0_OUT : OUT std_logic;
- CLK0_OUT1 : OUT std_logic;
- LOCKED_OUT : OUT std_logic
- );
- END COMPONENT;
-
begin
led0 <= '0';
led1 <= '1';
SYNC_STAGES => 2
)
port map (
- sys_clk => sys_clk,
- sys_res_n => sys_res_n,
+ sys_clk => CLK_50MHZ,
+ sys_res_n => '1',
command => command,
command_data => command_data,
free => free,
vga_clk => vga_clk,
- vga_res_n => sys_res_n,
+ vga_res_n => '1',
vsync_n => vsync_n,
hsync_n => hsync_n,
r => r,
);
-- pll fuer vga
- dcm_s3e_inst : dcm_s3e PORT MAP(
- CLKIN_IN => sys_clk_real,
- RST_IN => sys_res_n,
- CLKIN_IBUFG_OUT => sys_clk,
- CLK0_OUT => vga_clk,
- CLK0_OUT1 => open,
- LOCKED_OUT => open
+ clk_vga_s3e_inst : entity work.clk_vga_s3e(beh)
+ port map (
+ clk50 => CLK_50MHZ,
+ clk25 => vga_clk
);
-- display
display_inst : entity work.display(beh)
port map (
- sys_clk => sys_clk,
- sys_res_n => sys_res_n,
+ sys_clk => CLK_50MHZ,
+ sys_res_n => '1',
-- history
d_new_eingabe => d_new_eingabe,
d_new_result => d_new_result,
-- history
history_inst : entity work.history(beh)
port map (
- sys_clk => sys_clk,
- sys_res_n => sys_res_n,
+ sys_clk => CLK_50MHZ,
+ sys_res_n => '1',
-- scanner
s_char => s_char,
s_take => s_take,
-- scanner
scanner_inst : entity work.scanner(beh)
port map (
- sys_clk => sys_clk,
- sys_res_n => sys_res_n,
+ sys_clk => CLK_50MHZ,
+ sys_res_n => '1',
-- ps/2
new_data => new_data,
data => data,
SYNC_STAGES => 2
)
port map (
- sys_clk => sys_clk,
- sys_res_n => sys_res_n,
+ sys_clk => CLK_50MHZ,
+ sys_res_n => '1',
-- scanner
new_data => new_data,
data => data,
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity clk_vga_s3e is
+ port (
+ clk50 : in std_logic;
+ clk25 : out std_logic
+ );
+end clk_vga_s3e;
+
+architecture beh of clk_vga_s3e is
+ signal clk25_int : std_logic;
+begin
+ clk25 <= clk25_int;
+ process (clk50)
+ begin
+ if clk50'event and clk50='1' then
+ clk25_int <= not clk25_int;
+ end if;
+ end process;
+end architecture beh;
+
+++ /dev/null
--- Module dcm_s3e
--- Generated by Xilinx Architecture Wizard
--- Written for synthesis tool: XST
-
-library ieee;
-use ieee.std_logic_1164.ALL;
-use ieee.numeric_std.ALL;
-library UNISIM;
-use UNISIM.Vcomponents.ALL;
-
-entity dcm_s3e is
- port ( CLKIN_IN : in std_logic;
- RST_IN : in std_logic;
- CLKIN_IBUFG_OUT : out std_logic;
- CLK0_OUT : out std_logic;
- CLK0_OUT1 : out std_logic;
- LOCKED_OUT : out std_logic);
-end dcm_s3e;
-
-architecture BEHAVIORAL of dcm_s3e is
- signal CLKFB_IN : std_logic;
- signal CLKIN_IBUFG : std_logic;
- signal CLK0_BUF : std_logic;
- signal GND_BIT : std_logic;
-begin
- GND_BIT <= '0';
- CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
- CLK0_OUT <= CLKFB_IN;
- CLKIN_IBUFG_INST : IBUFG
- port map (I=>CLKIN_IN,
- O=>CLKIN_IBUFG);
-
- CLK0_BUFG_INST : BUFG
- port map (I=>CLK0_BUF,
- O=>CLKFB_IN);
-
- CLK0_BUFG_INST1 : BUFG
- port map (I=>CLK0_BUF,
- O=>CLK0_OUT1);
-
- DCM_SP_INST : DCM_SP
- generic map( CLK_FEEDBACK => "1X",
- CLKDV_DIVIDE => 2.0,
- CLKFX_DIVIDE => 1,
- CLKFX_MULTIPLY => 4,
- CLKIN_DIVIDE_BY_2 => FALSE,
- CLKIN_PERIOD => 20.000,
- CLKOUT_PHASE_SHIFT => "NONE",
- DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
- DFS_FREQUENCY_MODE => "LOW",
- DLL_FREQUENCY_MODE => "LOW",
- DUTY_CYCLE_CORRECTION => TRUE,
- FACTORY_JF => x"C080",
- PHASE_SHIFT => 0,
- STARTUP_WAIT => FALSE)
- port map (CLKFB=>CLKFB_IN,
- CLKIN=>CLKIN_IBUFG,
- DSSEN=>GND_BIT,
- PSCLK=>GND_BIT,
- PSEN=>GND_BIT,
- PSINCDEC=>GND_BIT,
- RST=>RST_IN,
- CLKDV=>open,
- CLKFX=>open,
- CLKFX180=>open,
- CLK0=>CLK0_BUF,
- CLK2X=>open,
- CLK2X180=>open,
- CLK90=>open,
- CLK180=>open,
- CLK270=>open,
- LOCKED=>LOCKED_OUT,
- PSDONE=>open,
- STATUS=>open);
-
-end BEHAVIORAL;
-
projects / hwmod.git / commitdiff