spartan3e: init

... tut sich leider noch nix am board

diff --git a/spartan3e/.gitignore b/spartan3e/.gitignore
new file mode 100644 (file)
index 0000000..9118e9d
--- /dev/null
+++ b/spartan3e/.gitignore
@@ -0,0 +1,29 @@
+calc.ngc_xst.xrpt
+calc.prj
+calc.srp
+xst/
+calc.bld
+calc.ngc
+calc_ngdbuild.xrpt
+calc.mrp
+calc.ncd
+calc.ngd
+calc.ngm
+calc.pad
+calc.par
+calc.pcf
+calc.ptwx
+calc.twr
+calc.twx
+calc.unroutes
+calc.xpi
+calc_map.xrpt
+calc_pad.csv
+calc_pad.txt
+calc_par.xrpt
+calc_summary.xml
+calc_usage.xml
+generated/
+smartpreview.twr
+xlnx_auto_0_xdb/
+*.log

diff --git a/spartan3e/ISE_scripts/calc.scrs b/spartan3e/ISE_scripts/calc.scrs
new file mode 100644 (file)
index 0000000..3931bcb
--- /dev/null
+++ b/spartan3e/ISE_scripts/calc.scrs
@@ -0,0 +1,7 @@
+run
+-ifn calc.prj
+-ifmt VHDL
+-ofn calc.ngc
+-ofmt NGC -p XC3S500E-FG320-4
+-opt_mode Area
+-opt_level 2

diff --git a/spartan3e/ISE_scripts/loadprom.cmds b/spartan3e/ISE_scripts/loadprom.cmds
new file mode 100644 (file)
index 0000000..a8d4495
--- /dev/null
+++ b/spartan3e/ISE_scripts/loadprom.cmds
@@ -0,0 +1,6 @@
+setMode -bscan
+setCable -p auto
+identify
+assignFile -p 2 -file generated/calc.mcs
+program -e -p 2 -v
+quit

diff --git a/spartan3e/ISE_scripts/makeprom.cmds b/spartan3e/ISE_scripts/makeprom.cmds
new file mode 100644 (file)
index 0000000..bb08e26
--- /dev/null
+++ b/spartan3e/ISE_scripts/makeprom.cmds
@@ -0,0 +1,8 @@
+setMode -pff
+setSubmode -pffserial
+addPromDevice -p 1 -name xcf04s
+addDesign -version 0 -name 0
+addDeviceChain -index 0
+addDevice -p 1 -file generated/calc.bit
+generate -format mcs -fillvalue FF -output generated/calc.mcs
+quit

diff --git a/spartan3e/Makefile b/spartan3e/Makefile
new file mode 100644 (file)
index 0000000..9a8725c
--- /dev/null
+++ b/spartan3e/Makefile
@@ -0,0 +1,97 @@
+SHELL := bash
+
+VHDL_DIR := ../src
+PROJ_VHDL = alu.vhd \
+       textmode_vga/spartan3e_starterkit/textmode_vga_platform_dependent_pkg.vhd \
+       calc_s3e.vhd \
+       dcm_s3e.vhd \
+       display.vhd \
+       history.vhd \
+       math_pkg.vhd \
+       gen_pkg.vhd \
+       parser.vhd \
+       scanner.vhd \
+       sp_ram.vhd \
+       textmode_vga/console_sm.vhd \
+       textmode_vga/console_sm_beh.vhd \
+       textmode_vga/console_sm_sync.vhd \
+       textmode_vga/console_sm_sync_beh.vhd \
+       textmode_vga/font_pkg.vhd \
+       textmode_vga/font_rom.vhd \
+       textmode_vga/font_rom_beh.vhd \
+       textmode_vga/interval.vhd \
+       textmode_vga/interval_beh.vhd \
+       textmode_vga/textmode_vga.vhd \
+       textmode_vga/textmode_vga_component_pkg.vhd \
+       textmode_vga/textmode_vga_h_sm.vhd \
+       textmode_vga/textmode_vga_h_sm_beh.vhd \
+       textmode_vga/textmode_vga_pkg.vhd \
+       textmode_vga/textmode_vga_struct.vhd \
+       textmode_vga/textmode_vga_v_sm.vhd \
+       textmode_vga/textmode_vga_v_sm_beh.vhd \
+       textmode_vga/video_memory.vhd \
+       textmode_vga/video_memory_beh.vhd \
+       ps2/ps2_keyboard_controller.vhd \
+       ps2/ps2_keyboard_controller_beh.vhd \
+       ps2/ps2_keyboard_controller_pkg.vhd \
+       ps2/ps2_transceiver.vhd \
+       ps2/ps2_transceiver_beh.vhd \
+       ps2/ps2_transceiver_pkg.vhd
+
+PROJ_VHDL := $(foreach n,$(PROJ_VHDL),$(VHDL_DIR)/$(n))
+
+NAME := calc
+
+
+all: generated/$(NAME).mcs
+
+generated: 
+       rm -rf generated
+       mkdir generated
+
+clean:
+       rm -rf *.o *.cf tb *.vcd $(NAME) $(SIM_TOP) *.ghw
+       rm -f *.bit *.bgn *_pad.txt *_pad.csv *.xpi *.srp *.ngc *.par
+       rm -f *.lst *.ngd *.ngm *.pcf *.mrp *.unroutes *.pad
+       rm -f *.bld *.ncd *.twr *.drc
+       rm -f *.map *.xrpt *.log *.twx *.xml *.ptwx
+       rm -rf xst $(NAME).prj
+       rm -rf generated/
+       rm -rf xlnx_auto_0_xdb
+
+#Xilinx ISE actions. Uses a wrapper script named "xilinx" to run the ISE batch commands
+
+# create an ISE project file from the list of VHDL files
+$(NAME).prj: $(PROJ_VHDL)
+       echo $(PROJ_VHDL) |tr " " "\n">$(NAME).prj
+
+bitfile: generated step0 step1 step2 step3 step4 step5
+
+step0: $(NAME).prj 
+       xst -ifn ISE_scripts/$(NAME).scrs -ofn $(NAME).srp
+step1:
+       ngdbuild -nt on -uc spartan3e.ucf $(NAME).ngc $(NAME).ngd
+step2:
+       map -pr b $(NAME).ngd -o $(NAME).ncd $(NAME).pcf
+step3:
+       par -w -ol high $(NAME).ncd $(NAME).ncd $(NAME).pcf
+step4:
+       trce -v 10 -o $(NAME).twr $(NAME).ncd $(NAME).pcf
+step5:
+       bitgen $(NAME).ncd generated/$(NAME).bit -w #-f $(NAME).ut
+
+generated/$(NAME).bit: bitfile
+
+mcs: generated/$(NAME).bit
+       impact -batch ISE_scripts/makeprom.cmds
+
+generated/$(NAME).mcs: mcs
+
+load: generated/$(NAME).mcs
+       impact -batch ISE_scripts/loadprom.cmds
+
+impact:
+       impact
+
+ise: $(NAME).prj
+       ise

diff --git a/spartan3e/spartan3e.ucf b/spartan3e/spartan3e.ucf
new file mode 100644 (file)
index 0000000..64826bb
--- /dev/null
+++ b/spartan3e/spartan3e.ucf
@@ -0,0 +1,279 @@
+#####################################################
+### SPARTAN-3E STARTER KIT BOARD CONSTRAINTS FILE
+#####################################################
+# ==== Analog-to-Digital Converter (ADC) ====
+# some connections shared with SPI Flash, DAC, ADC, and AMP
+#NET "AD_CONV" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+# ==== Programmable Gain Amplifier (AMP) ====
+# some connections shared with SPI Flash, DAC, ADC, and AMP
+#NET "AMP_CS" LOC = "N7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+#NET "AMP_DOUT" LOC = "E18" | IOSTANDARD = LVCMOS33 ;
+#NET "AMP_SHDN" LOC = "P7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+# ==== Pushbuttons (BTN) ====
+#NET "BTN_EAST" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ;
+#NET "BTN_NORTH" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ;
+#NET "BTN_SOUTH" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
+#NET "BTN_WEST" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ;
+# ==== Clock inputs (CLK) ====
+NET "sys_clk_real" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
+# Define clock period for 50 MHz oscillator (40%/60% duty-cycle)
+NET "sys_clk_real" PERIOD = 20 ns HIGH 40 %;
+#NET "CLK_AUX" LOC = "B8" | IOSTANDARD = LVCMOS33 ;
+#NET "CLK_SMA" LOC = "A10" | IOSTANDARD = LVCMOS33 ;
+# ==== Digital-to-Analog Converter (DAC) ====
+# some connections shared with SPI Flash, DAC, ADC, and AMP
+#NET "DAC_CLR" LOC = "P8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+#NET "DAC_CS" LOC = "N8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+# ==== 1-Wire Secure EEPROM (DS)
+#NET "DS_WIRE" LOC = "U4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+# ==== Ethernet PHY (E) ====
+#NET "E_COL" LOC = "U6" | IOSTANDARD = LVCMOS33 ;
+#NET "E_CRS" LOC = "U13" | IOSTANDARD = LVCMOS33 ;
+#NET "E_MDC" LOC = "P9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+#NET "E_MDIO" LOC = "U5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+#NET "E_RX_CLK" LOC = "V3" | IOSTANDARD = LVCMOS33 ;
+#NET "E_RX_DV" LOC = "V2" | IOSTANDARD = LVCMOS33 ;
+#NET "E_RXD<0>" LOC = "V8" | IOSTANDARD = LVCMOS33 ;
+#NET "E_RXD<1>" LOC = "T11" | IOSTANDARD = LVCMOS33 ;
+#NET "E_RXD<2>" LOC = "U11" | IOSTANDARD = LVCMOS33 ;
+#NET "E_RXD<3>" LOC = "V14" | IOSTANDARD = LVCMOS33 ;
+#NET "E_RXD<4>" LOC = "U14" | IOSTANDARD = LVCMOS33 ;
+#NET "E_TX_CLK" LOC = "T7" | IOSTANDARD = LVCMOS33 ;
+#NET "E_TX_EN" LOC = "P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+#NET "E_TXD<0>" LOC = "R11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+#NET "E_TXD<1>" LOC = "T15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+#NET "E_TXD<2>" LOC = "R5"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+#NET "E_TXD<3>" LOC = "T5"  | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+#NET "E_TXD<4>" LOC = "R6" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+# ==== FPGA Configuration Mode, INIT_B Pins (FPGA) ====
+#NET "FPGA_M0" LOC = "M10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+#NET "FPGA_M1" LOC = "V11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+#NET "FPGA_M2" LOC = "T10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+#NET "FPGA_INIT_B" LOC = "T3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
+#NET "FPGA_RDWR_B" LOC = "U10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
+#NET "FPGA_HSWAP" LOC = "B3" | IOSTANDARD = LVCMOS33 ;
+# ==== FX2 Connector (FX2) ====
+#NET "FX2_CLKIN" LOC = "E10" | IOSTANDARD = LVCMOS33 ;
+#NET "FX2_CLKIO" LOC = "D9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_CLKOUT" LOC = "D10" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+# These four connections are shared with the J1 6-pin accessory header
+#NET "FX2_IO<1>" LOC = "B4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<2>" LOC = "A4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<3>" LOC = "D5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<4>" LOC = "C5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+# These four connections are shared with the J2 6-pin accessory header
+#NET "FX2_IO<5>" LOC = "A6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<6>" LOC = "B6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<7>" LOC = "E7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<8>" LOC = "F7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+# These four connections are shared with the J4 6-pin accessory header
+#NET "FX2_IO<9>" LOC = "D7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<10>" LOC = "C7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<11>" LOC = "F8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<12>" LOC = "E8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+# The discrete LEDs are shared with the following 8 FX2 connections
+#NET "FX2_IO<13>" LOC = "F9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<14>" LOC = "E9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<15>" LOC = "D11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<16>" LOC = "C11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<17>" LOC = "F11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<18>" LOC = "E11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<19>" LOC = "E12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<20>" LOC = "F12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<21>" LOC = "A13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<22>" LOC = "B13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<23>" LOC = "A14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<24>" LOC = "B14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<25>" LOC = "C14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<26>" LOC = "D14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<27>" LOC = "A16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<28>" LOC = "B16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<29>" LOC = "E13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<30>" LOC = "C4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<31>" LOC = "B11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<32>" LOC = "A11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<33>" LOC = "A8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<34>" LOC = "G9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IP<35>" LOC = "D12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IP<36>" LOC = "C12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IP<37>" LOC = "A15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IP<38>" LOC = "B15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<39>" LOC = "C3" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IP<40>" LOC = "C15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+# ==== 6-pin header J1 ====
+# These are shared connections with the FX2 connector
+#NET "J1<0>" LOC = "B4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J1<1>" LOC = "A4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J1<2>" LOC = "D5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J1<3>" LOC = "C5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+# ==== 6-pin header J2 ====
+# These are shared connections with the FX2 connector
+#NET "J2<0>" LOC = "A6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J2<1>" LOC = "B6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J2<2>" LOC = "E7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J2<3>" LOC = "F7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+# ==== 6-pin header J4 ====
+# These are shared connections with the FX2 connector
+#NET "J4<0>" LOC = "D7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J4<1>" LOC = "C7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J4<2>" LOC = "F8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J4<3>" LOC = "E8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+# ==== Character LCD (LCD) ====
+#NET "LCD_E" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "LCD_RS" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "LCD_RW" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+# LCD data connections are shared with StrataFlash connections SF_D<11:8>
+#NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+# ==== Discrete LEDs (LED) ====
+# These are shared connections with the FX2 connector
+NET "LED0" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+NET "LED1" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<6>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<7>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+# ==== PS/2 Mouse/Keyboard Port (PS2) ====
+NET "PS2_CLK" LOC = "G14" | IOSTANDARD = LVCMOS33 ;
+NET "PS2_DATA" LOC = "G13" | IOSTANDARD = LVCMOS33 ;
+# ==== Rotary Pushbutton Switch (ROT) ====
+#NET "ROT_A" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP ;
+#NET "ROT_B" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP ;
+#NET "ROT_CENTER" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN ;
+# ==== RS-232 Serial Ports (RS232) ====
+#NET "RS232_DCE_RXD" LOC = "F8" | IOSTANDARD = LVTTL ;
+#NET "RS232_DCE_TXD" LOC = "E8" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
+#NET "RS232_DTE_RXD" LOC = "U8" | IOSTANDARD = LVTTL ;
+#NET "RS232_DTE_TXD" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
+# ==== DDR SDRAM (SD) ==== (I/O Bank 3, VCCO=2.5V)
+#NET "SD_A<0>" LOC = "T1" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<1>" LOC = "R3" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<2>" LOC = "R2" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<3>" LOC = "P1" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<4>" LOC = "F4" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<5>" LOC = "H4" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<6>" LOC = "H3" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<7>" LOC = "H1" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<8>" LOC = "H2" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<9>" LOC = "N4" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<10>" LOC = "T2" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<11>" LOC = "N5" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<12>" LOC = "P2" | IOSTANDARD = SSTL2_I ;
+#NET "SD_BA<0>" LOC = "K5" | IOSTANDARD = SSTL2_I ;
+#NET "SD_BA<1>" LOC = "K6" | IOSTANDARD = SSTL2_I ;
+#NET "SD_CAS" LOC = "C2" | IOSTANDARD = SSTL2_I ;
+#NET "SD_CK_N" LOC = "J4" | IOSTANDARD = SSTL2_I ;
+#NET "SD_CK_P" LOC = "J5" | IOSTANDARD = SSTL2_I ;
+#NET "SD_CKE" LOC = "K3" | IOSTANDARD = SSTL2_I ;
+#NET "SD_CS" LOC = "K4" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<0>" LOC = "L2" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<1>" LOC = "L1" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<2>" LOC = "L3" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<3>" LOC = "L4" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<4>" LOC = "M3" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<5>" LOC = "M4" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<6>" LOC = "M5" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<7>" LOC = "M6" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<8>" LOC = "E2" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<9>" LOC = "E1" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<10>" LOC = "F1" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<11>" LOC = "F2" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<12>" LOC = "G6" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<13>" LOC = "G5" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<14>" LOC = "H6" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<15>" LOC = "H5" | IOSTANDARD = SSTL2_I ;
+#NET "SD_LDM" LOC = "J2" | IOSTANDARD = SSTL2_I ;
+#NET "SD_LDQS" LOC = "L6" | IOSTANDARD = SSTL2_I ;
+#NET "SD_RAS" LOC = "C1" | IOSTANDARD = SSTL2_I ;
+#NET "SD_UDM" LOC = "J1" | IOSTANDARD = SSTL2_I ;
+#NET "SD_UDQS" LOC = "G3" | IOSTANDARD = SSTL2_I ;
+#NET "SD_WE" LOC = "D1" | IOSTANDARD = SSTL2_I ;
+# Path to allow connection to top DCM connection
+#NET "SD_CK_FB" LOC = "B9" | IOSTANDARD = LVCMOS33 ;
+# Prohibit VREF pins
+CONFIG PROHIBIT = D2;
+CONFIG PROHIBIT = G4;
+CONFIG PROHIBIT = J6;
+CONFIG PROHIBIT = L5;
+CONFIG PROHIBIT = R4;
+# ==== Intel StrataFlash Parallel NOR Flash (SF) ====
+#NET "SF_A<0>" LOC = "H17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<1>" LOC = "J13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<2>" LOC = "J12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<3>" LOC = "J14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<4>" LOC = "J15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<5>" LOC = "J16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<6>" LOC = "J17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<7>" LOC = "K14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<8>" LOC = "K15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<9>" LOC = "K12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<10>" LOC = "K13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<11>" LOC = "L15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<12>" LOC = "L16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<13>" LOC = "T18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<14>" LOC = "R18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<15>" LOC = "T17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<16>" LOC = "U18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<17>" LOC = "T16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<18>" LOC = "U15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<19>" LOC = "V15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<20>" LOC = "T12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<21>" LOC = "V13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<22>" LOC = "V12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<23>" LOC = "N11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<24>" LOC = "A11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_BYTE" LOC = "C17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<1>" LOC = "P10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<2>" LOC = "R10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<3>" LOC = "V9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<4>" LOC = "U9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<5>" LOC = "R9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<6>" LOC = "M9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<7>" LOC = "N9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<12>" LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<13>" LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<14>" LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<15>" LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_OE" LOC = "C18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_STS" LOC = "B18" | IOSTANDARD = LVCMOS33 ;
+#NET "SF_WE" LOC = "D17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+# ==== STMicro SPI serial Flash (SPI) ====
+# some connections shared with SPI Flash, DAC, ADC, and AMP
+#NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ;
+#NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+#NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+#NET "SPI_SS_B" LOC = "U3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+#NET "SPI_ALT_CS_JP11" LOC = "R12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+# ==== Slide Switches (SW) ====
+#NET "SW<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
+#NET "SW<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
+#NET "SW<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
+#NET "SW<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;
+# ==== VGA Port (VGA) ====
+NET "b<0>" LOC = "G15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "g<0>" LOC = "H15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "hsync_n" LOC = "F15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "r<0>" LOC = "H14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+NET "vsync_n" LOC = "F14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+# ==== Xilinx CPLD (XC) ====
+#NET "XC_CMD<0>" LOC = "P18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+#NET "XC_CMD<1>" LOC = "N18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+#NET "XC_CPLD_EN" LOC = "B10" | IOSTANDARD = LVTTL ;
+#NET "XC_D<0>" LOC = "G16" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+#NET "XC_D<1>" LOC = "F18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+#NET "XC_D<2>" LOC = "F17" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+#NET "XC_TRIG" LOC = "R17" | IOSTANDARD = LVCMOS33 ;
+#NET "XC_GCK0" LOC = "H16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "GCLK10" LOC = "C9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "sys_clk_real" TNM_NET = "sys_clk_real";
+#NET "clk_reg1" TNM_NET = "clk_reg1";
+#TIMESPEC "TS_clk_reg1" = PERIOD "clk_reg1" 40 ns HIGH 50 %;

diff --git a/src/calc_s3e.vhd b/src/calc_s3e.vhd
new file mode 100644 (file)
index 0000000..636128f
--- /dev/null
+++ b/src/calc_s3e.vhd
@@ -0,0 +1,179 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.gen_pkg.all;
+use work.textmode_vga_component_pkg.all;
+use work.textmode_vga_pkg.all;
+use work.textmode_vga_platform_dependent_pkg.all;
+use work.ps2_keyboard_controller_pkg.all;
+
+entity calc is
+       port (
+               sys_clk_real : in std_logic;
+               sys_res_n : in std_logic;
+               -- btnA
+               -- TODO: pins
+               -- rs232
+               -- TODO: pins
+               -- vga
+               vsync_n : out std_logic;
+               hsync_n : out std_logic;
+               r : out std_logic_vector(RED_BITS - 1 downto 0);
+               g : out std_logic_vector(GREEN_BITS - 1 downto 0);
+               b : out std_logic_vector(BLUE_BITS - 1 downto 0);
+               -- ps/2
+               ps2_clk : inout std_logic;
+               ps2_data : inout std_logic;
+               -- debug
+               led0 : out std_logic;
+               led1 : out std_logic
+       );
+end entity calc;
+
+architecture top of calc is
+       -- clk
+       signal sys_clk : std_logic;
+       -- ps/2
+       signal new_data : std_logic;
+       signal data : std_logic_vector(7 downto 0);
+       -- vga
+       signal vga_clk, free : std_logic;
+       -- vga/display
+       signal command : std_logic_vector(COMMAND_SIZE - 1 downto 0);
+       signal command_data : std_logic_vector(3 * COLOR_SIZE + CHAR_SIZE -1 downto 0);
+       -- history/display
+       signal d_new_eingabe, d_new_result : std_logic;
+       signal d_zeile : hzeile;
+       signal d_spalte : hspalte;
+       signal d_get, d_done : std_logic;
+       signal d_char : hbyte;
+       -- history/scanner
+       signal s_char : hbyte;
+       signal s_take, s_done, s_backspace : std_logic;
+
+       -- tmp: history<>scanner
+       signal do_it, finished : std_logic;
+
+       COMPONENT dcm_s3e
+       PORT(
+               CLKIN_IN : IN std_logic;
+               RST_IN : IN std_logic;
+               CLKIN_IBUFG_OUT : OUT std_logic;
+               CLK0_OUT : OUT std_logic;
+               CLK0_OUT1 : OUT std_logic;
+               LOCKED_OUT : OUT std_logic
+               );
+       END COMPONENT;
+
+begin
+       led0 <= '0';
+       led1 <= '1';
+
+       -- vga/ipcore
+       textmode_vga_inst : entity work.textmode_vga(struct)
+       generic map (
+               VGA_CLK_FREQ => 25000000,
+               BLINK_INTERVAL_MS => 500,
+               SYNC_STAGES => 2
+       )
+       port map (
+               sys_clk => sys_clk,
+               sys_res_n => sys_res_n,
+               command => command,
+               command_data => command_data,
+               free => free,
+               vga_clk => vga_clk,
+               vga_res_n => sys_res_n,
+               vsync_n => vsync_n,
+               hsync_n => hsync_n,
+               r => r,
+               g => g,
+               b => b
+       );
+
+       -- pll fuer vga
+       dcm_s3e_inst : dcm_s3e PORT MAP(
+               CLKIN_IN => sys_clk_real,
+               RST_IN => sys_res_n,
+               CLKIN_IBUFG_OUT => sys_clk,
+               CLK0_OUT => vga_clk,
+               CLK0_OUT1 => open,
+               LOCKED_OUT => open
+       );
+
+       -- display
+       display_inst : entity work.display(beh)
+       port map (
+               sys_clk => sys_clk,
+               sys_res_n => sys_res_n,
+               -- history
+               d_new_eingabe => d_new_eingabe,
+               d_new_result => d_new_result,
+               d_zeile => d_zeile,
+               d_spalte => d_spalte,
+               d_get => d_get,
+               d_done => d_done,
+               d_char => d_char,
+               -- vga
+               command => command,
+               command_data => command_data,
+               free => free
+       );
+
+       -- history
+       history_inst : entity work.history(beh)
+       port map (
+               sys_clk => sys_clk,
+               sys_res_n => sys_res_n,
+               -- scanner
+               s_char => s_char,
+               s_take => s_take,
+               s_done => s_done,
+               s_backspace => s_backspace,
+               -- display
+               d_new_eingabe => d_new_eingabe,
+               d_new_result => d_new_result,
+               d_zeile => d_zeile,
+               d_spalte => d_spalte,
+               d_get => d_get,
+               d_done => d_done,
+               d_char => d_char,
+               -- TODO: tmp only!
+               do_it => do_it,
+               finished => finished
+       );
+
+       -- scanner
+       scanner_inst : entity work.scanner(beh)
+       port map (
+               sys_clk => sys_clk,
+               sys_res_n => sys_res_n,
+               -- ps/2
+               new_data => new_data,
+               data => data,
+               -- history
+               s_char => s_char,
+               s_take => s_take,
+               s_done => s_done,
+               s_backspace => s_backspace,
+               -- TODO: parser. temporaer mit history verbunden
+               do_it => do_it,
+               finished => finished
+       );
+
+       -- ps/2
+       ps2_inst : entity work.ps2_keyboard_controller(beh)
+       generic map (
+               CLK_FREQ => 50000000,
+               SYNC_STAGES => 2
+       )
+       port map (
+               sys_clk => sys_clk,
+               sys_res_n => sys_res_n,
+               -- scanner
+               new_data => new_data,
+               data => data,
+               ps2_clk => ps2_clk,
+               ps2_data => ps2_data
+       );
+end architecture top;

diff --git a/src/dcm_s3e.vhd b/src/dcm_s3e.vhd
new file mode 100644 (file)
index 0000000..7787f9e
--- /dev/null
+++ b/src/dcm_s3e.vhd
@@ -0,0 +1,77 @@
+-- Module dcm_s3e
+-- Generated by Xilinx Architecture Wizard
+-- Written for synthesis tool: XST
+
+library ieee;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+library UNISIM;
+use UNISIM.Vcomponents.ALL;
+
+entity dcm_s3e is
+   port ( CLKIN_IN        : in    std_logic; 
+          RST_IN          : in    std_logic; 
+          CLKIN_IBUFG_OUT : out   std_logic; 
+          CLK0_OUT        : out   std_logic; 
+          CLK0_OUT1       : out   std_logic; 
+          LOCKED_OUT      : out   std_logic);
+end dcm_s3e;
+
+architecture BEHAVIORAL of dcm_s3e is
+   signal CLKFB_IN        : std_logic;
+   signal CLKIN_IBUFG     : std_logic;
+   signal CLK0_BUF        : std_logic;
+   signal GND_BIT         : std_logic;
+begin
+   GND_BIT <= '0';
+   CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
+   CLK0_OUT <= CLKFB_IN;
+   CLKIN_IBUFG_INST : IBUFG
+      port map (I=>CLKIN_IN,
+                O=>CLKIN_IBUFG);
+   
+   CLK0_BUFG_INST : BUFG
+      port map (I=>CLK0_BUF,
+                O=>CLKFB_IN);
+   
+   CLK0_BUFG_INST1 : BUFG
+      port map (I=>CLK0_BUF,
+                O=>CLK0_OUT1);
+   
+   DCM_SP_INST : DCM_SP
+   generic map( CLK_FEEDBACK => "1X",
+            CLKDV_DIVIDE => 2.0,
+            CLKFX_DIVIDE => 1,
+            CLKFX_MULTIPLY => 4,
+            CLKIN_DIVIDE_BY_2 => FALSE,
+            CLKIN_PERIOD => 20.000,
+            CLKOUT_PHASE_SHIFT => "NONE",
+            DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
+            DFS_FREQUENCY_MODE => "LOW",
+            DLL_FREQUENCY_MODE => "LOW",
+            DUTY_CYCLE_CORRECTION => TRUE,
+            FACTORY_JF => x"C080",
+            PHASE_SHIFT => 0,
+            STARTUP_WAIT => FALSE)
+      port map (CLKFB=>CLKFB_IN,
+                CLKIN=>CLKIN_IBUFG,
+                DSSEN=>GND_BIT,
+                PSCLK=>GND_BIT,
+                PSEN=>GND_BIT,
+                PSINCDEC=>GND_BIT,
+                RST=>RST_IN,
+                CLKDV=>open,
+                CLKFX=>open,
+                CLKFX180=>open,
+                CLK0=>CLK0_BUF,
+                CLK2X=>open,
+                CLK2X180=>open,
+                CLK90=>open,
+                CLK180=>open,
+                CLK270=>open,
+                LOCKED=>LOCKED_OUT,
+                PSDONE=>open,
+                STATUS=>open);
+   
+end BEHAVIORAL;
+

diff --git a/src/textmode_vga/spartan3e_starterkit/textmode_vga_platform_dependent_pkg.vhd b/src/textmode_vga/spartan3e_starterkit/textmode_vga_platform_dependent_pkg.vhd
new file mode 100644 (file)
index 0000000..4e87653
--- /dev/null
+++ b/src/textmode_vga/spartan3e_starterkit/textmode_vga_platform_dependent_pkg.vhd
@@ -0,0 +1,20 @@
+-------------------------------------------------------------------------
+--
+-- Filename: textmode_vga_platform_dependent_pkg.vhd
+-- =========
+--
+-- Short Description:
+-- ==================
+--   Platform depnded declarations used within the textmode
+--   VGA controller implementation.
+--
+-------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package textmode_vga_platform_dependent_pkg is
+  constant RED_BITS : integer := 1;
+  constant GREEN_BITS : integer := 1;
+  constant BLUE_BITS : integer := 1;  
+end package textmode_vga_platform_dependent_pkg;