src/dcm_s3e.vhd

   1 -- Module dcm_s3e
   2 -- Generated by Xilinx Architecture Wizard
   3 -- Written for synthesis tool: XST
   4
   5 library ieee;
   6 use ieee.std_logic_1164.ALL;
   7 use ieee.numeric_std.ALL;
   8 library UNISIM;
   9 use UNISIM.Vcomponents.ALL;
  10
  11 entity dcm_s3e is
  12    port ( CLKIN_IN        : in    std_logic;
  13           RST_IN          : in    std_logic;
  14           CLKIN_IBUFG_OUT : out   std_logic;
  15           CLK0_OUT        : out   std_logic;
  16           CLK0_OUT1       : out   std_logic;
  17           LOCKED_OUT      : out   std_logic);
  18 end dcm_s3e;
  19
  20 architecture BEHAVIORAL of dcm_s3e is
  21    signal CLKFB_IN        : std_logic;
  22    signal CLKIN_IBUFG     : std_logic;
  23    signal CLK0_BUF        : std_logic;
  24    signal GND_BIT         : std_logic;
  25 begin
  26    GND_BIT <= '0';
  27    CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
  28    CLK0_OUT <= CLKFB_IN;
  29    CLKIN_IBUFG_INST : IBUFG
  30       port map (I=>CLKIN_IN,
  31                 O=>CLKIN_IBUFG);
  32
  33    CLK0_BUFG_INST : BUFG
  34       port map (I=>CLK0_BUF,
  35                 O=>CLKFB_IN);
  36
  37    CLK0_BUFG_INST1 : BUFG
  38       port map (I=>CLK0_BUF,
  39                 O=>CLK0_OUT1);
  40
  41    DCM_SP_INST : DCM_SP
  42    generic map( CLK_FEEDBACK => "1X",
  43             CLKDV_DIVIDE => 2.0,
  44             CLKFX_DIVIDE => 1,
  45             CLKFX_MULTIPLY => 4,
  46             CLKIN_DIVIDE_BY_2 => FALSE,
  47             CLKIN_PERIOD => 20.000,
  48             CLKOUT_PHASE_SHIFT => "NONE",
  49             DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
  50             DFS_FREQUENCY_MODE => "LOW",
  51             DLL_FREQUENCY_MODE => "LOW",
  52             DUTY_CYCLE_CORRECTION => TRUE,
  53             FACTORY_JF => x"C080",
  54             PHASE_SHIFT => 0,
  55             STARTUP_WAIT => FALSE)
  56       port map (CLKFB=>CLKFB_IN,
  57                 CLKIN=>CLKIN_IBUFG,
  58                 DSSEN=>GND_BIT,
  59                 PSCLK=>GND_BIT,
  60                 PSEN=>GND_BIT,
  61                 PSINCDEC=>GND_BIT,
  62                 RST=>RST_IN,
  63                 CLKDV=>open,
  64                 CLKFX=>open,
  65                 CLKFX180=>open,
  66                 CLK0=>CLK0_BUF,
  67                 CLK2X=>open,
  68                 CLK2X180=>open,
  69                 CLK90=>open,
  70                 CLK180=>open,
  71                 CLK270=>open,
  72                 LOCKED=>LOCKED_OUT,
  73                 PSDONE=>open,
  74                 STATUS=>open);
  75
  76 end BEHAVIORAL;
  77