signal spalte, spalte_next : hspalte;
signal zeile , zeile_next : hzeile;
signal spalte_up, spalte_up_next : std_logic;
+ signal get, get_next : std_logic;
signal char, char_next : hbyte;
signal char_en : std_logic;
begin
+
+ d_zeile <= zeile;
+ d_spalte <= spalte;
+ d_get <= get;
+
sync: process (sys_clk, sys_res_n)
begin
if sys_res_n = '0' then
spalte_next <= "0000000";
zeile <= "0000000";
zeile_next <= "0000000";
- d_get <= '0';
+ get <= '0';
tx_new <= '0';
tx_data <= "00000000";
elsif rising_edge(sys_clk) then
spalte <= spalte_next;
zeile <= zeile_next;
state <= state_next;
+ get <= get_next;
if (char_en = '1') then
state <= state_next;
end if;
end if;
end process sync;
- process (spalte_up)
+ process (spalte_up, spalte, zeile)
variable spalte_tmp, zeile_tmp : integer;
variable spalte2_tmp, zeile2_tmp : std_logic_vector(7 downto 0);
begin
spalte_tmp := to_integer(unsigned(spalte)) + 1;
spalte2_tmp := std_logic_vector(to_unsigned(spalte_tmp,8));
spalte_next <= hspalte(spalte2_tmp(6 downto 0));
-
zeile_next <= zeile;
end if;
spalte_up <= '0';
output_pc : process (state, zeile, spalte, char)
begin
- d_get <= '0';
+ get_next <= '0';
spalte_next <= "0000000";
zeile_next <= "0000000";
case state is
when IDLE =>
null;
when FETCH =>
- d_zeile <= zeile_next;
- d_spalte <= spalte_next;
- d_get <= '1';
+ get_next <= '1';
char_en <= '1';
- -- wait for timer overflow
- -- increment counter
when FORWARD =>
char_en <= '0';
tx_data <= char;
tx_new <= '1';
when DONE =>
null;
- -- be there for a single cycle and then
end case;
end process output_pc;
spalte_up <= '1';
end if;
when DONE =>
- -- be there for a single cycle and then
state_next <= IDLE;
end case;
end process next_state_pc;