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make get a real flip flop
author
Alexander Oh
<oh.a@gmx.at>
Tue, 25 May 2010 00:56:07 +0000
(
02:56
+0200)
committer
Alexander Oh
<oh.a@gmx.at>
Tue, 25 May 2010 00:56:07 +0000
(
02:56
+0200)
src/pc_communication.vhd
patch
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diff --git
a/src/pc_communication.vhd
b/src/pc_communication.vhd
index 4c3a8b9af7ee1025a15595dc083bea5a6eb0a74b..53ca2150cf5b2dc3492504455ee9b0a2f8914ad3 100644
(file)
--- a/
src/pc_communication.vhd
+++ b/
src/pc_communication.vhd
@@
-35,6
+35,7
@@
architecture beh of pc_communication is
signal spalte, spalte_next : hspalte;
signal zeile , zeile_next : hzeile;
signal spalte_up, spalte_up_next : std_logic;
signal spalte, spalte_next : hspalte;
signal zeile , zeile_next : hzeile;
signal spalte_up, spalte_up_next : std_logic;
+ signal get, get_next : std_logic;
signal char, char_next : hbyte;
signal char_en : std_logic;
signal char, char_next : hbyte;
signal char_en : std_logic;
@@
-43,6
+44,11
@@
architecture beh of pc_communication is
begin
begin
+
+ d_zeile <= zeile;
+ d_spalte <= spalte;
+ d_get <= get;
+
sync: process (sys_clk, sys_res_n)
begin
if sys_res_n = '0' then
sync: process (sys_clk, sys_res_n)
begin
if sys_res_n = '0' then
@@
-52,7
+58,7
@@
begin
spalte_next <= "0000000";
zeile <= "0000000";
zeile_next <= "0000000";
spalte_next <= "0000000";
zeile <= "0000000";
zeile_next <= "0000000";
-
d_
get <= '0';
+ get <= '0';
tx_new <= '0';
tx_data <= "00000000";
elsif rising_edge(sys_clk) then
tx_new <= '0';
tx_data <= "00000000";
elsif rising_edge(sys_clk) then
@@
-60,13
+66,14
@@
begin
spalte <= spalte_next;
zeile <= zeile_next;
state <= state_next;
spalte <= spalte_next;
zeile <= zeile_next;
state <= state_next;
+ get <= get_next;
if (char_en = '1') then
state <= state_next;
end if;
end if;
end process sync;
if (char_en = '1') then
state <= state_next;
end if;
end if;
end process sync;
- process (spalte_up)
+ process (spalte_up
, spalte, zeile
)
variable spalte_tmp, zeile_tmp : integer;
variable spalte2_tmp, zeile2_tmp : std_logic_vector(7 downto 0);
begin
variable spalte_tmp, zeile_tmp : integer;
variable spalte2_tmp, zeile2_tmp : std_logic_vector(7 downto 0);
begin
@@
-80,7
+87,6
@@
begin
spalte_tmp := to_integer(unsigned(spalte)) + 1;
spalte2_tmp := std_logic_vector(to_unsigned(spalte_tmp,8));
spalte_next <= hspalte(spalte2_tmp(6 downto 0));
spalte_tmp := to_integer(unsigned(spalte)) + 1;
spalte2_tmp := std_logic_vector(to_unsigned(spalte_tmp,8));
spalte_next <= hspalte(spalte2_tmp(6 downto 0));
-
zeile_next <= zeile;
end if;
spalte_up <= '0';
zeile_next <= zeile;
end if;
spalte_up <= '0';
@@
-104,26
+110,21
@@
begin
output_pc : process (state, zeile, spalte, char)
begin
output_pc : process (state, zeile, spalte, char)
begin
-
d_ge
t <= '0';
+
get_nex
t <= '0';
spalte_next <= "0000000";
zeile_next <= "0000000";
case state is
when IDLE =>
null;
when FETCH =>
spalte_next <= "0000000";
zeile_next <= "0000000";
case state is
when IDLE =>
null;
when FETCH =>
- d_zeile <= zeile_next;
- d_spalte <= spalte_next;
- d_get <= '1';
+ get_next <= '1';
char_en <= '1';
char_en <= '1';
- -- wait for timer overflow
- -- increment counter
when FORWARD =>
char_en <= '0';
tx_data <= char;
tx_new <= '1';
when DONE =>
null;
when FORWARD =>
char_en <= '0';
tx_data <= char;
tx_new <= '1';
when DONE =>
null;
- -- be there for a single cycle and then
end case;
end process output_pc;
end case;
end process output_pc;
@@
-146,7
+147,6
@@
begin
spalte_up <= '1';
end if;
when DONE =>
spalte_up <= '1';
end if;
when DONE =>
- -- be there for a single cycle and then
state_next <= IDLE;
end case;
end process next_state_pc;
state_next <= IDLE;
end case;
end process next_state_pc;