beautify

[hwmod.git] / src / pc_communication.vhd

diff --git a/src/pc_communication.vhd b/src/pc_communication.vhd
index bb15b065194f9e32f24de8d848af9baa674229f8..b40444682580dddb605740bbba66703fa8517077 100644 (file)
--- a/src/pc_communication.vhd
+++ b/src/pc_communication.vhd
@@ -21,11 +21,11 @@ entity pc_communication is
                rx_new : in std_logic;
 
                -- History
-               d_zeile : out hzeile;
-               d_spalte : out hspalte;
-               d_get :  out std_logic;
-               d_done : in std_logic;
-               d_char : in hbyte
+               pc_zeile : out hzeile;
+               pc_spalte : out hspalte;
+               pc_get :  out std_logic;
+               pc_done : in std_logic;
+               pc_char : in hbyte
        );
 end entity pc_communication;
 
@@ -43,9 +43,9 @@ architecture beh of pc_communication is
 begin
 
 
-       d_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
-       d_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
-       d_get <= get;
+       pc_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
+       pc_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
+       pc_get <= get;
        tx_new <= new_i;
        tx_done_i_next <= tx_done;
        tx_data <= tx_data_i;
@@ -71,7 +71,7 @@ begin
                end if;
        end process sync;
 
-       output_pc : process (state, zeile, spalte, tx_data_i, tx_done_i, d_char)
+       output_pc : process (state, zeile, spalte, tx_data_i, tx_done_i, pc_char)
        begin
                get_next <= '0';
                new_i_next <= '0';
@@ -86,7 +86,7 @@ begin
                        when FETCH =>
                                get_next <= '1';
                        when WAIT_HIST =>
-                               tx_data_i_next <= d_char;
+                       tx_data_i_next <= pc_char;
                        when FORWARD =>
                                new_i_next <= '1';
                        when WAIT_UART =>
@@ -104,7 +104,8 @@ begin
                end case;
        end process output_pc;
 
-       next_state_pc : process (btn_a, d_done, rx_new, rx_data, spalte, state, tx_data_i ,tx_done_i, zeile)
+       next_state_pc : process (btn_a, pc_done, rx_new, rx_data, spalte, state,
+               tx_data_i ,tx_done_i, zeile)
        begin
                state_next <= state;
                case state is
@@ -115,7 +116,7 @@ begin
                        when FETCH =>
                                state_next <= WAIT_HIST;
                        when WAIT_HIST =>
-                               if (d_done = '1') then
+                               if (pc_done = '1') then
                                        state_next <= FORWARD;
                                end if;
                        when FORWARD =>