library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gen_pkg.all;

entity pc_communication is
	port (
		sys_clk : in std_logic;
		sys_res_n : in std_logic;

		--button
		btn_a : in std_logic;

		--uart_tx
		tx_data : out std_logic_vector(7 downto 0);
		tx_new : out std_logic;
		tx_done : in std_logic;

		--uart_rx
		rx_data : in std_logic_vector(7 downto 0);
		rx_new : in std_logic;

		-- History
		pc_zeile : out hzeile;
		pc_spalte : out hspalte;
		pc_get :  out std_logic;
		pc_done : in std_logic;
		pc_char : in hbyte
	);
end entity pc_communication;

architecture beh of pc_communication is
	signal spalte, spalte_next : integer range 1 to hspalte_max + 1;
	signal zeile , zeile_next : integer range 1 to hzeile_max + 1;
	signal get, get_next : std_logic;
	signal new_i, new_i_next : std_logic;
	signal tx_done_i, tx_done_i_next : std_logic;
	signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0);

	type STATE_PC is (IDLE, WAIT_HIST, FETCH, FORWARD, WAIT_UART, UART_DONE);
	signal state, state_next : STATE_PC ;

begin


	pc_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
	pc_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
	pc_get <= get;
	tx_new <= new_i;
	tx_done_i_next <= tx_done;
	tx_data <= tx_data_i;

	sync: process (sys_clk, sys_res_n)
	begin
		if sys_res_n = '0' then
			state <= IDLE;
			spalte <= 1;
			zeile <= 1;
			get <= '0';
			new_i <= '0';
			tx_data_i <= "00000000";
			tx_done_i <= '0';
		elsif rising_edge(sys_clk) then
			spalte <= spalte_next;
			zeile <= zeile_next;
			state <= state_next;
			get <= get_next;
			new_i <= new_i_next;
			tx_done_i <= tx_done_i_next;
			tx_data_i <= tx_data_i_next;
		end if;
	end process sync;

	output_pc : process (state, zeile, spalte, tx_data_i, tx_done_i, pc_char)
	begin
		get_next <= '0';
		new_i_next <= '0';

		spalte_next <= spalte;
		zeile_next <= zeile;
		tx_data_i_next <= tx_data_i;

		case state is
			when IDLE =>
				null;
			when FETCH =>
				get_next <= '1';
			when WAIT_HIST =>
			tx_data_i_next <= pc_char;
			when FORWARD =>
				new_i_next <= '1';
			when WAIT_UART =>
				null;
			when UART_DONE =>
				if tx_data_i = x"00" or spalte = hspalte_max then
					zeile_next <= zeile + 1;
					spalte_next <= 1;
					if zeile = hzeile_max then
						zeile_next <= 1;
					end if;
				else
					spalte_next <= spalte + 1;
				end if;
		end case;
	end process output_pc;

	next_state_pc : process (btn_a, pc_done, rx_new, rx_data, spalte, state,
		tx_data_i ,tx_done_i, zeile)
	begin
		state_next <= state;
		case state is
			when IDLE =>
				if (rx_new = '1' and rx_data = x"0a" ) or btn_a = '1' then
					state_next <= FETCH;
				end if;
			when FETCH =>
				state_next <= WAIT_HIST;
			when WAIT_HIST =>
				if (pc_done = '1') then
					state_next <= FORWARD;
				end if;
			when FORWARD =>
				state_next <= WAIT_UART;
			when WAIT_UART =>
				if (tx_done_i = '1') then
					state_next <= UART_DONE;
				end if;
			when UART_DONE =>
				if (tx_data_i = x"00" or spalte = hspalte_max) and
					zeile = hzeile_max then
					state_next <= IDLE;
				else
					state_next <= FETCH;
				end if;
		end case;
	end process next_state_pc;

end architecture beh;