2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 entity pc_communication is
8 sys_clk : in std_logic;
9 sys_res_n : in std_logic;
15 tx_data : out std_logic_vector(7 downto 0);
16 tx_new : out std_logic;
17 tx_done : in std_logic;
20 rx_data : in std_logic_vector(7 downto 0);
21 rx_new : in std_logic;
25 d_spalte : out hspalte;
26 d_get : out std_logic;
27 d_done : in std_logic;
30 end entity pc_communication;
32 architecture beh of pc_communication is
33 signal spalte, spalte_next : integer range 1 to hspalte_max + 1;
34 signal zeile , zeile_next : integer range 1 to hzeile_max + 1;
35 signal get, get_next : std_logic;
36 signal new_i, new_i_next : std_logic;
37 signal tx_done_i, tx_done_i_next : std_logic;
38 signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0);
40 type STATE_PC is (IDLE, WAIT_HIST, FETCH, FORWARD, WAIT_UART, UART_DONE);
41 signal state, state_next : STATE_PC ;
46 d_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
47 d_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
50 tx_done_i_next <= tx_done;
53 sync: process (sys_clk, sys_res_n)
55 if sys_res_n = '0' then
61 tx_data_i <= "00000000";
63 elsif rising_edge(sys_clk) then
64 spalte <= spalte_next;
69 tx_done_i <= tx_done_i_next;
70 tx_data_i <= tx_data_i_next;
74 output_pc : process (state, zeile, spalte, tx_data_i, tx_done_i, d_char)
79 spalte_next <= spalte;
81 tx_data_i_next <= tx_data_i;
89 tx_data_i_next <= d_char;
95 if tx_data_i = x"00" or spalte = hspalte_max then
96 zeile_next <= zeile + 1;
98 if zeile = hzeile_max then
102 spalte_next <= spalte + 1;
105 end process output_pc;
107 next_state_pc : process (btn_a, d_done, rx_new, rx_data, spalte, state, tx_data_i ,tx_done_i, zeile)
112 if (rx_new = '1' and rx_data = x"0a" ) or btn_a = '1' then
116 state_next <= WAIT_HIST;
118 if (d_done = '1') then
119 state_next <= FORWARD;
122 state_next <= WAIT_UART;
124 if (tx_done_i = '1') then
125 state_next <= UART_DONE;
128 if (tx_data_i = x"00" or spalte = hspalte_max) and
129 zeile = hzeile_max then
135 end process next_state_pc;
137 end architecture beh;