beautify

diff --git a/src/beh_history_tb.vhd b/src/beh_history_tb.vhd
index abce49d9826eadf770228f27b85bbf478fd8859f..2a24d04d7313a59d00791a0e07a69e1cd7ef6bf4 100644 (file)
--- a/src/beh_history_tb.vhd
+++ b/src/beh_history_tb.vhd
@@ -168,11 +168,11 @@ begin
                rx_data => (others => '0'),
                rx_new => '0',
                -- History
-                d_zeile  => pc_zeile,
-                d_spalte => pc_spalte,
-                d_get    => pc_get,
-                d_done   => pc_done,
-                d_char   => pc_char
+                pc_zeile  => pc_zeile,
+                pc_spalte => pc_spalte,
+                pc_get    => pc_get,
+                pc_done   => pc_done,
+                pc_char   => pc_char
        );
 
        process

diff --git a/src/beh_pc_communication_tb.vhd b/src/beh_pc_communication_tb.vhd
index 03d1d62cac108c8c6663047136bc9fb56a53b20a..ae8ed744aa2ddf41cf7241f8169ff21a12f80c15 100644 (file)
--- a/src/beh_pc_communication_tb.vhd
+++ b/src/beh_pc_communication_tb.vhd
@@ -21,13 +21,13 @@ architecture sim of beh_pc_communication_tb is
                signal tx_new : std_logic;
                signal tx_done : std_logic;
                signal rx_new : std_logic;
-               signal d_get : std_logic;
-               signal d_done : std_logic;
+               signal pc_get : std_logic;
+               signal pc_done : std_logic;
                signal rx_data, tx_data : std_logic_vector(7 downto 0);
 
-               signal d_zeile : hzeile;
-               signal d_spalte : hspalte;
-               signal d_char : hbyte;
+               signal pc_zeile : hzeile;
+               signal pc_spalte : hspalte;
+               signal pc_char : hbyte;
 begin
        -- pc_communication
        inst : entity work.pc_communication(beh)
@@ -48,11 +48,11 @@ begin
                rx_new => rx_new,
 
                -- History
-               d_zeile => d_zeile,
-               d_spalte => d_spalte,
-               d_get => d_get,
-               d_done => d_done,
-               d_char => d_char
+               pc_zeile => pc_zeile,
+               pc_spalte => pc_spalte,
+               pc_get => pc_get,
+               pc_done => pc_done,
+               pc_char => pc_char
        );
 
        clk : process
@@ -73,8 +73,8 @@ begin
                variable l : line;
        begin
                --take control of the situation.
-               d_char <= (others => '0');
-               d_done <= '0';
+               pc_char <= (others => '0');
+               pc_done <= '0';
                wait until sys_res_n = '1';
 
                while not endfile (f) loop
@@ -82,14 +82,14 @@ begin
                        buf := l.all;
                        i := 1;
                        while i < l'length loop
-                               d_done <= '0';
-                               wait until rising_edge(d_get);
-                               d_char <= (others => '0');
+                               pc_done <= '0';
+                               wait until rising_edge(pc_get);
+                               pc_char <= (others => '0');
                                wait for 300 ns;
 
-                               d_char <= hbyte(std_logic_vector(to_unsigned(character'pos(buf(i)),8)));
+                               pc_char <= hbyte(std_logic_vector(to_unsigned(character'pos(buf(i)),8)));
                                i := i + 1;
-                               d_done <= '1';
+                               pc_done <= '1';
                                wait for 30 ns;
                                
                        end loop;

diff --git a/src/calc.vhd b/src/calc.vhd
index 420e2734e01b700bfa5847f51fca5d90129ffbf2..5cfefaad061be980b687ede8aa998497a3606a9a 100644 (file)
--- a/src/calc.vhd
+++ b/src/calc.vhd
@@ -298,11 +298,11 @@ begin
                rx_data => rx_data,
                rx_new => rx_new,
                -- History
-               d_zeile => pc_zeile,
-               d_spalte => pc_spalte,
-               d_get => pc_get,
-               d_done => pc_done,
-               d_char => pc_char
+               pc_zeile => pc_zeile,
+               pc_spalte => pc_spalte,
+               pc_get => pc_get,
+               pc_done => pc_done,
+               pc_char => pc_char
        );
 
 end architecture top;

diff --git a/src/history.vhd b/src/history.vhd
index e260583cd0ac7c48c7d280b9719305a77a343064..dd2ce8bd7fae662811dccb4ab6d7e8adbcded876 100644 (file)
--- a/src/history.vhd
+++ b/src/history.vhd
@@ -13,6 +13,7 @@ entity history is
                pc_zeile : in hzeile;
                pc_char : out hbyte;
                pc_done : out std_logic;
+               pc_busy : out std_logic;
                -- Scanner
                s_char : in hbyte;
                s_take : in std_logic;
@@ -59,6 +60,7 @@ architecture beh of history is
        signal p_sp_write_int, p_sp_write_next : hspalte;
        signal pc_char_next ,pc_char_int : hbyte;
        signal pc_done_next, pc_done_int : std_logic;
+       signal pc_busy_next, pc_busy_int : std_logic;
 
        -- ram
        signal address_next, address_int : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
@@ -75,6 +77,7 @@ begin
        p_wdone <= p_wdone_int;
        p_read <= p_read_int;
        pc_done <= pc_done_int;
+       pc_busy <= pc_busy_int;
        pc_char <= pc_char_int;
 
        process(sys_clk, sys_res_n)

diff --git a/src/pc_communication.vhd b/src/pc_communication.vhd
index bb15b065194f9e32f24de8d848af9baa674229f8..b40444682580dddb605740bbba66703fa8517077 100644 (file)
--- a/src/pc_communication.vhd
+++ b/src/pc_communication.vhd
@@ -21,11 +21,11 @@ entity pc_communication is
                rx_new : in std_logic;
 
                -- History
-               d_zeile : out hzeile;
-               d_spalte : out hspalte;
-               d_get :  out std_logic;
-               d_done : in std_logic;
-               d_char : in hbyte
+               pc_zeile : out hzeile;
+               pc_spalte : out hspalte;
+               pc_get :  out std_logic;
+               pc_done : in std_logic;
+               pc_char : in hbyte
        );
 end entity pc_communication;
 
@@ -43,9 +43,9 @@ architecture beh of pc_communication is
 begin
 
 
-       d_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
-       d_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
-       d_get <= get;
+       pc_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
+       pc_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
+       pc_get <= get;
        tx_new <= new_i;
        tx_done_i_next <= tx_done;
        tx_data <= tx_data_i;
@@ -71,7 +71,7 @@ begin
                end if;
        end process sync;
 
-       output_pc : process (state, zeile, spalte, tx_data_i, tx_done_i, d_char)
+       output_pc : process (state, zeile, spalte, tx_data_i, tx_done_i, pc_char)
        begin
                get_next <= '0';
                new_i_next <= '0';
@@ -86,7 +86,7 @@ begin
                        when FETCH =>
                                get_next <= '1';
                        when WAIT_HIST =>
-                               tx_data_i_next <= d_char;
+                       tx_data_i_next <= pc_char;
                        when FORWARD =>
                                new_i_next <= '1';
                        when WAIT_UART =>
@@ -104,7 +104,8 @@ begin
                end case;
        end process output_pc;
 
-       next_state_pc : process (btn_a, d_done, rx_new, rx_data, spalte, state, tx_data_i ,tx_done_i, zeile)
+       next_state_pc : process (btn_a, pc_done, rx_new, rx_data, spalte, state,
+               tx_data_i ,tx_done_i, zeile)
        begin
                state_next <= state;
                case state is
@@ -115,7 +116,7 @@ begin
                        when FETCH =>
                                state_next <= WAIT_HIST;
                        when WAIT_HIST =>
-                               if (d_done = '1') then
+                               if (pc_done = '1') then
                                        state_next <= FORWARD;
                                end if;
                        when FORWARD =>