2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
7 entity pc_communication is
9 sys_clk : in std_logic;
10 sys_res_n : in std_logic;
16 tx_data : out std_logic_vector(7 downto 0);
17 tx_new : out std_logic;
18 tx_done : in std_logic;
21 rx_data : in std_logic_vector(7 downt 0); --not really required
22 rx_new : in std_logic_vector;
26 d_spalte : out hspalte;
27 d_get : out std_logic;
28 d_done : in std_logic;
31 end entity pc_communication;
35 architecture beh of display is
36 signal push_history, push_history_next : std_logic;
39 sync_push_history : process (sys_clk, sys_res_n)
41 if sys_res_n = '0' then
43 elsif rising_edge(sys_clk) then
44 push_history <= push_history_next;
46 end process sync_push_history;
48 push_history : process(rx_new, rx_data, btn_a)
50 if ( (rx_new = '1' and rx_data = X"41") or btn_a '1') then
51 push_history_next <= '1';
53 push_history_next <= '0';
55 end process push_history;
57 -- sync_pc : process ()
59 -- end process sync_pc;
61 -- next_state_pc : process ()
63 -- end process next_state_pc;
65 -- output_pc : process ()
67 -- end process output_pc;