initial files of pc_communication

diff --git a/src/beh_pc_communication_tb.do b/src/beh_pc_communication_tb.do
new file mode 100644 (file)
index 0000000..2f52a4c
--- /dev/null
+++ b/src/beh_pc_communication_tb.do
@@ -0,0 +1,14 @@
+#alias fuer simulation neustarten
+alias rr "restart -f"
+
+#signale hinzufuegen
+add wave inst/*
+
+#rauszoomen
+wave zoomout 500.0
+
+#simulation starten und 100ms lang laufen lassen (wird durch assert abgebrochen)
+run -all
+
+#ganz nach links scrollen
+wave seetime 0

diff --git a/src/beh_pc_communication_tb.vhd b/src/beh_pc_communication_tb.vhd
new file mode 100644 (file)
index 0000000..c862095
--- /dev/null
+++ b/src/beh_pc_communication_tb.vhd
@@ -0,0 +1,72 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.gen_pkg.all;
+use work.textmode_vga_component_pkg.all;
+use work.textmode_vga_pkg.all;
+use work.textmode_vga_platform_dependent_pkg.all;
+
+entity beh_pc_communication_tb is
+end entity beh_pc_communication_tb;
+
+architecture sim of beh_pc_communication_tb is
+begin
+       -- display
+       inst : entity work.pc_communication(beh)
+       port map (
+               sys_clk => sys_clk,
+               sys_res_n => sys_res_n,
+
+               --button=> ,
+               btn_a => btn_a,
+
+               --uart_tx=> ,
+               tx_data => tx_data,
+               tx_new => tx_new,
+               tx_done => tx_done,
+
+               --uart_rx=> ,
+               rx_data => rx_data,
+               rx_new => rx_new,
+
+               -- History=> ,
+               d_zeile => d_zeile,
+               d_spalte => d_spalte,
+               d_get => d_get,
+               d_done => d_done,
+               d_char => d_char--,
+       );
+
+       clk : process
+       begin
+               sys_clk <= '0';
+               wait for 15 ns;
+               sys_clk <= '1';
+               wait for 15 ns;
+               if stop = true then
+                       wait;
+               end if;
+       end process clk;
+
+       stub_history process (d_get)
+               file f : text open read_mode is "../../src/pc_communication.test";
+       begin
+               if rising_edge(d_get) then
+                       read(f, d_char);
+                       wait 30 ns;
+                       done <= d_done;
+               end if;
+       end process stub_history;
+
+       process
+       begin
+               -- init & reset
+               -- we only simulate pressing of button a by now!
+               sys_res_n <= 0;
+               wait for 100 ns;
+               sys_res_n <= 1;
+
+               btn_a <= 1;
+               wait;
+       end process;
+end architecture sim;

diff --git a/src/pc_communication.vhd b/src/pc_communication.vhd
new file mode 100644 (file)
index 0000000..3681c69
--- /dev/null
+++ b/src/pc_communication.vhd
@@ -0,0 +1,68 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.gen_pkg.all;
+
+
+entity pc_communication is
+       port (
+               sys_clk : in std_logic;
+               sys_res_n : in std_logic;
+
+               --button
+               btn_a : in std_logic;
+
+               --uart_tx
+               tx_data : out std_logic_vector(7 downto 0);
+               tx_new : out std_logic;
+               tx_done : in std_logic;
+
+               --uart_rx
+               rx_data : in std_logic_vector(7 downt 0); --not really required
+               rx_new : in std_logic_vector;
+
+               -- History
+               d_zeile : out hzeile;
+               d_spalte : out hspalte;
+               d_get :  out std_logic;
+               d_done : in std_logic;
+               d_char : in hbyte --;
+       );
+end entity pc_communication;
+
+
+
+architecture beh of display is
+       signal push_history, push_history_next : std_logic;
+begin
+
+       sync_push_history : process (sys_clk, sys_res_n)
+       begin
+               if sys_res_n = '0' then
+                       push_history <= '0';
+               elsif rising_edge(sys_clk) then
+                       push_history <= push_history_next;
+               end if;
+       end process sync_push_history;
+
+       push_history : process(rx_new, rx_data, btn_a)
+       begin
+               if ( (rx_new = '1' and rx_data = X"41") or btn_a '1') then
+                       push_history_next <= '1';
+               else
+                       push_history_next <= '0';
+               end if;
+       end process push_history;
+
+--     sync_pc : process ()
+--     begin
+--     end process sync_pc;
+--
+--     next_state_pc : process ()
+--     begin
+--     end process next_state_pc;
+--
+--     output_pc : process ()
+--     begin
+--     end process output_pc;
+end architecture beh;