library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gen_pkg.all;


entity pc_communication is
	port (
		sys_clk : in std_logic;
		sys_res_n : in std_logic;

		--button
		btn_a : in std_logic;

		--uart_tx
		tx_data : out std_logic_vector(7 downto 0);
		tx_new : out std_logic;
		tx_done : in std_logic;

		--uart_rx
		rx_data : in std_logic_vector(7 downt 0); --not really required
		rx_new : in std_logic_vector;

		-- History
		d_zeile : out hzeile;
		d_spalte : out hspalte;
		d_get :  out std_logic;
		d_done : in std_logic;
		d_char : in hbyte --;
	);
end entity pc_communication;



architecture beh of display is
	signal push_history, push_history_next : std_logic;
begin

	sync_push_history : process (sys_clk, sys_res_n)
	begin
		if sys_res_n = '0' then
			push_history <= '0';
		elsif rising_edge(sys_clk) then
			push_history <= push_history_next;
		end if;
	end process sync_push_history;

	push_history : process(rx_new, rx_data, btn_a)
	begin
		if ( (rx_new = '1' and rx_data = X"41") or btn_a '1') then
			push_history_next <= '1';
		else
			push_history_next <= '0';
		end if;
	end process push_history;

--	sync_pc : process ()
--	begin
--	end process sync_pc;
--
--	next_state_pc : process ()
--	begin
--	end process next_state_pc;
--
--	output_pc : process ()
--	begin
--	end process output_pc;
end architecture beh;