src/display.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use work.gen_pkg.all;
   5 use work.textmode_vga_component_pkg.all;
   6 use work.textmode_vga_pkg.all;
   7 use work.textmode_vga_platform_dependent_pkg.all;
   8
   9 entity display is
  10         port (
  11                 sys_clk : in std_logic;
  12                 sys_res_n : in std_logic;
  13                 -- History
  14                 d_new_eingabe : in std_logic;
  15                 d_new_result : in std_logic;
  16                 d_zeile : out hzeile;
  17                 d_spalte : out hspalte;
  18                 d_get : out std_logic;
  19                 d_done : in std_logic;
  20                 d_char : in hbyte;
  21                 -- VGA
  22                 command : out std_logic_vector(7 downto 0);
  23                 command_data : out std_logic_vector(31 downto 0);
  24                 free : in std_logic
  25         );
  26 end entity display;
  27
  28 architecture beh of display is
  29         type DISPLAY_STATE is (SIDLE, S_NEW_RESULT, S_NEW_INPUT);
  30         signal state_int, state_next : DISPLAY_STATE;
  31         signal d_zeile_int, d_zeile_next : hzeile;
  32         signal d_spalte_int, d_spalte_next : hspalte;
  33         signal d_get_int, d_get_next : std_logic;
  34         signal command_int, command_next : std_logic_vector(7 downto 0);
  35         signal command_data_int, command_data_next : std_logic_vector(31 downto 0);
  36 begin
  37         d_zeile <= d_zeile_int;
  38         d_spalte <= d_spalte_int;
  39         d_get <= d_get_int;
  40         command <= command_int;
  41         command_data <= command_data_int;
  42
  43         process(sys_clk, sys_res_n)
  44         begin
  45                 if sys_res_n = '0' then
  46                         -- internal
  47                         state_int <= SIDLE;
  48                         -- out
  49                         d_zeile_int <= (others => '0');
  50                         d_spalte_int <= (others => '0');
  51                         d_get_int <= '0';
  52                         command_int <= COMMAND_NOP;
  53                         command_data_int <= (others => '0');
  54                 elsif rising_edge(sys_clk) then
  55                         -- internal
  56                         state_int <= state_next;
  57                         -- out
  58                         d_zeile_int <= d_zeile_next;
  59                         d_spalte_int <= d_spalte_next;
  60                         d_get_int <= d_get_next;
  61                         command_int <= command_next;
  62                         command_data_int <= command_data_next;
  63                 end if;
  64         end process;
  65
  66         -- next state
  67         process(state_int, d_new_result, d_new_eingabe, d_done, free)
  68         begin
  69                 state_next <= state_int;
  70
  71                 case state_int is
  72                         when SIDLE =>
  73                                 if free = '1' then
  74                                         if d_new_eingabe = '1' then
  75                                                 state_next <= S_NEW_INPUT;
  76                                         end if;
  77                                         if d_new_result = '1' then
  78                                                 state_next <= S_NEW_RESULT;
  79                                         end if;
  80                                 end if;
  81                         when S_NEW_RESULT | S_NEW_INPUT =>
  82                                 if free = '0' then
  83                                         state_next <= SIDLE;
  84                                 end if;
  85                 end case;
  86         end process;
  87
  88         -- out
  89         process(state_int, d_zeile_int, d_spalte_int, d_get_int, command_int,
  90                 command_data_int)
  91         begin
  92                 d_zeile_next <= d_zeile_int;
  93                 d_spalte_next <= d_spalte_int;
  94                 d_get_next <= d_get_int;
  95                 command_next <= command_int;
  96                 command_data_next <= command_data_int;
  97
  98                 case state_int is
  99                         when SIDLE | S_NEW_INPUT | S_NEW_RESULT =>
 100                                 null;
 101                 end case;
 102         end process;
 103 end architecture beh;