top-level: ansatz fuer minimales setup inkl. geruest fuer history- und displaymodul...

diff --git a/quartus/project_gen.tcl b/quartus/project_gen.tcl
index 40dc720af45b0a98cd0b412107e31cc48bfece96..62d62a359b02894a3ffb849a3a53efb6d2a30cae 100644 (file)
--- a/quartus/project_gen.tcl
+++ b/quartus/project_gen.tcl
@@ -31,17 +31,76 @@ if {$make_assignments} {
        set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
        set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
 
-       #set_global_assignment -name TOP_LEVEL_ENTITY calc
-       set_global_assignment -name TOP_LEVEL_ENTITY scanner
+       #set_global_assignment -name TOP_LEVEL_ENTITY scanner
+       #set_global_assignment -name VHDL_FILE ../../src/gen_pkg.vhd
+       #set_global_assignment -name VHDL_FILE ../../src/alu.vhd
+       #set_global_assignment -name VHDL_FILE ../../src/parser.vhd
+       #set_global_assignment -name VHDL_FILE ../../src/scanner.vhd
+
+
+       #include source files
+       set_global_assignment -name TOP_LEVEL_ENTITY calc
        set_global_assignment -name VHDL_FILE ../../src/gen_pkg.vhd
-       #set_global_assignment -name VHDL_FILE ../../src/calc.vhd
+       set_global_assignment -name VHDL_FILE ../../src/calc.vhd
        set_global_assignment -name VHDL_FILE ../../src/alu.vhd
        set_global_assignment -name VHDL_FILE ../../src/parser.vhd
        set_global_assignment -name VHDL_FILE ../../src/scanner.vhd
+       set_global_assignment -name VHDL_FILE ../../src/vpll.vhd
+       
+       #vga ip-core
+       set_global_assignment -name VHDL_FILE ../../src/textmode_vga/console_sm.vhd
+       set_global_assignment -name VHDL_FILE ../../src/textmode_vga/console_sm_beh.vhd
+       set_global_assignment -name VHDL_FILE ../../src/textmode_vga/console_sm_sync.vhd
+       set_global_assignment -name VHDL_FILE ../../src/textmode_vga/console_sm_sync_beh.vhd
+       set_global_assignment -name VHDL_FILE ../../src/textmode_vga/font_pkg.vhd
+       set_global_assignment -name VHDL_FILE ../../src/textmode_vga/font_rom.vhd
+       set_global_assignment -name VHDL_FILE ../../src/textmode_vga/font_rom_beh.vhd
+       set_global_assignment -name VHDL_FILE ../../src/textmode_vga/interval.vhd
+       set_global_assignment -name VHDL_FILE ../../src/textmode_vga/interval_beh.vhd
+       set_global_assignment -name VHDL_FILE ../../src/textmode_vga/textmode_vga.vhd
+       set_global_assignment -name VHDL_FILE ../../src/textmode_vga/textmode_vga_component_pkg.vhd
+       set_global_assignment -name VHDL_FILE ../../src/textmode_vga/textmode_vga_h_sm.vhd
+       set_global_assignment -name VHDL_FILE ../../src/textmode_vga/textmode_vga_h_sm_beh.vhd
+       set_global_assignment -name VHDL_FILE ../../src/textmode_vga/textmode_vga_pkg.vhd
+       set_global_assignment -name VHDL_FILE ../../src/textmode_vga/textmode_vga_struct.vhd
+       set_global_assignment -name VHDL_FILE ../../src/textmode_vga/textmode_vga_v_sm.vhd
+       set_global_assignment -name VHDL_FILE ../../src/textmode_vga/textmode_vga_v_sm_beh.vhd
+       set_global_assignment -name VHDL_FILE ../../src/textmode_vga/video_memory.vhd
+       set_global_assignment -name VHDL_FILE ../../src/textmode_vga/video_memory_beh.vhd
+       set_global_assignment -name VHDL_FILE ../../src/textmode_vga/mjl_stratix/textmode_vga_platform_dependent_pkg.vhd
+       
+       #ps/2 ip-core
+       set_global_assignment -name VHDL_FILE ../../src/ps2/ps2_keyboard_controller.vhd
+       set_global_assignment -name VHDL_FILE ../../src/ps2/ps2_keyboard_controller_beh.vhd
+       set_global_assignment -name VHDL_FILE ../../src/ps2/ps2_keyboard_controller_pkg.vhd
+       set_global_assignment -name VHDL_FILE ../../src/ps2/ps2_transceiver.vhd
+       set_global_assignment -name VHDL_FILE ../../src/ps2/ps2_transceiver_beh.vhd
+       set_global_assignment -name VHDL_FILE ../../src/ps2/ps2_transceiver_pkg.vhd
+
+       #gen ip-core
+       set_global_assignment -name VHDL_FILE ../../src/math_pkg.vhd
 
+
+       #pin mapping/system
        set_location_assignment PIN_N3 -to sys_clk
        set_location_assignment PIN_AF17 -to sys_res_n
 
+       #vga
+       set_location_assignment PIN_F1 -to hsync_n
+       set_location_assignment PIN_F2 -to vsync_n
+       set_location_assignment E22 -to r[0]
+       set_location_assignment T4 -to r[1]
+       set_location_assignment T7 -to r[2]
+       set_location_assignment E23 -to g[0]
+       set_location_assignment T5 -to g[1]
+       set_location_assignment T24 -to g[2]
+       set_location_assignment E24 -to b[0]
+       set_location_assignment T6 -to b[1]
+
+       #ps/2
+       set_location_assignment Y26 -to ps2_clk
+       set_location_assignment E21 -to ps2_data
+
        set_global_assignment -name FMAX_REQUIREMENT "33.33 MHz" -section_id sys_clk
        set_instance_assignment -name CLOCK_SETTINGS sys_clk -to sys_clk
 

diff --git a/src/Makefile b/src/Makefile
index b0032333f20cf06c4de64475e81f49361c99ddc2..55a31144f240a56a97c38610e104bdf85bbee651 100644 (file)
--- a/src/Makefile
+++ b/src/Makefile
@@ -24,7 +24,7 @@ WORK := work
 # o source files der module
 # o reihenfolge ist wichtig
 # o keine testbechnes hier angeben
-SRCFILES := alu parser scanner
+SRCFILES := alu parser scanner display history
 
 # o files der packages
 # o keine testbechnes hier angeben

diff --git a/src/calc.vhd b/src/calc.vhd
index 7347002dcd823619e8d00e7ef18358d3f9a41645..922a2a6481d136a21d4a69424d92b93f28920334 100644 (file)
--- a/src/calc.vhd
+++ b/src/calc.vhd
@@ -1,63 +1,70 @@
--- TODO: dient im moment nur als "fake top entity"
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 use work.gen_pkg.all;
+use work.textmode_vga_component_pkg.all;
+use work.textmode_vga_pkg.all;
+use work.textmode_vga_platform_dependent_pkg.all;
+use work.ps2_keyboard_controller_pkg.all;
 
 entity calc is
-       port
-       (
+       port (
                sys_clk : in std_logic;
-               sys_res_n : in std_logic
+               sys_res_n : in std_logic;
+               -- btnA
+               -- TODO: pins
+               -- rs232
+               -- TODO: pins
+               -- vga
+               vsync_n : out std_logic;
+               hsync_n : out std_logic;
+               r : out std_logic_vector(RED_BITS - 1 downto 0);
+               g : out std_logic_vector(GREEN_BITS - 1 downto 0);
+               b : out std_logic_vector(BLUE_BITS - 1 downto 0);
+               -- ps/2
+               ps2_clk : inout std_logic;
+               ps2_data : inout std_logic
        );
 end entity calc;
 
 architecture top of calc is
-       component alu is
-               port
-               (
-                       sys_clk : in std_logic;
-                       sys_res_n : in std_logic;
-                       opcode : in alu_ops;
-                       op1 : in csigned;
-                       op2 : in csigned;
-                       op3 : out csigned;
-                       do_calc : in std_logic;
-                       calc_done : out std_logic
-               );
-       end component alu;
-
-       signal do_calc, calc_done : std_logic;
-       signal opcode : alu_ops;
-       signal op1, op2, op3 : csigned;
+       -- vga
+       signal vga_clk, free : std_logic;
+       signal command : std_logic_vector(COMMAND_SIZE - 1 downto 0);
+       signal command_data : std_logic_vector(3 * COLOR_SIZE + CHAR_SIZE -1 downto 0);
 begin
-       aluc : alu
-       port map
-       (
+       -- vga/ipcore
+       textmode_vga_inst : entity work.textmode_vga(struct)
+       generic map (
+               VGA_CLK_FREQ => 25000000,
+               BLINK_INTERVAL_MS => 500,
+               SYNC_STAGES => 2
+       )
+       port map (
                sys_clk => sys_clk,
                sys_res_n => sys_res_n,
-               do_calc => do_calc,
-               calc_done => calc_done,
-               op1 => op1,
-               op2 => op2,
-               op3 => op3,
-               opcode => opcode
+               command => command,
+               command_data => command_data,
+               free => free,
+               vga_clk => vga_clk,
+               vga_res_n => sys_res_n,
+               vsync_n => vsync_n,
+               hsync_n => hsync_n,
+               r => r,
+               g => g,
+               b => b
        );
 
-       process (sys_clk, sys_res_n)
-       begin
-               if sys_res_n = '0' then
-                       op1 <= (others => '0');
-                       opcode <= NOP;
-                       op2 <= (others => '0');
-                       do_calc <= '0';
-               elsif rising_edge(sys_clk) then
-                       op1 <= op3;
-                       opcode <= DIV;
-                       op2 <= to_signed(2,CBITS);
+       -- pll fuer vga
+       vpll_inst : entity work.vpll(syn)
+       port map (
+               inclk0 => sys_clk,
+               c0 => vga_clk
+       );
 
-                       do_calc <= calc_done;
-               end if;
-       end process;
+       -- TODO: display
+       -- TODO: history
+       -- TODO: scanner
+       -- TODO: ps/2
 end architecture top;
 

diff --git a/src/display.vhd b/src/display.vhd
new file mode 100644 (file)
index 0000000..f0a3cc0
--- /dev/null
+++ b/src/display.vhd
@@ -0,0 +1,103 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.gen_pkg.all;
+use work.textmode_vga_component_pkg.all;
+use work.textmode_vga_pkg.all;
+use work.textmode_vga_platform_dependent_pkg.all;
+
+entity display is
+       port (
+               sys_clk : in std_logic;
+               sys_res_n : in std_logic;
+               -- History
+               d_new_eingabe : in std_logic;
+               d_new_result : in std_logic;
+               d_zeile : out hzeile;
+               d_spalte : out hspalte;
+               d_get : out std_logic;
+               d_done : in std_logic;
+               d_char : in hbyte;
+               -- VGA
+               command : out std_logic_vector(7 downto 0);
+               command_data : out std_logic_vector(31 downto 0);
+               free : in std_logic
+       );
+end entity display;
+
+architecture beh of display is
+       type DISPLAY_STATE is (SIDLE, S_NEW_RESULT, S_NEW_INPUT);
+       signal state_int, state_next : DISPLAY_STATE;
+       signal d_zeile_int, d_zeile_next : hzeile;
+       signal d_spalte_int, d_spalte_next : hspalte;
+       signal d_get_int, d_get_next : std_logic;
+       signal command_int, command_next : std_logic_vector(7 downto 0);
+       signal command_data_int, command_data_next : std_logic_vector(31 downto 0);
+begin
+       d_zeile <= d_zeile_int;
+       d_spalte <= d_spalte_int;
+       d_get <= d_get_int;
+       command <= command_int;
+       command_data <= command_data_int;
+
+       process(sys_clk, sys_res_n)
+       begin
+               if sys_res_n = '0' then
+                       -- internal
+                       state_int <= SIDLE;
+                       -- out
+                       d_zeile_int <= (others => '0');
+                       d_spalte_int <= (others => '0');
+                       d_get_int <= '0';
+                       command_int <= COMMAND_NOP;
+                       command_data_int <= (others => '0');
+               elsif rising_edge(sys_clk) then
+                       -- internal
+                       state_int <= state_next;
+                       -- out
+                       d_zeile_int <= d_zeile_next;
+                       d_spalte_int <= d_spalte_next;
+                       d_get_int <= d_get_next;
+                       command_int <= command_next;
+                       command_data_int <= command_data_next;
+               end if;
+       end process;
+
+       -- next state
+       process(state_int, d_new_result, d_new_eingabe, d_done, free)
+       begin
+               state_next <= state_int;
+
+               case state_int is
+                       when SIDLE =>
+                               if free = '1' then
+                                       if d_new_eingabe = '1' then
+                                               state_next <= S_NEW_INPUT;
+                                       end if;
+                                       if d_new_result = '1' then
+                                               state_next <= S_NEW_RESULT;
+                                       end if;
+                               end if;
+                       when S_NEW_RESULT | S_NEW_INPUT =>
+                               if free = '0' then
+                                       state_next <= SIDLE;
+                               end if;
+               end case;
+       end process;
+
+       -- out
+       process(state_int, d_zeile_int, d_spalte_int, d_get_int, command_int,
+               command_data_int)
+       begin
+               d_zeile_next <= d_zeile_int;
+               d_spalte_next <= d_spalte_int;
+               d_get_next <= d_get_int;
+               command_next <= command_int;
+               command_data_next <= command_data_int;
+
+               case state_int is
+                       when SIDLE | S_NEW_INPUT | S_NEW_RESULT =>
+                               null;
+               end case;
+       end process;
+end architecture beh;

diff --git a/src/history.vhd b/src/history.vhd
new file mode 100644 (file)
index 0000000..3031c22
--- /dev/null
+++ b/src/history.vhd
@@ -0,0 +1,87 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.gen_pkg.all;
+
+entity history is
+       port (
+               sys_clk : in std_logic;
+               sys_res_n : in std_logic;
+               -- PC-komm
+               -- TODO: pins
+               -- Scanner
+               s_char : in hbyte;
+               s_take : in std_logic;
+               s_done : out std_logic;
+               s_backspace : in std_logic;
+               -- Display
+               d_new_eingabe : out std_logic;
+               d_new_result : out std_logic;
+               d_zeile : in hzeile;
+               d_spalte : in hspalte;
+               d_get : in std_logic;
+               d_done : out std_logic;
+               d_char : out hbyte
+               -- Parser
+               -- TODO: pins
+       );
+end entity history;
+
+architecture beh of history is
+       type HISTORY_STATE is (SIDLE);
+       signal state_int, state_next : HISTORY_STATE;
+       signal s_done_int, s_done_next : std_logic;
+       signal d_new_eingabe_int, d_new_eingabe_next : std_logic;
+       signal d_new_result_int, d_new_result_next : std_logic;
+       signal d_done_int, d_done_next : std_logic;
+       signal d_char_int, d_char_next : hbyte;
+begin
+       s_done <= s_done_int;
+       d_new_eingabe <= d_new_eingabe_int;
+       d_new_result <= d_new_result_int;
+       d_done <= d_done_int;
+       d_char <= d_char_int;
+
+       process(sys_clk, sys_res_n)
+       begin
+               if sys_res_n = '0' then
+                       -- internal
+                       state_int <= SIDLE;
+                       -- out
+                       s_done_int <= '0';
+                       d_new_result_int <= '0';
+                       d_new_eingabe_int <= '0';
+                       d_done_int <= '0';
+                       d_char_int <= (others => '0');
+               elsif rising_edge(sys_clk) then
+                       -- internal
+                       state_int <= state_next;
+                       -- out
+                       s_done_int <= s_done_next;
+                       d_new_result_int <= d_new_result_next;
+                       d_new_eingabe_int <= d_new_eingabe_next;
+                       d_done_int <= d_done_next;
+                       d_char_int <= d_char_next;
+               end if;
+       end process;
+
+       -- next state
+       process(state_int)
+       begin
+               state_next <= state_int;
+
+               case state_int is
+                       when SIDLE =>
+                               null;
+               end case;
+       end process;
+
+       -- out
+       process(state_int)
+       begin
+               case state_int is
+                       when SIDLE =>
+                               null;
+               end case;
+       end process;
+end architecture beh;

diff --git a/src/vpll.vhd b/src/vpll.vhd
new file mode 100644 (file)
index 0000000..dbb347f
--- /dev/null
+++ b/src/vpll.vhd
@@ -0,0 +1,274 @@
+-- megafunction wizard: %ALTPLL%\r
+-- GENERATION: STANDARD\r
+-- VERSION: WM1.0\r
+-- MODULE: altpll \r
+\r
+-- ============================================================\r
+-- File Name: vpll.vhd\r
+-- Megafunction Name(s):\r
+--                     altpll\r
+-- ============================================================\r
+-- ************************************************************\r
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\r
+--\r
+-- 4.1 Build 181 06/29/2004 SJ Full Version\r
+-- ************************************************************\r
+\r
+\r
+--Copyright (C) 1991-2004 Altera Corporation\r
+--Any  megafunction  design,  and related netlist (encrypted  or  decrypted),\r
+--support information,  device programming or simulation file,  and any other\r
+--associated  documentation or information  provided by  Altera  or a partner\r
+--under  Altera's   Megafunction   Partnership   Program  may  be  used  only\r
+--to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any\r
+--other  use  of such  megafunction  design,  netlist,  support  information,\r
+--device programming or simulation file,  or any other  related documentation\r
+--or information  is prohibited  for  any  other purpose,  including, but not\r
+--limited to  modification,  reverse engineering,  de-compiling, or use  with\r
+--any other  silicon devices,  unless such use is  explicitly  licensed under\r
+--a separate agreement with  Altera  or a megafunction partner.  Title to the\r
+--intellectual property,  including patents,  copyrights,  trademarks,  trade\r
+--secrets,  or maskworks,  embodied in any such megafunction design, netlist,\r
+--support  information,  device programming or simulation file,  or any other\r
+--related documentation or information provided by  Altera  or a megafunction\r
+--partner, remains with Altera, the megafunction partner, or their respective\r
+--licensors. No other licenses, including any licenses needed under any third\r
+--party's intellectual property, are provided herein.\r
+\r
+\r
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.all;\r
+\r
+LIBRARY altera_mf;\r
+USE altera_mf.altera_mf_components.all;\r
+\r
+ENTITY vpll IS\r
+       PORT\r
+       (\r
+               inclk0          : IN STD_LOGIC  := '0';\r
+--             pllena          : IN STD_LOGIC  := '1';\r
+--             areset          : IN STD_LOGIC  := '0';\r
+               c0              : OUT STD_LOGIC \r
+--             locked          : OUT STD_LOGIC \r
+       );\r
+END vpll;\r
+\r
+\r
+ARCHITECTURE SYN OF vpll IS\r
+\r
+       SIGNAL sub_wire0        : STD_LOGIC_VECTOR (5 DOWNTO 0);\r
+       SIGNAL sub_wire1        : STD_LOGIC ;\r
+       SIGNAL sub_wire2        : STD_LOGIC ;\r
+       SIGNAL sub_wire3_bv     : BIT_VECTOR (0 DOWNTO 0);\r
+       SIGNAL sub_wire3        : STD_LOGIC_VECTOR (0 DOWNTO 0);\r
+       SIGNAL sub_wire4        : STD_LOGIC_VECTOR (5 DOWNTO 0);\r
+       SIGNAL sub_wire5_bv     : BIT_VECTOR (0 DOWNTO 0);\r
+       SIGNAL sub_wire5        : STD_LOGIC_VECTOR (0 DOWNTO 0);\r
+       SIGNAL sub_wire6        : STD_LOGIC ;\r
+       SIGNAL sub_wire7        : STD_LOGIC_VECTOR (1 DOWNTO 0);\r
+       SIGNAL sub_wire8        : STD_LOGIC_VECTOR (3 DOWNTO 0);\r
+\r
+signal pllena_int : std_logic;\r
+signal areset_int : std_logic;\r
+signal locked : std_logic;\r
+\r
+       COMPONENT altpll\r
+       GENERIC (\r
+               bandwidth_type          : STRING;\r
+               clk0_duty_cycle         : NATURAL;\r
+               lpm_type                : STRING;\r
+               clk0_multiply_by                : NATURAL;\r
+               invalid_lock_multiplier         : NATURAL;\r
+               inclk0_input_frequency          : NATURAL;\r
+               gate_lock_signal                : STRING;\r
+               clk0_divide_by          : NATURAL;\r
+               pll_type                : STRING;\r
+               valid_lock_multiplier           : NATURAL;\r
+               clk0_time_delay         : STRING;\r
+               spread_frequency                : NATURAL;\r
+               intended_device_family          : STRING;\r
+               operation_mode          : STRING;\r
+               compensate_clock                : STRING;\r
+               clk0_phase_shift                : STRING\r
+       );\r
+       PORT (\r
+                       clkena  : IN STD_LOGIC_VECTOR (5 DOWNTO 0);\r
+                       inclk   : IN STD_LOGIC_VECTOR (1 DOWNTO 0);\r
+                       pllena  : IN STD_LOGIC ;\r
+                       extclkena       : IN STD_LOGIC_VECTOR (3 DOWNTO 0);\r
+                       locked  : OUT STD_LOGIC ;\r
+                       areset  : IN STD_LOGIC ;\r
+                       clk     : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)\r
+       );\r
+       END COMPONENT;\r
+\r
+BEGIN\r
+       sub_wire3_bv(0 DOWNTO 0) <= "0";\r
+       sub_wire3    <= To_stdlogicvector(sub_wire3_bv);\r
+       sub_wire5_bv(0 DOWNTO 0) <= "0";\r
+       sub_wire5    <= NOT(To_stdlogicvector(sub_wire5_bv));\r
+       sub_wire1    <= sub_wire0(0);\r
+       c0    <= sub_wire1;\r
+       locked    <= sub_wire2;\r
+       sub_wire4    <= sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire5(0 DOWNTO 0);\r
+       sub_wire6    <= inclk0;\r
+       sub_wire7    <= sub_wire3(0 DOWNTO 0) & sub_wire6;\r
+       sub_wire8    <= sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0) & sub_wire3(0 DOWNTO 0);\r
+\r
+areset_int <= '0';\r
+pllena_int <= '1';\r
+\r
+       altpll_component : altpll\r
+       GENERIC MAP (\r
+               bandwidth_type => "AUTO",\r
+               clk0_duty_cycle => 50,\r
+               lpm_type => "altpll",\r
+               clk0_multiply_by => 5435,\r
+               invalid_lock_multiplier => 5,\r
+               inclk0_input_frequency => 30003,\r
+               gate_lock_signal => "NO",\r
+               clk0_divide_by => 6666,\r
+               pll_type => "AUTO",\r
+               valid_lock_multiplier => 1,\r
+               clk0_time_delay => "0",\r
+               spread_frequency => 0,\r
+               intended_device_family => "Stratix",\r
+               operation_mode => "NORMAL",\r
+               compensate_clock => "CLK0",\r
+               clk0_phase_shift => "0"\r
+       )\r
+       PORT MAP (\r
+               clkena => sub_wire4,\r
+               inclk => sub_wire7,\r
+               pllena => pllena_int,\r
+               extclkena => sub_wire8,\r
+               areset => areset_int,\r
+               clk => sub_wire0,\r
+               locked => sub_wire2\r
+       );\r
+\r
+\r
+\r
+END SYN;\r
+\r
+-- ============================================================\r
+-- CNX file retrieval info\r
+-- ============================================================\r
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"\r
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"\r
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"\r
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"\r
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"\r
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "1"\r
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"\r
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"\r
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"\r
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"\r
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"\r
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"\r
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"\r
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"\r
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"\r
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"\r
+-- Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000"\r
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"\r
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"\r
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"\r
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"\r
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"\r
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"\r
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"\r
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"\r
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"\r
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"\r
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"\r
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"\r
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"\r
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"\r
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"\r
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "33.330"\r
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"\r
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"\r
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"\r
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"\r
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"\r
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"\r
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"\r
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"\r
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"\r
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"\r
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"\r
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"\r
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"\r
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"\r
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"\r
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"\r
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "299.970"\r
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"\r
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"\r
+-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "1"\r
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.330"\r
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"\r
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"\r
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "27.175"\r
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"\r
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"\r
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"\r
+-- Retrieval info: PRIVATE: DEV_FAMILY STRING "Stratix"\r
+-- Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"\r
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"\r
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"\r
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"\r
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"\r
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"\r
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"\r
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"\r
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"\r
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"\r
+-- Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "9"\r
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\r
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"\r
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"\r
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"\r
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5435"\r
+-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"\r
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30003"\r
+-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"\r
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "6666"\r
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"\r
+-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"\r
+-- Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0"\r
+-- Retrieval info: CONSTANT: SPREAD_FREQUENCY NUMERIC "0"\r
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix"\r
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"\r
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"\r
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"\r
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"\r
+-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"\r
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"\r
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"\r
+-- Retrieval info: USED_PORT: pllena 0 0 0 0 INPUT VCC "pllena"\r
+-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"\r
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT VCC "@inclk[1..0]"\r
+-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"\r
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0\r
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0\r
+-- Retrieval info: CONNECT: @extclkena 0 0 1 1 GND 0 0 0 0\r
+-- Retrieval info: CONNECT: @clkena 0 0 1 4 GND 0 0 0 0\r
+-- Retrieval info: CONNECT: @clkena 0 0 1 1 GND 0 0 0 0\r
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0\r
+-- Retrieval info: CONNECT: @pllena 0 0 0 0 pllena 0 0 0 0\r
+-- Retrieval info: CONNECT: @extclkena 0 0 1 2 GND 0 0 0 0\r
+-- Retrieval info: CONNECT: @clkena 0 0 1 5 GND 0 0 0 0\r
+-- Retrieval info: CONNECT: @clkena 0 0 1 2 GND 0 0 0 0\r
+-- Retrieval info: CONNECT: @clkena 0 0 1 0 VCC 0 0 0 0\r
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0\r
+-- Retrieval info: CONNECT: @extclkena 0 0 1 3 GND 0 0 0 0\r
+-- Retrieval info: CONNECT: @extclkena 0 0 1 0 GND 0 0 0 0\r
+-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0\r
+-- Retrieval info: CONNECT: @clkena 0 0 1 3 GND 0 0 0 0\r
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.vhd TRUE FALSE\r
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.inc FALSE FALSE\r
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.cmp TRUE FALSE\r
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll.bsf TRUE\r
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vpll_inst.vhd TRUE FALSE\r